1. [IR] Add NoUndef attribute to (details)
  2. [SampleFDO] Enhance profile remapping support for searching inline instance (details)
  3. AMDGPU: Don't assert on misaligned DS read2/write2 offsets (details)
  4. [Hexagon] Implement llvm.masked.load and for HVX (details)
  5. [SVE] Remove calls to VectorType::getNumElements from clang (details)
  6. [Polly] Use llvm::function_ref. NFC. (details)
  7. [Polly] Inline ShoulDelete lambda. NFC. (details)
  8. [LTO] Don't apply LTOPostLink module flag during writeMergedModule (details)
  9. [MC][SVE] Fix data operand for instruction alias of `st1d`. (details)
  10. [gn build] Manually port ed07e1fe (details)
  11. [InstSimplify] Simplify to vector constants when possible (details)
  12. Add cmake test support for LLJITWithThinLTOSummaries to make sure (details)
  13. [mlir] NFC: fix trivial typos in documents (details)
Commit 684b43c0cfb1092a65c237b39d0662bfe0a2c97a by aqjune
[IR] Add NoUndef attribute to

This patch adds NoUndef to
The attribute is attached to llvm.assume's operand, because llvm.assume(undef)
is UB.
It is attached to pointer operands of several memory accessing intrinsics
as well.

This change makes ValueTracking::getGuaranteedNonPoisonOps' intrinsic check
unnecessary, so it is removed.

Reviewed By: jdoerfert

Differential Revision:
The file was modifiedllvm/test/Transforms/EarlyCSE/invariant.start.ll (diff)
The file was modifiedllvm/utils/TableGen/CodeGenIntrinsics.h (diff)
The file was modifiedllvm/lib/Analysis/ValueTracking.cpp (diff)
The file was modifiedllvm/utils/TableGen/IntrinsicEmitter.cpp (diff)
The file was modifiedmlir/test/Target/llvmir-intrinsics.mlir (diff)
The file was modifiedllvm/include/llvm/IR/ (diff)
The file was modifiedllvm/utils/TableGen/CodeGenTarget.cpp (diff)
Commit c67ccf5fafc8c035f152ce30115bbdacf23530d5 by wmi
[SampleFDO] Enhance profile remapping support for searching inline instance
and indirect call promotion candidate.

Profile remapping is a feature to match a function in the module with its
profile in sample profile if the function name and the name in profile look
different but are equivalent using given remapping rules. This is a useful
feature to keep the performance stable by specifying some remapping rules
when sampleFDO targets are going through some large scale function signature

However, currently profile remapping support is only valid for outline
function profile in SampleFDO. It cannot match a callee with an inline
instance profile if they have different but equivalent names. We found
that without the support for inline instance profile, remapping is less
effective for some large scale change.

To add that support, before any remapping lookup happens, all the names
in the profile will be inserted into remapper and the Key to the name
mapping will be recorded in a map called NameMap in the remapper. During
name lookup, a Key will be returned for the given name and it will be used
to extract an equivalent name in the profile from NameMap. So with the help
of the NameMap, we can translate any given name to an equivalent name in
the profile if it exists. Whenever we try to match a name in the module to
a name in the profile, we will try the match with the original name first,
and if it doesn't match, we will use the equivalent name got from remapper
to try the match for another time. In this way, the patch can enhance the
profile remapping support for searching inline instance and searching
indirect call promotion candidate.

In a planned large scale change of int64 type (long long) to int64_t (long),
we found the performance of a google internal benchmark degraded by 2% if
nothing was done. If existing profile remapping was enabled, the performance
degradation dropped to 1.2%. If the profile remapping with the current patch
was enabled, the performance degradation further dropped to 0.14% (Note the
experiment was done before searching indirect call promotion candidate was
added. We hope with the remapping support of searching indirect call promotion
candidate, the degradation can drop to 0% in the end. It will be evaluated
post commit).

Differential Revision:
The file was addedllvm/test/Transforms/SampleProfile/Inputs/
The file was modifiedllvm/include/llvm/ProfileData/SampleProf.h (diff)
The file was modifiedllvm/unittests/ProfileData/SampleProfTest.cpp (diff)
The file was modifiedllvm/lib/Transforms/IPO/SampleProfile.cpp (diff)
The file was modifiedllvm/lib/ProfileData/SampleProfReader.cpp (diff)
The file was addedllvm/test/Transforms/SampleProfile/remap-2.ll
The file was modifiedllvm/lib/ProfileData/SampleProf.cpp (diff)
The file was modifiedllvm/include/llvm/ProfileData/SampleProfReader.h (diff)
Commit f78687df9b790b4f4177a72cbd25b49d14c437b4 by Matthew.Arsenault
AMDGPU: Don't assert on misaligned DS read2/write2 offsets

This would assert with unaligned DS access enabled. The offset may not
be aligned. Theoretically the pattern predicate should check the
memory alignment, although it is possible to have the memory be
aligned but not the immediate offset.

In this case I would expect it to use ds_{read|write}_b64 with
unaligned access, but am not clear if there's a reason it doesn't.
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/ds_write2.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/ds_read2.ll (diff)
Commit e15143d31bca3973db51714af6361f3e77a9e058 by kparzysz
[Hexagon] Implement llvm.masked.load and for HVX
The file was modifiedllvm/lib/Target/Hexagon/ (diff)
The file was modifiedllvm/lib/Target/Hexagon/HexagonTargetTransformInfo.cpp (diff)
The file was modifiedllvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp (diff)
The file was modifiedllvm/test/CodeGen/Hexagon/store-vector-pred.ll (diff)
The file was modifiedllvm/lib/Target/Hexagon/HexagonTargetTransformInfo.h (diff)
The file was addedllvm/test/CodeGen/Hexagon/autohvx/masked-vmem-basic.ll
The file was modifiedllvm/test/CodeGen/Hexagon/hvx-bitcast-v64i1.ll (diff)
The file was modifiedllvm/lib/Target/Hexagon/HexagonISelLowering.h (diff)
The file was modifiedllvm/lib/Target/Hexagon/HexagonInstrInfo.cpp (diff)
Commit 19e883fc59887e98a49ec03557ad2b6bc5537e03 by ctetreau
[SVE] Remove calls to VectorType::getNumElements from clang

Reviewed By: RKSimon

Differential Revision:
The file was modifiedclang/lib/CodeGen/CGExpr.cpp (diff)
The file was modifiedclang/lib/CodeGen/CGAtomic.cpp (diff)
The file was modifiedclang/lib/CodeGen/CGBuiltin.cpp (diff)
The file was modifiedclang/lib/CodeGen/CGExprScalar.cpp (diff)
The file was modifiedclang/lib/CodeGen/SwiftCallingConv.cpp (diff)
Commit c971b53b22a5cd43b54bf4773fe3c59ea1b805fb by llvm-project
[Polly] Use llvm::function_ref. NFC.

As suggested by David Blaike at
The file was modifiedpolly/lib/Analysis/ScopInfo.cpp (diff)
The file was modifiedpolly/include/polly/ScopInfo.h (diff)
Commit 6538fff37245921a0983d94c08af7e6cc120b3a9 by llvm-project
[Polly] Inline ShoulDelete lambda. NFC.

As suggested by David Blaikie at
The file was modifiedpolly/lib/Transform/Simplify.cpp (diff)
The file was modifiedpolly/lib/Analysis/ScopInfo.cpp (diff)
Commit 476ca330894bf42feeb6c13547d14c821f6b8e0a by Steven Wu
[LTO] Don't apply LTOPostLink module flag during writeMergedModule

For `ld64` which uses legacy LTOCodeGenerator, it relies on
writeMergedModule to perform `ld -r` (generates a linked object file).
If all the inputs to `ld -r` is fullLTO bitcode, `ld64` will linked the
bitcode module, internalize all the symbols and write out another
fullLTO bitcode object file. This bitcode file doesn't have all the
bitcode inputs and it should not have LTOPostLink module flag. It will
also cause error when this bitcode object file is linked with other LTO
object file.
Fix the issue by not applying LTOPostLink flag during writeMergedModule
function. The flag should only be added when all the bitcode are linked
and ready to be optimized.


Reviewed By: tejohnson

Differential Revision:
The file was modifiedllvm/test/LTO/ARM/lto-linking-metadata.ll (diff)
The file was modifiedllvm/lib/LTO/LTOCodeGenerator.cpp (diff)
The file was modifiedllvm/tools/llvm-lto/llvm-lto.cpp (diff)
Commit 61dfa009579f10e75ef110a80c3e5b657ec5867a by francesco.petrogalli
[MC][SVE] Fix data operand for instruction alias of `st1d`.

The version of `st1d` that operates with vector plus immediate
addressing mode uses the alias `st1d { <Zn>.d }, <Pg>, [<Za>.d]` for
rendering `st1d { <Zn>.d }, <Pg>, [<Za>.d, #0]`. The disassembler was
generating `<Zn>.s` instead of `<Zn>.d>`.

Differential Revision:
The file was modifiedllvm/test/MC/AArch64/SVE/st1w.s (diff)
The file was modifiedllvm/lib/Target/AArch64/ (diff)
The file was modifiedllvm/test/MC/AArch64/SVE/st1d.s (diff)
The file was modifiedllvm/test/MC/AArch64/SVE/st1b.s (diff)
The file was modifiedllvm/test/MC/AArch64/SVE/st1h.s (diff)
Commit 1446c1801deaf7a38221b45662f2e17fa1d5e8f0 by aeubanks
[gn build] Manually port ed07e1fe
The file was modifiedllvm/utils/gn/secondary/llvm/include/llvm/Config/ (diff)
Commit 098d3f98276de90b6e1468031bd3858615240bb7 by aeubanks
[InstSimplify] Simplify to vector constants when possible

InstSimplify should do all transformations that ConstProp does, but
one thing that ConstProp does that InstSimplify wouldn't is inline
vector instructions that are constants, e.g. into a ret.

Previously vector instructions wouldn't be inlined in InstSimplify
because llvm::Simplify*Instruction() would return nullptr for specific
instructions, such as vector instructions that were actually constants,
if it couldn't simplify them.

This changes SimplifyInsertElementInst, SimplifyExtractElementInst, and
SimplifyShuffleVectorInst to return a vector constant when possible.

Reviewed By: efriedma

Differential Revision:
The file was modifiedllvm/test/Analysis/ConstantFolding/vscale-shufflevector.ll (diff)
The file was modifiedllvm/test/Transforms/InstSimplify/vscale.ll (diff)
The file was modifiedllvm/lib/Analysis/InstructionSimplify.cpp (diff)
Commit ea7b1c79f73d8def5d806ae79dea125d146ac864 by echristo
Add cmake test support for LLJITWithThinLTOSummaries to make sure
it's being built and called (and substituted).
The file was modifiedllvm/test/CMakeLists.txt (diff)
The file was modifiedllvm/test/ (diff)
Commit 603a8a60ba444eb7fc77f0b31dd063a7583df2c4 by ishizaki
[mlir] NFC: fix trivial typos in documents

Reviewed By: mravishankar

Differential Revision:
The file was modifiedmlir/docs/Rationale/ (diff)
The file was modifiedmlir/docs/ (diff)
The file was modifiedmlir/docs/Dialects/ (diff)
The file was modifiedmlir/docs/ (diff)
The file was modifiedmlir/docs/ (diff)