SuccessChanges

Summary

  1. [FPEnv] Partially implement #pragma STDC FENV_ROUND (details)
  2. [analyzer][StdLibraryFunctionsChecker] Do not match based on the restrict qualifier in C++ (details)
  3. [llvm-readobj/elf] - Refine signature of print*Reloc methods. (details)
  4. MIRFormatter.h - remove MachineInstr.h include. NFC. (details)
  5. [llvm-readelf/obj] - Use `RelSymbol<ELFT>` instead of std::pair. NFCI. (details)
  6. [ARM] Fold predicate_cast(load) into vldr p0 (details)
  7. [X86] Make lowerShuffleAsLanePermuteAndPermute use sublanes on AVX2 (details)
Commit a633da5391b0e42c0185132e8b532ae9bc34489f by sepavloff
[FPEnv] Partially implement #pragma STDC FENV_ROUND

This change implements pragma STDC FENV_ROUND, which is introduced by
the extension to standard (TS 18661-1). The pragma is implemented only
in frontend, it sets apprpriate state of FPOptions stored in Sema. Use
of these bits in constant evaluation adn/or code generator is not in the
scope of this change.

Parser issues warning on unsuppored pragma when it encounteres pragma
STDC FENV_ROUND, however it makes syntax checks and updates Sema state
as if the pragma were supported.

Primary purpose of the partial implementation is to facilitate
development of non-default floating poin environment. Previously a
developer cannot set non-default rounding mode in sources, this mades
preparing tests for say constant evaluation  substantially complicated.

Differential Revision: https://reviews.llvm.org/D86921
The file was addedclang/test/Parser/pragma-fenv_round.c
The file was modifiedclang/include/clang/Parse/Parser.h (diff)
The file was modifiedclang/lib/Sema/SemaAttr.cpp (diff)
The file was modifiedclang/include/clang/Sema/Sema.h (diff)
The file was modifiedclang/lib/Parse/ParsePragma.cpp (diff)
The file was modifiedclang/test/AST/ast-dump-fpfeatures.cpp (diff)
The file was modifiedclang/lib/Parse/Parser.cpp (diff)
The file was modifiedclang/include/clang/Basic/DiagnosticParseKinds.td (diff)
The file was modifiedclang/lib/Parse/ParseStmt.cpp (diff)
The file was modifiedclang/include/clang/Basic/TokenKinds.def (diff)
Commit fe0972d3e4a65b4c5f5fa602b17ad30e463050b3 by gabor.marton
[analyzer][StdLibraryFunctionsChecker] Do not match based on the restrict qualifier in C++

The "restrict" keyword is illegal in C++, however, many libc
implementations use the "__restrict" compiler intrinsic in functions
prototypes. The "__restrict" keyword qualifies a type as a restricted type
even in C++.
In case of any non-C99 languages, we don't want to match based on the
restrict qualifier because we cannot know if the given libc implementation
qualifies the paramter type or not.

Differential Revision: https://reviews.llvm.org/D87097
The file was modifiedclang/lib/StaticAnalyzer/Checkers/StdLibraryFunctionsChecker.cpp (diff)
The file was addedclang/test/Analysis/std-c-library-functions-restrict.c
The file was addedclang/test/Analysis/std-c-library-functions-restrict.cpp
Commit b7c181098675eb75bc79a9b38891ee88e56a9103 by grimar
[llvm-readobj/elf] - Refine signature of print*Reloc methods.

This makes the interface cleaner and slightly improves messages
reported.

Differential revision: https://reviews.llvm.org/D87086
The file was modifiedllvm/test/tools/llvm-readobj/ELF/relocation-errors.test (diff)
The file was modifiedllvm/tools/llvm-readobj/ELFDumper.cpp (diff)
Commit 3a1308be051711473e4cdd4aa12c70070991f648 by llvm-dev
MIRFormatter.h - remove MachineInstr.h include. NFC.

Use forward declarations and include the inner dependencies directly.
The file was modifiedllvm/include/llvm/CodeGen/MIRFormatter.h (diff)
Commit 0faf3930c405c320d8ed210aa0b44ef608e208da by grimar
[llvm-readelf/obj] - Use `RelSymbol<ELFT>` instead of std::pair. NFCI.

We have the `RelSymbol<ELFT>` struct and can use it instead
of `std::pair<const Elf_Sym *, std::string>` in a few methods.
This is a bit cleaner.

Differential revision: https://reviews.llvm.org/D87092
The file was modifiedllvm/tools/llvm-readobj/ELFDumper.cpp (diff)
Commit 294c0cc3ebad969819be4b5b8d091418b0704595 by david.green
[ARM] Fold predicate_cast(load) into vldr p0

This adds a simple tablegen pattern for folding predicate_cast(load)
into vldr p0, providing the alignment and offset are correct.

Differential Revision: https://reviews.llvm.org/D86702
The file was modifiedllvm/test/CodeGen/Thumb2/mve-pred-loadstore.ll (diff)
The file was modifiedllvm/lib/Target/ARM/ARMInstrMVE.td (diff)
Commit 740625fecd1a4cd8e5521bd1c98627eca6f7565d by llvm-dev
[X86] Make lowerShuffleAsLanePermuteAndPermute use sublanes on AVX2

Extends lowerShuffleAsLanePermuteAndPermute to search for opportunities to use vpermq (64-bit cross-lane shuffle) and vpermd (32-bit cross-lane shuffle) to get elements into the correct lane, in addition to the 128-bit full-lane permutes it previously searched for.

This is especially helpful in cross-lane byte shuffles, where the alternative tends to be "vpshufb both lanes separately and blend them with a vpblendvb", which is very expensive, especially on Haswell where vpblendvb uses the same execution port as all the shuffles.

Addresses PR47262

Patch By: @TellowKrinkle (TellowKrinkle)

Differential Revision: https://reviews.llvm.org/D86429
The file was modifiedllvm/test/CodeGen/X86/vector-shuffle-256-v16.ll (diff)
The file was modifiedllvm/test/CodeGen/X86/vector-shuffle-256-v32.ll (diff)
The file was modifiedllvm/test/CodeGen/X86/vector-shuffle-512-v32.ll (diff)
The file was modifiedllvm/test/CodeGen/X86/oddshuffles.ll (diff)
The file was modifiedllvm/test/CodeGen/X86/vector-shuffle-combining-avx2.ll (diff)
The file was modifiedllvm/test/CodeGen/X86/vector-shuffle-combining.ll (diff)
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp (diff)