SuccessChanges

Summary

  1. [GlobalISel] Rewrite the elide-br-by-swapping-icmp-ops combine to do less. (details)
  2. [GlobalISel][IRTranslator] Generate better conditional branch lowering. (details)
  3. [X86] Add tests for minnum/maxnum with constant NaN (NFC) (details)
Commit cc76da7adab71f0b6559ea13069f899b2ecbf70c by Amara Emerson
[GlobalISel] Rewrite the elide-br-by-swapping-icmp-ops combine to do less.

This combine previously tried to take sequences like:
  %cond = G_ICMP pred, a, b
  G_BRCOND %cond, %truebb
  G_BR %falsebb
%truebb:
  ...
%falsebb:
  ...

and by inverting the compare predicate and swapping branch targets, delete the
G_BR and instead have a single conditional branch to the falsebb. Since in an
earlier patch we have a combine to fold not(icmp) into just an inverted icmp,
we don't need this combine to do as much. This patch instead generalizes the
combine by just looking for:
  G_BRCOND %cond, %truebb
  G_BR %falsebb
%truebb:
  ...
%falsebb:
  ...

and then inverting the condition using a not (xor). The xor can be folded away
in a separate combine. This change also lets us avoid some optimization code
in the IRTranslator.

I also think that deleting G_BRs in the combiner is unnecessary. That's
something that targets can decide to do at selection time and could simplify
generic code in future.

Differential Revision: https://reviews.llvm.org/D86664
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/urem.i64.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.is.shared.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/bool-legalization.ll (diff)
The file was modifiedllvm/lib/CodeGen/GlobalISel/Utils.cpp (diff)
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUCombine.td (diff)
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-br.mir (diff)
The file was modifiedllvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp (diff)
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/select-constant.mir (diff)
The file was modifiedllvm/include/llvm/Target/GlobalISel/Combine.td (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.is.private.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/localizer.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/srem.i64.ll (diff)
The file was modifiedllvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/udiv.i64.ll (diff)
The file was removedllvm/test/CodeGen/AArch64/GlobalISel/const-0.ll
The file was modifiedllvm/include/llvm/CodeGen/GlobalISel/Utils.h (diff)
The file was modifiedllvm/lib/Target/AArch64/AArch64Combine.td (diff)
Commit 467a07128533276e3457b72a775e43190bdc1071 by Amara Emerson
[GlobalISel][IRTranslator] Generate better conditional branch lowering.

This is a port of the functionality from SelectionDAG, which tries to find
a tree of conditions from compares that are then combined using OR or AND,
before using that result as the input to a branch. Instead of naively
lowering the code as is, this change converts that into a sequence of
conditional branches on the sub-expressions of the tree.

Like SelectionDAG, we re-use the case block codegen functionality from
the switch lowering utils, which causes us to generate some different code.
The result of which I've tried to mitigate in earlier combine patches.

Differential Revision: https://reviews.llvm.org/D86665
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-switch.ll (diff)
The file was modifiedllvm/lib/CodeGen/GlobalISel/IRTranslator.cpp (diff)
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/long_ambiguous_chain_s64.ll (diff)
The file was modifiedllvm/include/llvm/CodeGen/GlobalISel/IRTranslator.h (diff)
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/long_ambiguous_chain_s32.ll (diff)
The file was addedllvm/test/CodeGen/AArch64/GlobalISel/irtranslator-condbr-lower-tree.ll
Commit 91656fcb57ec6878833aba615e1142225514e13b by nikita.ppv
[X86] Add tests for minnum/maxnum with constant NaN (NFC)
The file was modifiedllvm/test/CodeGen/X86/fminnum.ll (diff)
The file was modifiedllvm/test/CodeGen/X86/fmaxnum.ll (diff)