FailedChanges

Summary

  1. [mlir][Linalg] Small refactoring of ConvOpVectorization (details)
  2. [clang] Disallow fbasic-block-sections on non-ELF, non-x86 targets. (details)
  3. [ARM] Tail predicate VQDMULH and VQRDMULH (details)
  4. [SCEV] Constant expansion cost at minsize (details)
  5. [mlir] [VectorOps] Enable 32-bit index optimizations (details)
Commit fea175b59fbdf5d2b95e8fd81ac043479f20fe10 by limo
[mlir][Linalg] Small refactoring of ConvOpVectorization

This commit addresses comments that were requested on D86619
after it was landed.

Differential Revision: https://reviews.llvm.org/D87354
The file was modifiedmlir/lib/Dialect/Linalg/Transforms/Vectorization.cpp (diff)
The file was modifiedmlir/include/mlir/Dialect/Linalg/Transforms/Transforms.h (diff)
Commit 157cd93b48a90f484e9eb2ed9997e0372b9c7ebb by snehasishk
[clang] Disallow fbasic-block-sections on non-ELF, non-x86 targets.

Basic block sections is untested on other platforms and binary formats apart
from x86,elf. This patch emits a warning and drops the flag if the platform
and binary format are not compatible. Add a test to ensure that
specifying an incompatible target in the driver does not enable the
feature.

Differential Revision: https://reviews.llvm.org/D87426
The file was modifiedclang/test/Driver/fbasic-block-sections.c (diff)
The file was modifiedclang/lib/Driver/ToolChains/Clang.cpp (diff)
Commit 1919b650523282c550536b6b72eb4713cd6712f4 by sam.parker
[ARM] Tail predicate VQDMULH and VQRDMULH

Mark the family of instructions as valid for tail predication.

Differential Revision: https://reviews.llvm.org/D87348
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/remat-vctp.ll (diff)
The file was modifiedllvm/lib/Target/ARM/ARMInstrMVE.td (diff)
The file was modifiedllvm/unittests/Target/ARM/MachineInstrTest.cpp (diff)
Commit 0bdf8c9127244127aef3620a8ef1eb4d2be57dad by sam.parker
[SCEV] Constant expansion cost at minsize

As code size is the only thing we care about at minsize, query the
cost of materialising immediates when calculating the cost of a SCEV
expansion. We also modify the CostKind to TCK_CodeSize for minsize,
instead of RecipThroughput.

Differential Revision: https://reviews.llvm.org/D76434
The file was modifiedllvm/lib/Transforms/Utils/ScalarEvolutionExpander.cpp (diff)
The file was modifiedllvm/test/Transforms/IndVarSimplify/ARM/indvar-unroll-imm-cost.ll (diff)
Commit 3c42c0dcf631ad6b90e718df895c05f79718659f by ajcbik
[mlir] [VectorOps] Enable 32-bit index optimizations

Rationale:
After some discussion we decided that it is safe to assume 32-bit
indices for all subscripting in the vector dialect (it is unlikely
the dialect will be used; or even work; for such long vectors).
So rather than detecting specific situations that can exploit
32-bit indices with higher parallel SIMD, we just optimize it
by default, and let users that don't want it opt-out.

Reviewed By: nicolasvasilache, bkramer

Differential Revision: https://reviews.llvm.org/D87404
The file was modifiedmlir/include/mlir/Conversion/VectorToLLVM/ConvertVectorToLLVM.h (diff)
The file was modifiedmlir/include/mlir/Conversion/Passes.td (diff)
The file was modifiedmlir/test/Conversion/VectorToLLVM/vector-to-llvm.mlir (diff)