SuccessChanges

Summary

  1. Fix 132e57bc597bd3f50174b7d286c43f76b47f11c1 (details)
  2. [DAGCombiner] Fold fmin/fmax with INF / FLT_MAX (details)
  3. [InstCombine] Simplify select operand based on equality condition (details)
  4. [ms] [llvm-ml] Add missing built-in type aliases (details)
  5. [ms] [llvm-ml] Fix struct padding logic (details)
  6. [ms] [llvm-ml] Add support for size queries in MASM (details)
  7. [ms] [llvm-ml] Add basic support for SEH, including PROC FRAME (details)
  8. [ARM] Add more tests for vecreduce soft float legalization (NFC) (details)
  9. [Legalize][ARM][X86] Add float legalization for VECREDUCE (details)
Commit a3bc0401d436d8c7d2dd5b54e13b81333d53bdff by walter erquinigo
Fix 132e57bc597bd3f50174b7d286c43f76b47f11c1

Compile error found in
http://lab.llvm.org:8011/builders/lldb-x86_64-debian/builds/17403/steps/build/logs/stdio

Simple fix
The file was modifiedlldb/tools/lldb-vscode/lldb-vscode.cpp (diff)
Commit 8e69c3cde8eed94be226bdef1ff6cedda3a33bc4 by nikita.ppv
[DAGCombiner] Fold fmin/fmax with INF / FLT_MAX

Similar to D87415, this folds the various float min/max opcodes
with a constant INF or -INF operand, or FLT_MAX / -FLT_MAX operand
if the ninf flag is set. Some of the folds are only possible under
nnan.

The fminnum(X, INF) with nnan and fmaxnum(X, -INF) with nnan cases
are needed to improve the VECREDUCE_FMIN/FMAX lowerings on X86,
the rest is here for the sake of completeness.

Differential Revision: https://reviews.llvm.org/D87571
The file was modifiedllvm/test/CodeGen/ARM/fminmax-folds.ll (diff)
The file was modifiedllvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (diff)
Commit cfff88c03cf9e9b72906a41fd11e06721d54f293 by nikita.ppv
[InstCombine] Simplify select operand based on equality condition

For selects of the type X == Y ? A : B, check if we can simplify A
by using the X == Y equality and replace the operand if that's
possible. We already try to do this in InstSimplify, but will only
fold if the result of the simplification is the same as B, in which
case the select can be dropped entirely. Here the select will be
retained, just one operand simplified.

As we are performing an actual replacement here, we don't have
problems with refinement / poison values.

Differential Revision: https://reviews.llvm.org/D87480
The file was modifiedllvm/test/Transforms/InstCombine/rem.ll (diff)
The file was modifiedllvm/test/Transforms/InstCombine/select-binop-cmp.ll (diff)
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineSelect.cpp (diff)
The file was modifiedllvm/test/Transforms/InstCombine/select.ll (diff)
Commit da17e0d5c1dfabcba887e323b1aabc8cc4342cd6 by epastor
[ms] [llvm-ml] Add missing built-in type aliases

Add signed aliases for integral types, as well as the "DF" abbreviation for the FWORD type.

Reviewed By: thakis

Differential Revision: https://reviews.llvm.org/D87246
The file was addedllvm/test/tools/llvm-ml/builtin_types.test
The file was modifiedllvm/lib/MC/MCParser/MasmParser.cpp (diff)
Commit 7c44ee8e1937c7402a106f3fa6a356caa73a14e8 by epastor
[ms] [llvm-ml] Fix struct padding logic

MASM structs are end-padded to have size a multiple of the smaller of the requested alignment and the size of their largest field (taken recursively, if they have a field of STRUCT type).

This matches the behavior of ml.exe and ml64.exe. Our original implementation followed the MASM 6.0 documentation, which instead specified that MASM structs were padded to a multiple of their requested alignment.

Reviewed By: thakis

Differential Revision: https://reviews.llvm.org/D87248
The file was addedllvm/test/tools/llvm-ml/struct_alignment.test
The file was modifiedllvm/lib/MC/MCParser/MasmParser.cpp (diff)
Commit 20201dc76aaf68eb940eb14bfc6dd4983292fb79 by epastor
[ms] [llvm-ml] Add support for size queries in MASM

Add support for size inference, sizeof, typeof, and lengthof.

Reviewed By: thakis

Differential Revision: https://reviews.llvm.org/D86947
The file was modifiedllvm/lib/Target/X86/AsmParser/X86AsmParser.cpp (diff)
The file was addedllvm/test/tools/llvm-ml/size_inference.test
The file was modifiedllvm/lib/MC/MCParser/MasmParser.cpp (diff)
The file was modifiedllvm/include/llvm/MC/MCParser/MCTargetAsmParser.h (diff)
The file was modifiedllvm/include/llvm/MC/MCParser/MCAsmParser.h (diff)
The file was modifiedllvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp (diff)
The file was modifiedllvm/test/tools/llvm-ml/struct.test (diff)
The file was addedllvm/test/tools/llvm-ml/type_operators.test
The file was modifiedllvm/lib/MC/MCParser/AsmParser.cpp (diff)
Commit 23a2b03221c5664fefc658c3eb26e7b6ecd1a1e8 by epastor
[ms] [llvm-ml] Add basic support for SEH, including PROC FRAME

Add basic support for SEH, including PROC FRAME

Reviewed By: thakis

Differential Revision: https://reviews.llvm.org/D86948
The file was modifiedllvm/lib/Target/X86/AsmParser/X86AsmParser.cpp (diff)
The file was modifiedllvm/lib/MC/MCParser/MasmParser.cpp (diff)
The file was addedllvm/test/tools/llvm-ml/proc_frame.test
The file was modifiedllvm/lib/MC/MCParser/COFFMasmParser.cpp (diff)
The file was addedllvm/test/tools/llvm-ml/proc.test
Commit c0e3996bc7087a27e685c734480c0b92ff427d37 by nikita.ppv
[ARM] Add more tests for vecreduce soft float legalization (NFC)

This mirrors the existing fadd tests to fmul, fmin and fmax.
The file was addedllvm/test/CodeGen/ARM/vecreduce-fmax-legalization-soft-float.ll
The file was addedllvm/test/CodeGen/ARM/vecreduce-fmin-legalization-soft-float.ll
The file was addedllvm/test/CodeGen/ARM/vecreduce-fmul-legalization-soft-float.ll
Commit 53f36f06afbc02d1ab96e3789b41ddeafe31f40e by nikita.ppv
[Legalize][ARM][X86] Add float legalization for VECREDUCE

This adds SoftenFloatRes, PromoteFloatRes and SoftPromoteHalfRes
legalizations for VECREDUCE, to fill the remaining hole in the SDAG
legalization. These legalizations simply expand the reduction and
let it be recursively legalized. For the PromoteFloatRes case at
least it is possible to do better than that, but it's pretty tricky
(because we need to consider the interaction of three different
vector legalizations and the type promotion) and probably not
really worthwhile.

I haven't added ExpandFloatRes support, as I am not familiar with
ppc_fp128.

Differential Revision: https://reviews.llvm.org/D87569
The file was modifiedllvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp (diff)
The file was modifiedllvm/test/CodeGen/ARM/vecreduce-fadd-legalization-soft-float.ll (diff)
The file was modifiedllvm/lib/Target/ARM/ARMTargetTransformInfo.h (diff)
The file was modifiedllvm/test/CodeGen/X86/vector-reduce-fmin-nnan.ll (diff)
The file was modifiedllvm/test/CodeGen/X86/vector-reduce-fmax-nnan.ll (diff)
The file was modifiedllvm/test/CodeGen/ARM/vecreduce-fmax-legalization-soft-float.ll (diff)
The file was modifiedllvm/test/CodeGen/ARM/vecreduce-fmul-legalization-soft-float.ll (diff)
The file was modifiedllvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h (diff)
The file was modifiedllvm/test/CodeGen/ARM/vecreduce-fmin-legalization-soft-float.ll (diff)