FailedChanges

Summary

  1. [PowerPC] Implement Vector Count Mask Bits builtins in LLVM/Clang (details)
  2. [PowerPC] Add Set Boolean Condition Instruction Definitions and MC Tests (details)
  3. [AArch64][GlobalISel] clang-format AArch64LegalizerInfo.cpp. NFC. (details)
  4. [AArch64][GlobalISel] Make G_STORE <8 x s8> legal. (details)
  5. [lldb] Clarify docstring for SBBlock::IsInlined, NFC (details)
  6. [mlir][shape] Add `shape.cstr_require %bool` (details)
  7. [MLIR] Fix build failure due to https://reviews.llvm.org/D87059. (details)
Commit 2c3bc918db35913437e9302b77b11c08eb3ea6e4 by amy.kwan1
[PowerPC] Implement Vector Count Mask Bits builtins in LLVM/Clang

This patch implements the vec_cntm function prototypes in altivec.h in order to
utilize the vector count mask bits instructions introduced in Power10.

Differential Revision: https://reviews.llvm.org/D82726
The file was modifiedclang/lib/Headers/altivec.h (diff)
The file was modifiedllvm/test/CodeGen/PowerPC/p10-vector-mask-ops.ll (diff)
The file was modifiedllvm/lib/Target/PowerPC/PPCInstrPrefix.td (diff)
The file was modifiedclang/test/CodeGen/builtins-ppc-p10vector.c (diff)
The file was modifiedllvm/include/llvm/IR/IntrinsicsPowerPC.td (diff)
The file was modifiedclang/include/clang/Basic/BuiltinsPPC.def (diff)
Commit 6f3c0991bf9be48bd18a324c90e4cfcd37f82b96 by amy.kwan1
[PowerPC] Add Set Boolean Condition Instruction Definitions and MC Tests

This patch adds the instruction definitions and assembly/disassembly tests for
the set boolean condition instructions. This also includes the negative, and
reverse variants of the instruction.

Differential Revision: https://reviews.llvm.org/D86252
The file was modifiedllvm/test/MC/PowerPC/ppc64-encoding-ISA31.s (diff)
The file was modifiedllvm/test/MC/Disassembler/PowerPC/ppc64-encoding-ISA31.txt (diff)
The file was modifiedllvm/lib/Target/PowerPC/PPCInstrPrefix.td (diff)
Commit 196e2f97b714bb535a39a2daa949e523c21c0269 by Amara Emerson
[AArch64][GlobalISel] clang-format AArch64LegalizerInfo.cpp. NFC.
The file was modifiedllvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp (diff)
Commit f5898f8c2def7a1897559a7454086243b7e9ebb6 by Amara Emerson
[AArch64][GlobalISel] Make G_STORE <8 x s8> legal.
The file was modifiedllvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp (diff)
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir (diff)
Commit 4926a5ee63017396e1c55b1505f9fd2bed858218 by Vedant Kumar
[lldb] Clarify docstring for SBBlock::IsInlined, NFC

Previously, there was a little ambiguity about whether IsInlined should
return true for an inlined lexical block, since technically the lexical
block would not represent an inlined function (it'd just be contained
within one).

Edit suggested by Jim Ingham.
The file was modifiedlldb/bindings/interface/SBBlock.i (diff)
Commit bae63742057785e03732f58d6ed1ec7bda090cc1 by silvasean
[mlir][shape] Add `shape.cstr_require %bool`

This op is a catch-all for creating witnesses from various random kinds
of constraints. In particular, I when dealing with extents directly,
which are of `index` type, one can directly use std ops for calculating
the predicates, and then use cstr_require for the final conversion to a
witness.

Differential Revision: https://reviews.llvm.org/D87871
The file was modifiedmlir/test/Dialect/Shape/ops.mlir (diff)
The file was modifiedmlir/include/mlir/Dialect/Shape/IR/ShapeOps.td (diff)
The file was modifiedmlir/lib/Dialect/Shape/IR/Shape.cpp (diff)
The file was modifiedmlir/test/Dialect/Shape/canonicalize.mlir (diff)
Commit ea237e2c8e5d082715effb9cb64158d7c6894e27 by jurahul
[MLIR] Fix build failure due to https://reviews.llvm.org/D87059.

- Remove spurious ;
- Make comparison object invokable as const.

Differential Revision: https://reviews.llvm.org/D87872
The file was modifiedmlir/include/mlir/TableGen/OpClass.h (diff)