SuccessChanges

Summary

  1. [PowerPC] Implement Vector signed/unsigned __int128 overloads for the comparison builtins (details)
  2. [PowerPC] Implement the 128-bit vec_[all|any]_[eq | ne | lt | gt | le | ge] builtins in Clang/LLVM (details)
  3. Recommit [NFC] Refactor DiagnosticBuilder and PartialDiagnostic (details)
  4. [AArch64] Expand some vector of i64 reductions on NEON (details)
  5. [SelectionDAG][GISel] Make LegalizeDAG lower FNEG using integer ops. (details)
Commit 88cdbeab417cc716d1da2de2a508d24622f4a4bc by conanap
[PowerPC] Implement Vector signed/unsigned __int128 overloads for the comparison builtins

This patch implements Vector signed/unsigned __int128 overloads for the comparison builtins.

Differential Revision: https://reviews.llvm.org/D87804
The file was modifiedclang/lib/Headers/altivec.h (diff)
The file was modifiedclang/test/CodeGen/builtins-ppc-p10vector.c (diff)
The file was modifiedllvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp (diff)
The file was modifiedllvm/lib/Target/PowerPC/PPCISelLowering.cpp (diff)
The file was modifiedclang/include/clang/Basic/BuiltinsPPC.def (diff)
The file was modifiedllvm/include/llvm/IR/IntrinsicsPowerPC.td (diff)
The file was addedllvm/test/CodeGen/PowerPC/vec_cmpq.ll
Commit 2e7117f847708d2fd1ff2d2961c3439470532b80 by conanap
[PowerPC] Implement the 128-bit vec_[all|any]_[eq | ne | lt | gt | le | ge] builtins in Clang/LLVM

This patch implements the vec_[all|any]_[eq | ne | lt | gt | le | ge] builtins for vector signed/unsigned __int128.

Differential Revision: https://reviews.llvm.org/D87910
The file was modifiedclang/lib/CodeGen/CGExprScalar.cpp (diff)
The file was modifiedclang/lib/Headers/altivec.h (diff)
The file was modifiedclang/include/clang/Basic/BuiltinsPPC.def (diff)
The file was modifiedllvm/include/llvm/IR/IntrinsicsPowerPC.td (diff)
The file was modifiedllvm/test/CodeGen/PowerPC/vec_cmpq.ll (diff)
The file was modifiedllvm/lib/Target/PowerPC/PPCISelLowering.cpp (diff)
The file was modifiedclang/test/CodeGen/builtins-ppc-p10vector.c (diff)
Commit 8e780a1653e6f87755a447e921b8f929d8b70996 by Yaxun.Liu
Recommit [NFC] Refactor DiagnosticBuilder and PartialDiagnostic

This recommits 829d14ee0a6aa79c89f7f3d9fcd9d27d3efd2b91.

The patch was reverted due to a regression in some CUDA app
which was thought to be caused by this patch. However, investigation
showed that the regression was due to some other issues, therefore
recommit this patch.
The file was modifiedclang/include/clang/AST/ASTContext.h (diff)
The file was modifiedclang/include/clang/AST/TemplateName.h (diff)
The file was modifiedclang/include/clang/AST/Attr.h (diff)
The file was modifiedclang/include/clang/Basic/Diagnostic.h (diff)
The file was modifiedclang/include/clang/AST/CanonicalType.h (diff)
The file was modifiedclang/include/clang/AST/DeclCXX.h (diff)
The file was modifiedclang/include/clang/Sema/Ownership.h (diff)
The file was modifiedclang/include/clang/AST/TemplateBase.h (diff)
The file was modifiedclang/lib/Basic/Diagnostic.cpp (diff)
The file was modifiedclang/lib/AST/TemplateBase.cpp (diff)
The file was modifiedclang/include/clang/AST/Type.h (diff)
The file was modifiedclang/lib/AST/DeclCXX.cpp (diff)
The file was modifiedclang/lib/AST/ASTContext.cpp (diff)
The file was modifiedclang/include/clang/AST/NestedNameSpecifier.h (diff)
The file was modifiedclang/include/clang/Basic/PartialDiagnostic.h (diff)
The file was modifiedclang/lib/AST/TemplateName.cpp (diff)
The file was modifiedclang/include/clang/AST/Decl.h (diff)
The file was modifiedclang/include/clang/AST/DeclarationName.h (diff)
The file was modifiedclang/include/clang/Sema/ParsedAttr.h (diff)
The file was modifiedclang/include/clang/Sema/Sema.h (diff)
Commit e8413ac97f6ca2b1897cc9555ad9b0194456629f by mcinally
[AArch64] Expand some vector of i64 reductions on NEON

With the exception of VECREDUCE_ADD, there are no NEON instructions to support vector of i64 reductions. This patch removes the Custom lowerings for those and adds some test coverage to confirm.

Differential Revision: https://reviews.llvm.org/D88161
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.cpp (diff)
The file was modifiedllvm/test/CodeGen/AArch64/vecreduce-umax-legalization.ll (diff)
The file was modifiedllvm/test/CodeGen/AArch64/aarch64-addv.ll (diff)
Commit 3f739f736b8fed6f4d63569f56c985ef04b21cd1 by efriedma
[SelectionDAG][GISel] Make LegalizeDAG lower FNEG using integer ops.

Previously, if a floating-point type was legal, but FNEG wasn't legal,
we would use FSUB.  Instead, we should use integer ops, to preserve the
semantics.  (Alternatively, there's a compiler-rt call we could use, but
there isn't much reason to use that.)

It turns out we actually are still using this obscure codepath in a few
cases: on some targets, we have "legal" floating-point types that don't
actually support any floating-point operations.  In particular, ARM and
AArch64 are using this path.

The implementation for SelectionDAG is pretty simple because we can
reuse the infrastructure from FCOPYSIGN.

See also 9a3dc3e, the corresponding change to type legalization.

Also includes a "bonus" change to STRICT_FSUB legalization, so we can
lower a STRICT_FSUB to a float libcall.

Includes the changes to both LegalizeDAG and GlobalISel so we don't have
inconsistent results in the future.

Fixes https://bugs.llvm.org/show_bug.cgi?id=46792 .

Differential Revision: https://reviews.llvm.org/D84287
The file was modifiedllvm/lib/Target/ARM/ARMLegalizerInfo.cpp (diff)
The file was modifiedllvm/test/CodeGen/ARM/GlobalISel/arm-legalize-binops.mir (diff)
The file was modifiedllvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp (diff)
The file was modifiedllvm/test/CodeGen/X86/GlobalISel/legalize-fneg.mir (diff)
The file was modifiedllvm/test/CodeGen/AArch64/arm64-fp128.ll (diff)
The file was modifiedllvm/test/CodeGen/Thumb2/mve-fp-negabs.ll (diff)
The file was modifiedllvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (diff)
The file was modifiedllvm/test/CodeGen/ARM/GlobalISel/arm-legalize-fp.mir (diff)