SuccessChanges

Summary

  1. [PhaseOrdering] move an 'opt' test from x86 codegen; NFC (details)
  2. [PhaseOrdering] move test with target requirement to x86 dir (details)
  3. [MLIR][SPIRV] Fixed dialect loading in deserialization (details)
  4. OpaquePtr: Add helpers for sret to mirror byval (details)
  5. IR: Have byref imply dereferenceable (details)
  6. [AMDGPU] Fix v3f16 handling for getresinfo (details)
  7. [AMDGPU] Use cast instead of dyn_cast (details)
Commit 9cf647bb3f88434e3ecba8e108d56fa4e3ed56f9 by spatel
[PhaseOrdering] move an 'opt' test from x86 codegen; NFC

This file comes from 2007, and I'm not entirely sure of the
motivation, but it was going through all of opt and llc.
The llc part is almost certainly unnecessary as shown in
the now auto-generated FileCheck lines.

This test may be affected by a logic change suggested in:
D87835
The file was removedllvm/test/CodeGen/X86/nancvt.ll
The file was addedllvm/test/Transforms/PhaseOrdering/nancvt.ll
Commit 2625433e77ef5e161536f6fd01ea68840cfcb0dc by spatel
[PhaseOrdering] move test with target requirement to x86 dir

I'm not sure if the target is actually necessary,
but since it was specified, I'm moving to the
appropriate dir to avoid bot fallout.
The file was addedllvm/test/Transforms/PhaseOrdering/X86/nancvt.ll
The file was removedllvm/test/Transforms/PhaseOrdering/nancvt.ll
Commit 8f72717ebe27209a11be80629c667332cd5e4e60 by georgemitenk0v
[MLIR][SPIRV] Fixed dialect loading in deserialization

Fixed an error when deserializing the SPIR-V binary
to MLIR SPIR-V. Before, the SPIR-V dialect was not loaded
explicitly into the context, which resulted in unregistered
operation error.

Reviewed By: antiagainst

Differential Revision: https://reviews.llvm.org/D88223
The file was modifiedmlir/lib/Dialect/SPIRV/Serialization/TranslateRegistration.cpp (diff)
Commit d65a7003c435de22b8e30dca292160fea822d887 by Matthew.Arsenault
OpaquePtr: Add helpers for sret to mirror byval

Sret should really have a type parameter like byval does.
The file was modifiedllvm/lib/IR/Value.cpp (diff)
The file was modifiedllvm/lib/IR/Function.cpp (diff)
The file was modifiedllvm/test/CodeGen/X86/vectorcall.ll (diff)
The file was modifiedllvm/include/llvm/IR/Argument.h (diff)
The file was modifiedllvm/lib/Transforms/Scalar/MemCpyOptimizer.cpp (diff)
The file was modifiedllvm/lib/Analysis/Lint.cpp (diff)
The file was modifiedllvm/include/llvm/IR/Function.h (diff)
Commit dc08185ca797a3bcd7721a0d55db876a6cc4de10 by Matthew.Arsenault
IR: Have byref imply dereferenceable

The langref already states it does, but this wasn't implemented. Also
covers inalloca and preallocated. Also helps fix a dependence on
pointer element types.
The file was modifiedllvm/test/Transforms/InstCombine/AMDGPU/memcpy-from-constant.ll (diff)
The file was modifiedllvm/test/Transforms/Attributor/readattrs.ll (diff)
The file was modifiedllvm/test/Transforms/Attributor/value-simplify.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_kernel.ll (diff)
The file was modifiedllvm/lib/IR/Value.cpp (diff)
Commit 6f7cd16d297155332ff2b4c7efb01ca592eb7753 by sebastian.neubauer
[AMDGPU] Fix v3f16 handling for getresinfo

v3f32 should not be expanded to v4f32. getresinfo with a dmask of 7
created an image sample with a v3f32 return value, which was bitcasted
to a v4f32 in constructRetValue.

Differential Revision: https://reviews.llvm.org/D88206
The file was modifiedllvm/lib/Target/AMDGPU/SIISelLowering.cpp (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.dim.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.getresinfo.ll (diff)
Commit c05cf1ca3c55362c5a8ef8a148c3b763cc8784e9 by jay.foad
[AMDGPU] Use cast instead of dyn_cast
The file was modifiedllvm/lib/Target/AMDGPU/R600ISelLowering.cpp (diff)