SuccessChanges

Summary

  1. Revert rGe55410f8b260 : "AArch64/GlobalISel: Add testcase for bug 47619" (details)
  2. [SplitKit] In addDeadDef tolerate parent range that defines more lanes (details)
  3. [AMDGPU] Fix declaration parameter names to match definition (details)
  4. [AArch64] PAC/BTI code generation for LLVM generated functions (details)
Commit 42bfa7c63b85e76fe16521d1671afcafaf8f64ed by llvm-dev
Revert rGe55410f8b260 : "AArch64/GlobalISel: Add testcase for bug 47619"

This reverts commit e55410f8b260a2868d600ca99fe5ee80f9cd4fc5.

This is failing on EXPENSIVE_CHECKS buildbots
The file was removedllvm/test/CodeGen/AArch64/GlobalISel/irtranslator-stack-evt-bug47619.ll
Commit b34ddfcc76e39cdad62887f648aec46c8434c648 by jay.foad
[SplitKit] In addDeadDef tolerate parent range that defines more lanes

Following on from D87757 "[SplitKit] Only copy live lanes", in
SplitEditor::addDeadDef, when we're checking whether the parent live
interval has a subrange defining the same lanes, tolerate the case
where the parent subrange defines a superset of the lanes. This can
happen when the child subrange comes from SplitEditor::buildCopy
decomposing a partial copy into a sequence of subreg copies that cover
the required lanes.

Differential Revision: https://reviews.llvm.org/D88020
The file was modifiedllvm/lib/CodeGen/SplitKit.cpp (diff)
The file was addedllvm/test/CodeGen/AMDGPU/splitkit-getsubrangeformask.ll
The file was modifiedllvm/lib/CodeGen/SplitKit.h (diff)
Commit f11f382523e096859571b61520af81b9bb1defbf by jay.foad
[AMDGPU] Fix declaration parameter names to match definition

This fixes the declaration of AMDGPULegalizerInfo::legalizeBufferLoad to
match the definition. It is still confusing that that parameter order is
different from legalizeBufferStore.

https://bugs.llvm.org/show_bug.cgi?id=47535
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h (diff)
Commit a88c722e687e6780dcd6a58718350dc76fcc4cc9 by momchil.velikov
[AArch64] PAC/BTI code generation for LLVM generated functions

PAC/BTI-related codegen in the AArch64 backend is controlled by a set
of LLVM IR function attributes, added to the function by Clang, based
on command-line options and GCC-style function attributes. However,
functions, generated in the LLVM middle end (for example,
asan.module.ctor or __llvm_gcov_write_out) do not get any attributes
and the backend incorrectly does not do any PAC/BTI code generation.

This patch record the default state of PAC/BTI codegen in a set of
LLVM IR module-level attributes, based on command-line options:

* "sign-return-address", with non-zero value means generate code to
  sign return addresses (PAC-RET), zero value means disable PAC-RET.

* "sign-return-address-all", with non-zero value means enable PAC-RET
  for all functions, zero value means enable PAC-RET only for
  functions, which spill LR.

* "sign-return-address-with-bkey", with non-zero value means use B-key
  for signing, zero value mean use A-key.

This set of attributes are always added for AArch64 targets (as
opposed, for example, to interpreting a missing attribute as having a
value 0) in order to be able to check for conflicts when combining
module attributed during LTO.

Module-level attributes are overridden by function level attributes.
All the decision making about whether to not to generate PAC and/or
BTI code is factored out into AArch64FunctionInfo, there shouldn't be
any places left, other than AArch64FunctionInfo, which directly
examine PAC/BTI attributes, except AArch64AsmPrinter.cpp, which
is/will-be handled by a separate patch.

Differential Revision: https://reviews.llvm.org/D85649
The file was modifiedclang/test/CodeGen/aarch64-branch-protection-attr.c (diff)
The file was addedllvm/test/CodeGen/AArch64/pacbti-module-attrs.ll
The file was modifiedllvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-5.ll (diff)
The file was modifiedllvm/lib/Target/AArch64/AArch64InstrInfo.td (diff)
The file was removedclang/test/CodeGenCXX/aarch64-sign-return-address-static-ctor.cpp
The file was modifiedllvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-3.ll (diff)
The file was modifiedllvm/lib/Target/AArch64/AArch64MachineFunctionInfo.cpp (diff)
The file was modifiedllvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-8.ll (diff)
The file was modifiedclang/test/CodeGen/aarch64-sign-return-address.c (diff)
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp (diff)
The file was modifiedllvm/lib/Target/AArch64/AArch64MachineFunctionInfo.h (diff)
The file was modifiedllvm/test/CodeGen/AArch64/machine-outliner-bti.mir (diff)
The file was addedllvm/test/CodeGen/AArch64/pacbti-llvm-generated-funcs-2.ll
The file was modifiedclang/lib/CodeGen/CGDeclCXX.cpp (diff)
The file was modifiedllvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-4.ll (diff)
The file was addedllvm/test/CodeGen/AArch64/pacbti-llvm-generated-funcs-1.ll
The file was modifiedllvm/test/CodeGen/AArch64/machine-outliner-2fixup-blr-terminator.mir (diff)
The file was modifiedllvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp (diff)
The file was modifiedllvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-0.ll (diff)
The file was modifiedclang/lib/CodeGen/CodeGenModule.cpp (diff)
The file was modifiedllvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-7.ll (diff)
The file was modifiedllvm/test/CodeGen/AArch64/patchable-function-entry-bti.ll (diff)
The file was modifiedllvm/lib/Target/AArch64/AArch64InstrInfo.cpp (diff)
The file was modifiedllvm/test/CodeGen/AArch64/branch-target-enforcement-indirect-calls.ll (diff)
The file was modifiedllvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-1.ll (diff)
The file was modifiedllvm/test/CodeGen/AArch64/machine-outliner-outline-bti.ll (diff)
The file was modifiedclang/lib/CodeGen/TargetInfo.cpp (diff)
The file was modifiedllvm/lib/Target/AArch64/AArch64BranchTargets.cpp (diff)
The file was modifiedllvm/lib/Target/AArch64/AArch64FrameLowering.cpp (diff)
The file was modifiedllvm/test/CodeGen/AArch64/bti-branch-relaxation.ll (diff)
The file was modifiedllvm/test/CodeGen/AArch64/branch-target-enforcement.mir (diff)