1. [Legalize][X86] Improve nnan fmin/fmax vector reduction (details)
  2. [AArch64][GlobalISel] Promote scalar G_SHL constant shift amounts to s64. (details)
Commit f229bf2e12461be55446e6b08ccb931308586031 by nikita.ppv
[Legalize][X86] Improve nnan fmin/fmax vector reduction

Use +/-Inf or +/-Largest as neutral element for nnan fmin/fmax
reductions. This avoids dropping any FMF flags. Preserving the
nnan flag in particular is important to get a good lowering on X86.

Differential Revision:
The file was modifiedllvm/test/CodeGen/X86/vector-reduce-fmax-nnan.ll (diff)
The file was modifiedllvm/test/CodeGen/AArch64/vecreduce-fmax-legalization.ll (diff)
The file was modifiedllvm/test/CodeGen/AArch64/vecreduce-fmin-legalization.ll (diff)
The file was modifiedllvm/test/CodeGen/X86/vector-reduce-fmin-nnan.ll (diff)
The file was modifiedllvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp (diff)
Commit 5811d723998a3abdd3cb95dc579d28f48c57c2fa by Amara Emerson
[AArch64][GlobalISel] Promote scalar G_SHL constant shift amounts to s64.

This was supposed to be done in the first place as is currently the case for
G_ASHR and G_LSHR but was forgotten when the original shift legalization
overhaul was done last year.

This was exposed because we started falling back on s32 = s32, s64 SHLs
due to a recent combiner change.

Gives a very minor (0.1%) code size -O0 improvement on consumer-typeset.
The file was modifiedllvm/test/CodeGen/AArch64/arm64-clrsb.ll (diff)
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/legalize-merge-values.mir (diff)
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/legalize-non-pow2-load-store.mir (diff)
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/legalize-shift.mir (diff)
The file was modifiedllvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp (diff)