SuccessChanges

Summary

  1. remove an include that's unused after r347592 (details)
  2. [lldb/test] Revert changes to debug-names-compressed.cpp (details)
  3. [SystemZ] Avoid unnecessary conversions in vecintrin.h (details)
  4. [PowerPC][AIX] Make PIC the default relocation model for AIX (details)
  5. [gn build] include revision information in lld --version output (details)
  6. [gn build] (manually) port bed7626f04f7 (details)
  7. Revert "[Loop Peeling] Add possibility to enable peeling on loop nests." (details)
  8. [ELF] Decrease alignment of ThunkSection on 64-bit targets from 8 to 4 (details)
  9. [Hexagon] Add a target feature to disable compound instructions (details)
  10. Delete control character from comment. (NFC) (details)
  11. AMDGPU: Update tests to use modern buffer intrinsics (details)
  12. TableGen: Remove dead code (details)
  13. TableGen/GlobalISel: Fix srcvalue inputs (details)
  14. GlobalISel: Preserve load/store metadata in IRTranslator (details)
  15. GlobalISel: Apply target MMO flags to atomics (details)
  16. AMDGPU: Remove IR section from MIR test (details)
  17. [clangd] Make define outline code action visible (details)
  18. [clangd] Print underlying type for decltypes in hover (details)
  19. [LegalizeDAG][Mips] Add an assert to protect a uint_to_fp implementation (details)
  20. [Hexagon] Update autogeneated intrinsic information in LLVM (details)
Commit 81c67da0f20a101b5ee3a9c1ce8c74a6a0a1925c by thakis
remove an include that's unused after r347592
The file was modifiedllvm/lib/LTO/ThinLTOCodeGenerator.cpp
Commit ee05138515abee2a349ad2fdc8320ab17ddfde12 by pavel
[lldb/test] Revert changes to debug-names-compressed.cpp
With the changes in 15a6df52efa, the test is failing in some
configurations. Reverting while I investigate
The file was modifiedlldb/test/Shell/SymbolFile/DWARF/debug-names-compressed.cpp
Commit cebba7ce3952c8f37a923fa3a10360fd4c463775 by ulrich.weigand
[SystemZ] Avoid unnecessary conversions in vecintrin.h
Use floating-point instead of integer zero constants to avoid creating
implicit conversions, which currently cause suboptimal code to be
generated with -ffp-exception-behavior=strict.
NFC otherwise.
The file was modifiedclang/lib/Headers/vecintrin.h
Commit bed7626f04f7442bed3674126ba6b658b4dfa505 by wanyu9511
[PowerPC][AIX] Make PIC the default relocation model for AIX
Summary: The `llc` tool currently defaults to Static relocation model
and generates non-relocatable code for 32-bit Power. This is not
desirable on AIX where we always generate Position Independent Code
(PIC). This patch makes PIC the default relocation model for AIX.
Reviewers: daltenty, hubert.reinterpretcast, DiggerLin, Xiangling_L,
sfertile
Reviewed By: hubert.reinterpretcast
Subscribers: mgorny, wuzish, nemanjai, hiraditya, kbarton, jsji,
shchenz, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D72479
The file was modifiedllvm/lib/Target/PowerPC/PPCTargetMachine.cpp
The file was addedllvm/unittests/Target/PowerPC/CMakeLists.txt
The file was addedllvm/unittests/Target/PowerPC/AIXRelocModelTest.cpp
The file was modifiedllvm/tools/llc/llc.cpp
The file was addedllvm/test/tools/llc/aix-pic-setting.ll
Commit 5caa1212957456c3bfb4adf3cd3b7308cecc8650 by thakis
[gn build] include revision information in lld --version output
The file was modifiedllvm/utils/gn/secondary/clang/lib/Basic/BUILD.gn
The file was modifiedllvm/utils/gn/build/write_vcsrevision.gni
The file was modifiedllvm/utils/gn/secondary/lld/Common/BUILD.gn
Commit d51a15d86a2501343fc169a4e02ec03a5e6e92be by thakis
[gn build] (manually) port bed7626f04f7
The file was addedllvm/utils/gn/secondary/llvm/unittests/Target/PowerPC/BUILD.gn
The file was modifiedllvm/utils/gn/secondary/llvm/unittests/BUILD.gn
Commit c87982b46701155926ca2c2bf07cbda3d3bade7b by arkady.shlykov
Revert "[Loop Peeling] Add possibility to enable peeling on loop nests."
This reverts commit 3f3017e because there's a failure on
peel-loop-nests.ll with LLVM_ENABLE_EXPENSIVE_CHECKS on.
Differential Revision: https://reviews.llvm.org/D70304
The file was removedllvm/test/Transforms/LoopUnroll/peel-loop-nests.ll
The file was modifiedllvm/include/llvm/Analysis/TargetTransformInfo.h
The file was modifiedllvm/lib/Transforms/Scalar/LoopUnrollPass.cpp
The file was modifiedllvm/lib/Transforms/Utils/LoopUnrollPeel.cpp
The file was modifiedllvm/test/Transforms/LoopUnroll/peel-loop-conditions.ll
Commit 870094decfc9fe80c8e0a6405421b7d09b97b02b by maskray
[ELF] Decrease alignment of ThunkSection on 64-bit targets from 8 to 4
ThunkSection contains 4-byte instructions on all targets that use
thunks. Thunks should not be used in any performance sensitive places,
and locality/cache line/instruction fetching arguments should not apply.
We use 16 bytes as preferred function alignments for modern PowerPC
cores. In any case, 8 is not optimal.
Differential Revision: https://reviews.llvm.org/D72819
The file was modifiedlld/test/ELF/aarch64-cortex-a53-843419-thunk.s
The file was modifiedlld/test/ELF/ppc64-ifunc.s
The file was modifiedlld/test/ELF/aarch64-thunk-pi.s
The file was modifiedlld/test/ELF/ppc64-dtprel.s
The file was modifiedlld/ELF/SyntheticSections.cpp
The file was modifiedlld/test/ELF/ppc64-long-branch.s
The file was modifiedlld/test/ELF/ppc64-toc-restore.s
The file was modifiedlld/test/ELF/aarch64-call26-thunk.s
The file was modifiedlld/test/ELF/aarch64-jump26-thunk.s
The file was modifiedlld/test/ELF/aarch64-thunk-script.s
The file was modifiedlld/test/ELF/ppc64-tls-gd.s
Commit 8ee2d1689664d4d116c693ff427159396474c30d by kparzysz
[Hexagon] Add a target feature to disable compound instructions
This affects the following instructions: Tag: M4_mpyrr_addr     Syntax:
Ry32 = add(Ru32,mpyi(Ry32,Rs32)) Tag: M4_mpyri_addr_u2  Syntax: Rd32 =
add(Ru32,mpyi(#u6:2,Rs32)) Tag: M4_mpyri_addr     Syntax: Rd32 =
add(Ru32,mpyi(Rs32,#u6)) Tag: M4_mpyri_addi     Syntax: Rd32 =
add(#u6,mpyi(Rs32,#U6)) Tag: M4_mpyrr_addi     Syntax: Rd32 =
add(#u6,mpyi(Rs32,Rt32)) Tag: S4_addaddi        Syntax: Rd32 =
add(Rs32,add(Ru32,#s6)) Tag: S4_subaddi        Syntax: Rd32 =
add(Rs32,sub(#s6,Ru32)) Tag: S4_or_andix       Syntax: Rx32 =
or(Ru32,and(Rx32,#s10)) Tag: S4_andi_asl_ri    Syntax: Rx32 =
and(#u8,asl(Rx32,#U5)) Tag: S4_ori_asl_ri     Syntax: Rx32 =
or(#u8,asl(Rx32,#U5)) Tag: S4_addi_asl_ri    Syntax: Rx32 =
add(#u8,asl(Rx32,#U5)) Tag: S4_subi_asl_ri    Syntax: Rx32 =
sub(#u8,asl(Rx32,#U5)) Tag: S4_andi_lsr_ri    Syntax: Rx32 =
and(#u8,lsr(Rx32,#U5)) Tag: S4_ori_lsr_ri     Syntax: Rx32 =
or(#u8,lsr(Rx32,#U5)) Tag: S4_addi_lsr_ri    Syntax: Rx32 =
add(#u8,lsr(Rx32,#U5)) Tag: S4_subi_lsr_ri    Syntax: Rx32 =
sub(#u8,lsr(Rx32,#U5))
The file was modifiedllvm/lib/Target/Hexagon/HexagonPatterns.td
The file was modifiedllvm/lib/Target/Hexagon/HexagonSubtarget.h
The file was modifiedllvm/lib/Target/Hexagon/HexagonDepInstrInfo.td
The file was modifiedllvm/lib/Target/Hexagon/HexagonConstExtenders.cpp
The file was addedllvm/test/CodeGen/Hexagon/feature-compound.ll
The file was modifiedllvm/lib/Target/Hexagon/HexagonDepMapAsm2Intrin.td
The file was modifiedllvm/lib/Target/Hexagon/Hexagon.td
The file was modifiedllvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
Commit c0d909a1b12fd646f7dbca3cd098ff7e278d7446 by Adrian Prantl
Delete control character from comment. (NFC)
The file was modifiedlldb/source/Expression/DWARFExpression.cpp
Commit 20ca49b646b73619b05d1a6908c5ab3416f53f97 by arsenm2
AMDGPU: Update tests to use modern buffer intrinsics
The file was modifiedllvm/test/CodeGen/AMDGPU/mubuf-shader-vgpr.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/uniform-branch-intrinsic-cond.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/vgpr-spill-emergency-stack-slot.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/amdpal.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/mubuf-legalize-operands.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/wave32.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.softwqm.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/i1-copy-from-loop.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/loop_exit_with_xor.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/else.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/vgpr-descriptor-waterfall-loop-idom-update.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/wqm.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/wait.ll
Commit 86d14ed766eb10b2c0c61126343bb305676d85de by arsenm2
TableGen: Remove dead code
The file was modifiedllvm/include/llvm/Target/TargetSelectionDAG.td
Commit 03a592f18ba57d52a65e70ad5e1dd709cdcfb71d by arsenm2
TableGen/GlobalISel: Fix srcvalue inputs
Allow using srcvalue for discarding pattern inputs.
The file was addedllvm/test/TableGen/GlobalISelEmitter-input-discard.td
The file was modifiedllvm/utils/TableGen/GlobalISelEmitter.cpp
Commit 0d0fce42b0ea7c7ce18cd0191f95204a0b800b15 by arsenm2
GlobalISel: Preserve load/store metadata in IRTranslator
This was dropping the invariant metadata on dead argument loads, so they
weren't deleted.
Atomics still need to be fixed the same way. Also, apparently store was
never preserving dereferencable which should also be fixed.
The file was modifiedllvm/lib/CodeGen/TargetLoweringBase.cpp
The file was modifiedllvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
The file was modifiedllvm/lib/Target/SystemZ/SystemZISelLowering.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-function-args.ll
The file was modifiedllvm/lib/Target/SystemZ/SystemZISelLowering.h
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.cpp
The file was addedllvm/test/CodeGen/AArch64/GlobalISel/irtranslator-load-metadata.ll
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/constant-dbg-loc.ll
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/irtranslator/var_arg.ll
The file was modifiedllvm/include/llvm/CodeGen/TargetLowering.h
The file was modifiedllvm/test/CodeGen/X86/GlobalISel/x86_64-irtranslator-struct-return.ll
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/irtranslator-stackprotect-check.ll
The file was modifiedllvm/lib/Target/XCore/XCoreISelLowering.cpp
The file was addedllvm/test/CodeGen/AArch64/GlobalISel/irtranslator-store-metadata.ll
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.h
The file was modifiedllvm/lib/Target/XCore/XCoreISelLowering.h
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/localizer-arm64-tti.ll
The file was modifiedllvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
Commit d0943537e10e25281164bb27df843e283dc6666c by arsenm2
GlobalISel: Apply target MMO flags to atomics
Unify MMO flag handling with SelectionDAG like with loads and stores.
The file was modifiedllvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
The file was modifiedllvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
The file was modifiedllvm/include/llvm/CodeGen/TargetLowering.h
The file was addedllvm/test/CodeGen/AArch64/GlobalISel/irtranslator-atomic-metadata.ll
The file was modifiedllvm/lib/CodeGen/TargetLoweringBase.cpp
Commit de4f88df97cbc99b0a7855b177d62f62f4ddd533 by arsenm2
AMDGPU: Remove IR section from MIR test
Also generate check lines so this isn't just testing the meaningless
block name.
The file was modifiedllvm/test/CodeGen/AMDGPU/couldnt-join-subrange-3.mir
Commit a881fcafaa5af545b049c5fd69ccaf9c93196640 by kadircet
[clangd] Make define outline code action visible
Summary: This got forgotten during the process.
Reviewers: sammccall, usaxena95
Subscribers: ilya-biryukov, MaskRay, jkorous, arphaman, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D72840
The file was modifiedclang-tools-extra/clangd/refactor/tweaks/DefineOutline.cpp
Commit 0474fe465d8feebcfd54a16d93ad8518b5625972 by kadircet
[clangd] Print underlying type for decltypes in hover
Summary: Fixes https://github.com/clangd/clangd/issues/249
Reviewers: sammccall
Subscribers: ilya-biryukov, MaskRay, jkorous, arphaman, usaxena95,
cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D72498
The file was modifiedclang-tools-extra/clangd/unittests/HoverTests.cpp
The file was modifiedclang-tools-extra/clangd/Hover.cpp
Commit 61a89e17df4c3baf9cdf317d8ae3a73788f2aa92 by craig.topper
[LegalizeDAG][Mips] Add an assert to protect a uint_to_fp implementation
from double rounding. Add a i32->f32 uint_to_fp implementation that
avoids this code.
The algorithm here only works if the sint_to_fp doesn't do any rounding.
Otherwise it can round before the offset fixup is applied. Add an assert
to protect this.
To avoid breaking the one test in tree that tested this code with a set
of types that fail the assert, I've enabled i32->f32 to use the i64->f32
algorithm. This only occurs when f64 isn't a legal type. If f64 is legal
then we do i32->f64->f32 instead.
Differential Revision: https://reviews.llvm.org/D72794
The file was modifiedllvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
The file was modifiedllvm/test/CodeGen/Mips/uitofp.ll
Commit 5f65065437cdbb680a6552d12d43090dc8d632b9 by kparzysz
[Hexagon] Update autogeneated intrinsic information in LLVM
The file was modifiedllvm/lib/Target/Hexagon/HexagonDepMapAsm2Intrin.td
The file was addedllvm/include/llvm/IR/IntrinsicsHexagonDep.td
The file was modifiedllvm/include/llvm/IR/IntrinsicsHexagon.td