FailedChanges

Summary

  1. Relax newly added opcode checks to check only for a number instead of a specific opcode. (details)
  2. [X86] Split more masked instruction tests to enable D60940. (details)
  3. [PowerPC] Improve the way legalize mul for v8i16 and add pattern to match mul + add (details)
  4. Use optimal layout and preserve alloca alignment in coroutine frames. (details)
  5. Fix `-Wreturn-type` warning. NFC. (details)
  6. [InstCombine] Fix a code-sinking bug after D73832/f1a9efabcb9b (details)
  7. [X86] Update more intrinsic tests to prepare to extend D60940 to scalar fp. (details)
  8. [ELF][test] Delete unneeded binding directive (.weak or .globl) (details)
  9. [MLIR] Add flat affine constraints method to round trip integer set (details)
Commit d622612e618adf4b21fc12aac51f88b5e878157a by douglas.yung
Relax newly added opcode checks to check only for a number instead of a specific opcode.
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
Commit 31c5afb3f2e7617586996a6cb9513eda353ce0d1 by craig.topper
[X86] Split more masked instruction tests to enable D60940.

More mechanical splitting of tests so we can add a one use
check to the isel patterns for forming masked instructions.

In a few cases I changed immediates of instructions in
order to avoid needing to split.
The file was modifiedllvm/test/CodeGen/X86/avx512-rotate.ll
The file was modifiedllvm/test/CodeGen/X86/avx512vnni-intrinsics.ll
The file was modifiedllvm/test/CodeGen/X86/avx512vbmi2-intrinsics-upgrade.ll
The file was modifiedllvm/test/CodeGen/X86/avx512vnni-intrinsics-upgrade.ll
The file was modifiedllvm/test/CodeGen/X86/avx512vl-intrinsics-upgrade.ll
The file was modifiedllvm/test/CodeGen/X86/avx512vl_vnni-intrinsics-upgrade.ll
The file was modifiedllvm/test/CodeGen/X86/avx512dqvl-intrinsics.ll
The file was modifiedllvm/test/CodeGen/X86/avx512vbmi2vl-intrinsics.ll
The file was modifiedllvm/test/CodeGen/X86/avx512-intrinsics-upgrade.ll
The file was modifiedllvm/test/CodeGen/X86/avx512vl_vnni-intrinsics.ll
The file was modifiedllvm/test/CodeGen/X86/avx512ifma-intrinsics.ll
The file was modifiedllvm/test/CodeGen/X86/avx512cdvl-intrinsics-upgrade.ll
The file was modifiedllvm/test/CodeGen/X86/avx512vbmi2vl-intrinsics-upgrade.ll
The file was modifiedllvm/test/CodeGen/X86/avx512bwvl-intrinsics-upgrade.ll
The file was modifiedllvm/test/CodeGen/X86/avx512ifmavl-intrinsics.ll
The file was modifiedllvm/test/CodeGen/X86/avx512vbmi2-intrinsics.ll
The file was modifiedllvm/test/CodeGen/X86/avx512bw-intrinsics-upgrade.ll
The file was modifiedllvm/test/CodeGen/X86/avx512-intrinsics.ll
The file was modifiedllvm/test/CodeGen/X86/avx512vl-intrinsics.ll
The file was modifiedllvm/test/CodeGen/X86/avx512ifmavl-intrinsics-upgrade.ll
The file was modifiedllvm/test/CodeGen/X86/avx512-gfni-intrinsics.ll
The file was modifiedllvm/test/CodeGen/X86/avx512bw-intrinsics.ll
The file was modifiedllvm/test/CodeGen/X86/avx512bwvl-intrinsics.ll
The file was modifiedllvm/test/CodeGen/X86/avx512cdvl-intrinsics.ll
The file was modifiedllvm/test/CodeGen/X86/avx512ifma-intrinsics-upgrade.ll
Commit 1ef7bf412141811fa80473e0f13e9dc76972b1a0 by qshanz
[PowerPC] Improve the way legalize mul for v8i16 and add pattern to match mul + add

We can legalize the operation MUL for v8i16 with instruction (vmladduhm A, B, 0)
if altivec enabled. Now, it is set as custom and expand it later, which is not
the right way. And then, we can add the pattern to match the mul + add with (vmladduhm A, B, C)

Reviewed By: Nemanjai

Differential Revision: https://reviews.llvm.org/D76751
The file was modifiedllvm/test/CodeGen/PowerPC/vmladduhm.ll
The file was modifiedllvm/lib/Target/PowerPC/PPCISelLowering.cpp
The file was modifiedllvm/lib/Target/PowerPC/PPCInstrAltivec.td
Commit 9514c048d89e6aef82d86c3478223fcb28230a4f by rjmccall
Use optimal layout and preserve alloca alignment in coroutine frames.

Previously, we would ignore alloca alignment when building the frame
and just use the natural alignment of the allocated type.  If an alloca
is over-aligned for its IR type, this could lead to a frame entry with
inadequate alignment for the downstream uses of the alloca.

Since highly-aligned fields also tend to produce poor layouts under a
naive layout algorithm, I've also switched coroutine frames to use the
new optimal struct layout algorithm.

In order to communicate the frame size and alignment to later passes,
I needed to set align+dereferenceable attributes on the frame-pointer
parameter of the resume function.  This is clearly the right thing to
do, but the align attribute currently seems to result in assumptions
being added during inlining that the optimizer cannot easily remove.
The file was modifiedllvm/test/Transforms/Coroutines/ex5.ll
The file was modifiedllvm/lib/Transforms/Coroutines/CoroEarly.cpp
The file was modifiedllvm/test/Transforms/Coroutines/coro-eh-aware-edge-split-01.ll
The file was modifiedllvm/test/Transforms/Coroutines/coro-spill-after-phi.ll
The file was modifiedllvm/test/Transforms/Coroutines/coro-frame.ll
The file was modifiedllvm/lib/Transforms/Coroutines/CoroElide.cpp
The file was modifiedllvm/lib/IR/Verifier.cpp
The file was modifiedllvm/test/Transforms/Coroutines/coro-padding.ll
The file was modifiedllvm/test/Transforms/Coroutines/coro-spill-corobegin.ll
The file was modifiedllvm/test/Transforms/Coroutines/coro-frame-arrayalloca.ll
The file was modifiedllvm/lib/Transforms/Coroutines/CoroInternal.h
The file was modifiedllvm/lib/Transforms/Coroutines/CoroInstr.h
The file was modifiedllvm/test/Transforms/Coroutines/coro-retcon-value.ll
The file was modifiedllvm/test/Transforms/Coroutines/coro-catchswitch.ll
The file was modifiedllvm/test/Transforms/Coroutines/coro-retcon-resume-values.ll
The file was modifiedllvm/test/Transforms/Coroutines/ex1.ll
The file was modifiedllvm/test/Transforms/Coroutines/coro-eh-aware-edge-split-02.ll
The file was modifiedllvm/test/Transforms/Coroutines/coro-heap-elide.ll
The file was modifiedllvm/test/Transforms/Coroutines/coro-debug.ll
The file was modifiedllvm/test/Transforms/Coroutines/coro-materialize.ll
The file was modifiedllvm/test/Transforms/Coroutines/ArgAddr.ll
The file was modifiedllvm/test/Transforms/Coroutines/coro-retcon.ll
The file was modifiedllvm/test/Transforms/Coroutines/ex0.ll
The file was modifiedllvm/lib/Transforms/Coroutines/CoroFrame.cpp
The file was modifiedllvm/test/Transforms/Coroutines/coro-retcon-resume-values2.ll
The file was modifiedllvm/test/Transforms/Coroutines/coro-retcon-alloca.ll
The file was modifiedllvm/test/Transforms/Coroutines/coro-retcon-once-value2.ll
The file was modifiedllvm/test/Transforms/Coroutines/coro-alloc-with-param-O2.ll
The file was modifiedllvm/test/Transforms/Coroutines/coro-retcon-once-value.ll
The file was modifiedllvm/test/Transforms/Coroutines/coro-alloc-with-param-O0.ll
The file was modifiedllvm/test/Transforms/Coroutines/coro-param-copy.ll
The file was modifiedllvm/test/Transforms/Coroutines/coro-swifterror.ll
The file was modifiedllvm/lib/Transforms/Coroutines/CoroSplit.cpp
Commit d264f02c6f502960e2bcdd332f250efc702d09f2 by michael.hliao
Fix `-Wreturn-type` warning. NFC.
The file was modifiedclang/lib/Basic/Targets/X86.cpp
Commit 4c52d51e784ca7603969f2a664e5430d41b9d5dc by maskray
[InstCombine] Fix a code-sinking bug after D73832/f1a9efabcb9b

- UserParent = PN->getIncomingBlock(*I->use_begin());
+ UserParent = PN->getIncomingBlock(*SingleUse);

The first use of I may be droppable (llvm.assume).

When compiling llvm/lib/IR/AutoUpgrade.cpp with a bootstrapped clang
with ThinLTO with minimized bitcode files, I see such a case in
the function _ZN4llvm20UpgradeIntrinsicCallEPNS_8CallInstEPNS_8FunctionE

  clang -c -fthinlto-index=AutoUpgrade.o.thinlto.bc AutoUpgrade.bc -O3

Unfortunately it is really difficult to get a minimized reproduce.
The file was modifiedllvm/lib/Transforms/InstCombine/InstructionCombining.cpp
Commit 281015de5d98a9ca92c18f5271aa028e980a76e7 by craig.topper
[X86] Update more intrinsic tests to prepare to extend D60940 to scalar fp.

I want to extend D60940 to scalar FP which will prevent forming
masked instructions if the arithmetic op has another use. To
prepare for that, this patch updates tests to avoid repeating
the operation multiple times with different masking.
The file was modifiedllvm/test/CodeGen/X86/avx512-intrinsics-upgrade.ll
The file was modifiedllvm/test/CodeGen/X86/avx512-memfold.ll
The file was modifiedllvm/test/CodeGen/X86/avx512dq-intrinsics.ll
The file was modifiedllvm/test/CodeGen/X86/avx512-intrinsics.ll
Commit 72ffc14e13b85fd95c1ffeec22e050b27249264d by maskray
[ELF][test] Delete unneeded binding directive (.weak or .globl)

Future MC may error for a changed symbol binding.
This may be a preferred resolution to https://bugs.llvm.org/show_bug.cgi?id=38921

See https://sourceware.org/pipermail/binutils/2020-March/110399.html
The file was modifiedlld/test/ELF/Inputs/copy-rel.s
The file was modifiedlld/test/ELF/lazy-arch-conflict.s
The file was modifiedlld/test/ELF/relocation-relative-weak.s
The file was modifiedlld/test/ELF/znotext-weak-undef.s
Commit 92744f624783d92a07db25bc76e181b879f17e5b by uday
[MLIR] Add flat affine constraints method to round trip integer set

- add method to get back an integer set from flat affine constraints;
  this allows a round trip
- use this to complete the simplification of integer sets in
  -simplify-affine-structures
- update FlatAffineConstraints::removeTrivialRedundancy to also do GCD
  tightening and normalize by GCD (while still keeping it linear time).

Signed-off-by: Uday Bondhugula <uday@polymagelabs.com>
The file was modifiedmlir/include/mlir/Analysis/AffineStructures.h
The file was modifiedmlir/lib/Analysis/AffineStructures.cpp
The file was modifiedmlir/test/Dialect/Affine/simplify-affine-structures.mlir
The file was modifiedmlir/include/mlir/Analysis/Utils.h
The file was modifiedmlir/lib/Analysis/Utils.cpp
The file was modifiedmlir/lib/Dialect/Affine/Transforms/SimplifyAffineStructures.cpp