SuccessChanges

Summary

  1. [CodeMoverUtils] Use dominator tree level to decide the direction of (details)
  2. [mlir] [VectorOps] Add 'vector.flat_transpose' operation (details)
  3. [PowerPC] Add support for -mcpu=pwr10 in both clang and llvm (details)
  4. [BPF] simplify zero extension with MOV_32_64 (details)
  5. AMDGPU: Start adding MODE register uses to instructions (details)
  6. [InstCombine] add tests for vector demanded elements of select condition; NFC (details)
  7. [llvm]NFC] Simplify ProfileSummaryInfo state transitions (details)
  8. [X86] Restore selection of MULX on BMI2 targets. (details)
  9. [lldb/Test] Generate YAML binary in build directory (details)
  10. [lldb/Reproducers] Skip tests relying on timeouts (details)
  11. Also cache negative results in GetXcodeSDKPath (NFC) (details)
  12. [AMDGPU] Fix for the lost CarryOut/CarryIn register operands in S_ADD/SUB_CO_PSEUDO. (details)
  13. tsan: fix test in debug mode (details)
  14. [GlobalISel] Don't combine instructions which are fed by memory instructions. (details)
  15. Fix `-Wpedantic` warning. NFC. (details)
  16. [mlir][Linalg] Fix build failure from D80188 (details)
  17. [mlir] Fix RunnerUtils template specialization (details)
  18. [TargetPassConfig] Add CanonicalizeFreezeInLoops before LSR (details)
  19. Remove error-prone mlir::ExecutionEngine::invoke overload. (details)
  20. [StackSafety] Bailout more aggressively (details)
  21. [NFC,StackSafety] Rename some variables (details)
  22. Refactor argument attribute specification in intrinsic definition. NFC. (details)
  23. Enable `align <n>` to be used in the intrinsic definition. (details)
  24. [llvm] Add function feature extraction analysis (details)
  25. [mlir][core] Add IndexElementsAttr helpers. (details)
  26. [mlir][shape] Use IndexElementsAttr in Shape dialect. (details)
  27. [lldb/Reproducers] Differentiate active and passive replay unexpected packet. (details)
  28. [lldb/Reproducers] Skip & add FIXME to tests failing with unexpected packet. (details)
  29. [NFC] Reformat TEST_FOO macros in test_macros.h (details)
  30. Fix a use-after-free in GetXcodeSDKPath (details)
  31. [mlir][Linalg] Add missing library linkage for shared library builds. (details)
  32. Fix Windows command line bug when last token in response file is "" (details)
  33. Fix shared libs build break introduced in rG98ef93eabd76 (details)
  34. [MLPolicies] Fix dependency and -DBUILD_SHARED_LIBS=on builds after D80579 (details)
  35. [CMake] Revert cf86a234ba86acf0bb875e21d27833be36e08be4 (details)
  36. AMDGPU/GlobalISel: Fixed handling of non-standard vectors (details)
  37. DAG: Fix expansion of DYNAMIC_STACKALLOC for StackGrowsUp targets (details)
  38. AMDGPU: Support non-entry block static sized allocas (details)
  39. [Lexer] Fix invalid suffix diagnostic for fixed-point literals (details)
  40. AMDGPU/GlobalISel: Fixed insert element for non-standard vectors (details)
  41. [TRE] Allow elimination when the returned value is non-constant (details)
  42. [ELF] --wrap: Drop __real_ symbol from the symbol table (details)
Commit eadf2959567c89bebff153feac873cbc1b71eb04 by whitneyt
[CodeMoverUtils] Use dominator tree level to decide the direction of
code motion

Summary: Currently isSafeToMoveBefore uses DFS numbering for determining
the relative position of instruction and insert point which is not
always correct. This PR proposes the use of Dominator Tree depth for the
same. If a node is at a higher level than the insert point then it is
safe to say that we want to move in the forward direction.
Authored By: RithikSharma
Reviewer: Whitney, nikic, bmahjour, etiotto, fhahn
Reviewed By: Whitney
Subscribers: fhahn, hiraditya, llvm-commits
Tag: LLVM
Differential Revision: https://reviews.llvm.org/D80084
The file was modifiedllvm/include/llvm/Analysis/OrderedInstructions.h
The file was modifiedllvm/lib/Analysis/OrderedInstructions.cpp
The file was modifiedllvm/unittests/Transforms/Utils/CodeMoverUtilsTest.cpp
The file was modifiedllvm/lib/Transforms/Utils/CodeMoverUtils.cpp
Commit c295a65da496f5e982402e8f83e417659c7dd166 by ajcbik
[mlir] [VectorOps] Add 'vector.flat_transpose' operation

Summary:
Provides a representation of the linearized LLVM instrinsic.
With tests and lowering implementation to LLVM IR dialect.
Prepares better lowering for 2-D vector.transpose.

Reviewers: nicolasvasilache, ftynse, reidtatge, bkramer, dcaballe

Reviewed By: ftynse, dcaballe

Subscribers: mehdi_amini, rriddle, jpienaar, shauheen, antiagainst, nicolasvasilache, arpith-jacob, mgester, lucyrfox, liufengdb, stephenneuendorffer, Joonsoo, grosul1, frgossen, Kayjukh, jurahul, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D80419
The file was modifiedmlir/include/mlir/Dialect/Vector/VectorOps.td
The file was modifiedmlir/test/Conversion/VectorToLLVM/vector-to-llvm.mlir
The file was modifiedmlir/lib/Conversion/VectorToLLVM/ConvertVectorToLLVM.cpp
The file was modifiedmlir/test/Dialect/Vector/invalid.mlir
The file was modifiedmlir/test/Dialect/Vector/ops.mlir
Commit 2368bf52cd7725a34f09f4b27a9c205cda06f478 by lei
[PowerPC] Add support for -mcpu=pwr10 in both clang and llvm

Summary:
This patch simply adds support for the new CPU in anticipation of
Power10. There isn't really any functionality added so there are no
associated test cases at this time.

Reviewers: stefanp, nemanjai, amyk, hfinkel, power-llvm-team, #powerpc

Reviewed By: stefanp, nemanjai, amyk, #powerpc

Subscribers: NeHuang, steven.zhang, hiraditya, llvm-commits, wuzish, shchenz, cfe-commits, kbarton, echristo

Tags: #clang, #powerpc, #llvm

Differential Revision: https://reviews.llvm.org/D80020
The file was modifiedllvm/lib/Support/Host.cpp
The file was modifiedclang/lib/Basic/Targets/PPC.h
The file was modifiedllvm/lib/Target/PowerPC/PPCSubtarget.cpp
The file was modifiedllvm/lib/Target/PowerPC/PPCSubtarget.h
The file was modifiedclang/lib/Driver/ToolChains/Arch/PPC.cpp
The file was modifiedllvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
The file was modifiedclang/test/Misc/target-invalid-cpu-note.c
The file was modifiedclang/lib/Basic/Targets/PPC.cpp
The file was modifiedclang/test/Preprocessor/init-ppc64.c
The file was modifiedllvm/lib/Target/PowerPC/PPC.td
The file was modifiedllvm/lib/Target/PowerPC/PPCISelLowering.cpp
The file was modifiedllvm/test/CodeGen/PowerPC/check-cpu.ll
Commit 13f6c81c5d9a7a34a684363bcaad8eb7c65356fd by yhs
[BPF] simplify zero extension with MOV_32_64

The current pattern matching for zext results in the following code snippet
being produced,

  w1 = w0
  r1 <<= 32
  r1 >>= 32

Because BPF implementations require zero extension on 32bit loads this
both adds a few extra unneeded instructions but also makes it a bit
harder for the verifier to track the r1 register bounds. For example in
this verifier trace we see at the end of the snippet R2 offset is unknown.
However, if we track this correctly we see w1 should have the same bounds
as r8. R8 smax is less than U32 max value so a zero extend load should keep
the same value. Adding a max value of 800 (R8=inv(id=0,smax_value=800)) to
an off=0, as seen in R7 should create a max offset of 800. However at the
end of the snippet we note the R2 max offset is 0xffffFFFF.

  R0=inv(id=0,smax_value=800)
  R1_w=inv(id=0,umax_value=2147483647,var_off=(0x0; 0x7fffffff))
  R6=ctx(id=0,off=0,imm=0) R7=map_value(id=0,off=0,ks=4,vs=1600,imm=0)
  R8_w=inv(id=0,smax_value=800,umax_value=4294967295,var_off=(0x0; 0xffffffff))
  R9=inv800 R10=fp0 fp-8=mmmm????
58: (1c) w9 -= w8
59: (bc) w1 = w8
60: (67) r1 <<= 32
61: (77) r1 >>= 32
62: (bf) r2 = r7
63: (0f) r2 += r1
64: (bf) r1 = r6
65: (bc) w3 = w9
66: (b7) r4 = 0
67: (85) call bpf_get_stack#67
  R0=inv(id=0,smax_value=800)
  R1_w=ctx(id=0,off=0,imm=0)
  R2_w=map_value(id=0,off=0,ks=4,vs=1600,umax_value=4294967295,var_off=(0x0; 0xffffffff))
  R3_w=inv(id=0,umax_value=800,var_off=(0x0; 0x3ff))
  R4_w=inv0 R6=ctx(id=0,off=0,imm=0)
  R7=map_value(id=0,off=0,ks=4,vs=1600,imm=0)
  R8_w=inv(id=0,smax_value=800,umax_value=4294967295,var_off=(0x0; 0xffffffff))
  R9_w=inv(id=0,umax_value=800,var_off=(0x0; 0x3ff))
  R10=fp0 fp-8=mmmm????

After this patch R1 bounds are not smashed by the <<=32 >>=32 shift and we
get correct bounds on R2 umax_value=800.

Further it reduces 3 insns to 1.

Signed-off-by: John Fastabend <john.fastabend@gmail.com>

Differential Revision: https://reviews.llvm.org/D73985
The file was addedllvm/test/CodeGen/BPF/32-bit-subreg-zext.ll
The file was modifiedllvm/test/CodeGen/BPF/32-bit-subreg-peephole-phi-3.ll
The file was modifiedllvm/lib/Target/BPF/BPFInstrInfo.td
The file was modifiedllvm/test/CodeGen/BPF/32-bit-subreg-cond-select.ll
The file was modifiedllvm/lib/Target/BPF/BPFMIPeephole.cpp
The file was modifiedllvm/test/CodeGen/BPF/32-bit-subreg-peephole-phi-1.ll
The file was modifiedllvm/test/CodeGen/BPF/32-bit-subreg-peephole.ll
The file was modifiedllvm/lib/Target/BPF/BPFISelLowering.cpp
The file was modifiedllvm/test/CodeGen/BPF/32-bit-subreg-peephole-phi-2.ll
Commit 4b4496312e3380d8c427ef836f2b0a38d145652b by arsenm2
AMDGPU: Start adding MODE register uses to instructions

This is the groundwork required to implement strictfp. For now, this
should be NFC for regular instructoins (many instructions just gain an
extra use of a reserved register). Regalloc won't rematerialize
instructions with reads of physical registers, but we were suffering
from that anyway with the exec reads.

Should add it for all the related FP uses (possibly with some
extras). I did not add it to either the gpr index mode instructions
(or every single VALU instruction) since it's a ridiculous feature
already modeled as an arbitrary side effect.

Also work towards marking instructions with FP exceptions. This
doesn't actually set the bit yet since this would start to change
codegen. It seems nofpexcept is currently not implied from the regular
IR FP operations. Add it to some MIR tests where I think it might
matter.
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cos.s16.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum-ieee.s16.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/power-sched-no-instr-sunit.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.sin.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-intrinsic-trunc.s16.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/bundle-latency.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/regcoalescing-remove-partial-redundancy-assert.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/merge-m0.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/twoaddr-mad.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/mai-hazards.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/subreg-split-live-in-error.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ffloor.s32.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fract.s16.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ffloor.s16.mir
The file was modifiedllvm/lib/Target/AMDGPU/SIInstructions.td
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fmed3.s16.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/waitcnt-overflow.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/sdwa-gfx9.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmul.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fceil.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/sdwa-peephole-instr-gfx10.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fceil.s16.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/endpgm-dce.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rsq.legacy.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/regcoalesce-prune.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/waitcnt-permute.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/fold-imm-f16-f32.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sitofp.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fadd.s64.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmul.v2s16.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fcmp.mir
The file was modifiedllvm/unittests/MI/LiveIntervalTest.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/debug-value-scheduler-crash.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/coalescer-subregjoin-fullcopy.mir
The file was modifiedllvm/lib/Target/AMDGPU/VOP2Instructions.td
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fadd.s32.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/shrink-instructions-flags.mir
The file was modifiedllvm/lib/Target/AMDGPU/VOPCInstructions.td
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rcp.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/sdwa-peephole-instr.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fptosi.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-frint.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/waitcnt-back-edge-loop.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/dead-lane.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/twoaddr-fma.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cos.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/inserted-wait-states.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/sched-crash-dbg-value.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.ldexp.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/vccz-corrupt-bug-workaround.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum-ieee.v2s16.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/rename-independent-subregs-mac-operands.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rcp.legacy.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/fp-atomic-to-s_denormmode.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/coalescer-subranges-another-prune-error.mir
The file was modifiedllvm/lib/Target/AMDGPU/VOP3Instructions.td
The file was modifiedllvm/test/CodeGen/AMDGPU/movrels-bug.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/omod-nsz-flag.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/coalescer-subranges-another-copymi-not-live.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/smem-war-hazard.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/regcoal-subrange-join-seg.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fmad.ftz.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/hazard-hidden-bundle.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.sin.s16.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum-ieee.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/clamp-omod-special-case.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/couldnt-join-subrange-3.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fadd.s16.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fmed3.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rcp.s16.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum.s16.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/regcoal-subrange-join.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rsq.clamp.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/vcmpx-permlane-hazard.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.ldexp.s16.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/spill-empty-live-interval.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/hazard.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fma.s32.mir
The file was modifiedllvm/lib/Target/AMDGPU/SOPInstructions.td
The file was modifiedllvm/test/CodeGen/AMDGPU/hazard-kill.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/hazard-in-bundle.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fcmp.s16.mir
The file was modifiedllvm/lib/Target/AMDGPU/VOP3PInstructions.td
The file was modifiedllvm/test/CodeGen/AMDGPU/mode-register.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/sched-assert-onlydbg-value-empty-region.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/dpp_combine.mir
The file was modifiedllvm/lib/Target/AMDGPU/VOP1Instructions.td
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/hazard-buffer-store-v-interp.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/v_swap_b32.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rsq.s16.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fexp2.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum-ieee.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cvt.pkrtz.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fptoui.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-intrinsic-trunc.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum.v2s16.mir
The file was modifiedllvm/lib/Target/AMDGPU/VOPInstructions.td
The file was modifiedllvm/test/CodeGen/AMDGPU/fold-immediate-output-mods.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rsq.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/fold-vgpr-copy.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum.v2s16.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/madak-inline-constant.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/sdwa-preserve.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/cluster-flat-loads.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fcanonicalize.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/vmem-to-salu-hazard.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ffloor.s64.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum-ieee.s16.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/fix-sgpr-copies.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-frint.s16.mir
The file was modifiedllvm/lib/Target/AMDGPU/SIInstrFormats.td
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fract.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum-ieee.v2s16.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/insert-waitcnts-callee.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum.s16.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-uitofp.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/coalescer-with-subregs-bad-identical.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmad.s32.mir
Commit 48cb380abdca27d177520aea4fe4dfe8d628b466 by spatel
[InstCombine] add tests for vector demanded elements of select condition; NFC
The file was modifiedllvm/test/Transforms/InstCombine/vec_demanded_elts.ll
Commit fa3b587196dbc04e445257ae38e7906e5c0c4888 by mtrofin
[llvm]NFC] Simplify ProfileSummaryInfo state transitions

ProfileSummaryInfo is updated seldom, as result of very specific
triggers. This patch clearly demarcates state updates from read-only uses.
This, arguably, improves readability and maintainability.
The file was modifiedllvm/lib/Transforms/IPO/SampleProfile.cpp
The file was modifiedllvm/include/llvm/Analysis/ProfileSummaryInfo.h
The file was modifiedllvm/lib/Analysis/ProfileSummaryInfo.cpp
The file was modifiedllvm/lib/Transforms/Instrumentation/PGOInstrumentation.cpp
Commit 8e7e6a8d6bae19c5a18e0d0daa0614272b85598c by craig.topper
[X86] Restore selection of MULX on BMI2 targets.

Looking back over gcc and icc behavior it looks like icc does
use mulx32 on 32-bit targets and mulx64 on 64-bit targets. It's
also used when dividing i32 by constant on 32-bit targets and
i64 by constant on 64-bit targets.

gcc uses it multiplies producing a 64 bit result on 32-bit targets
and 128-bit results on a 64-bit target. gcc does not appear to use
it for division by constant.

After this patch clang is closer to the icc behavior. This
basically reverts d1c61861ddc94457b08a5a653d3908b7b38ebb22, but
there were no strong feelings at the time.

Fixes PR45518.

Differential Revision: https://reviews.llvm.org/D80498
The file was modifiedllvm/lib/Target/X86/X86ISelDAGToDAG.cpp
The file was modifiedllvm/test/CodeGen/X86/mulx64.ll
The file was modifiedllvm/test/CodeGen/X86/hoist-invariant-load.ll
The file was modifiedllvm/test/CodeGen/X86/i128-mul.ll
The file was modifiedllvm/test/CodeGen/X86/bmi2-x86_64.ll
The file was modifiedllvm/test/CodeGen/X86/atomic-unordered.ll
The file was modifiedllvm/test/CodeGen/X86/mulx32.ll
The file was modifiedllvm/test/CodeGen/X86/pr35636.ll
The file was modifiedllvm/test/CodeGen/X86/bmi2.ll
Commit fe9d8442e0dfc8c83e9a0a31f5079e7a70b54d9d by Jonas Devlieghere
[lldb/Test] Generate YAML binary in build directory

Although it's not entirely clear to me why, this test was generating its
binary in the source directory instead of the build directory. This
patch fixes that following the same approach as other tests.
The file was modifiedlldb/test/API/functionalities/show_location/TestShowLocationDwarf5.py
Commit c30c2368c77f05a1447bb7442c6ac2fad2912a57 by Jonas Devlieghere
[lldb/Reproducers] Skip tests relying on timeouts

The reproducer don't model timeouts so tests that rely on them end up
with unexpected packets during replay. Skip them until we can handle
this scenario.
The file was modifiedlldb/test/API/commands/expression/timeout/TestCallWithTimeout.py
The file was modifiedlldb/test/API/commands/expression/no-deadlock/TestExprDoesntBlock.py
Commit 334552150770faaa407fecab42f5333bb2a898a6 by Adrian Prantl
Also cache negative results in GetXcodeSDKPath (NFC)

This fixes a performance issue in the failure case.

rdar://63547920

Differential Revision: https://reviews.llvm.org/D80595
The file was modifiedlldb/source/Host/macosx/objcxx/HostInfoMacOSX.mm
Commit eb1092ada32d6855dcb4f763ce48ede21f4d7441 by Alexander Timofeev
[AMDGPU] Fix for the lost CarryOut/CarryIn register operands in S_ADD/SUB_CO_PSEUDO.

Summary: This fixes the 5b898bddff51 bug when the carry-in and carry-out registers became lost in lowering S_ADD/SUB_CO_PSEUDO.

Reviewers: rampitec, arsenm

Reviewed By: arsenm

Subscribers: msearles, arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, kerbowa, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D80158
The file was modifiedllvm/lib/Target/AMDGPU/SIInstrInfo.cpp
The file was addedllvm/test/CodeGen/AMDGPU/s_add_co_pseudo_lowering.mir
Commit d24dd2b279ffe60d579b425fb74f6e4904323a34 by dvyukov
tsan: fix test in debug mode

sanitizer-x86_64-linux-autoconf has failed after the previous tsan commit:

FAIL: ThreadSanitizer-x86_64 :: java_finalizer2.cpp (245 of 403)
******************** TEST 'ThreadSanitizer-x86_64 :: java_finalizer2.cpp' FAILED ********************
Script:
--
: 'RUN: at line 1';      /b/sanitizer-x86_64-linux-autoconf/build/tsan_debug_build/./bin/clang  --driver-mode=g++ -fsanitize=thread -Wall  -m64   -gline-tables-only -I/b/sanitizer-x86_64-linux-autoconf/build/llvm-project/compiler-rt/test/tsan/../ -std=c++11 -I/b/sanitizer-x86_64-linux-autoconf/build/llvm-project/compiler-rt/test/tsan/../ -nostdinc++ -I/b/sanitizer-x86_64-linux-autoconf/build/tsan_debug_build/tools/clang/runtime/compiler-rt-bins/lib/tsan/libcxx_tsan_x86_64/include/c++/v1 -O1 /b/sanitizer-x86_64-linux-autoconf/build/llvm-project/compiler-rt/test/tsan/java_finalizer2.cpp -o /b/sanitizer-x86_64-linux-autoconf/build/tsan_debug_build/tools/clang/runtime/compiler-rt-bins/test/tsan/X86_64Config/Output/java_finalizer2.cpp.tmp &&  /b/sanitizer-x86_64-linux-autoconf/build/tsan_debug_build/tools/clang/runtime/compiler-rt-bins/test/tsan/X86_64Config/Output/java_finalizer2.cpp.tmp 2>&1 | FileCheck /b/sanitizer-x86_64-linux-autoconf/build/llvm-project/compiler-rt/test/tsan/java_finalizer2.cpp
--
Exit Code: 1

Command Output (stderr):
--
/b/sanitizer-x86_64-linux-autoconf/build/llvm-project/compiler-rt/test/tsan/java_finalizer2.cpp:82:11: error: CHECK: expected string not found in input
// CHECK: DONE
          ^
<stdin>:1:1: note: scanning from here
FATAL: ThreadSanitizer CHECK failed: /b/sanitizer-x86_64-linux-autoconf/build/llvm-project/compiler-rt/lib/tsan/rtl/tsan_sync.cpp:69 "((*meta)) == ((0))" (0x4000003e, 0x0)
^
<stdin>:5:12: note: possible intended match here
#3 __tsan::OnUserAlloc(__tsan::ThreadState*, unsigned long, unsigned long, unsigned long, bool) /b/sanitizer-x86_64-linux-autoconf/build/llvm-project/compiler-rt/lib/tsan/rtl/tsan_mman.cpp:225:16 (java_finalizer2.cpp.tmp+0x4af407)
           ^

http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux-autoconf/builds/51143/steps/test%20tsan%20in%20debug%20compiler-rt%20build/logs/stdio

Fix heap object overlap by offsetting java heap as other tests are doing.
The file was modifiedcompiler-rt/test/tsan/java_finalizer2.cpp
Commit c593bf534222f2206f89b6a61993125b2475b954 by Jessica Paquette
[GlobalISel] Don't combine instructions which are fed by memory instructions.

If we have a memory instruction (e.g. a load), we shouldn't combine it away in
some trivial combine.

It's possible that, say, a call lives between the instructions. This could
modify the value loaded, making the load instructions not safe to fold.

Differential Revision: https://reviews.llvm.org/D80053
The file was modifiedllvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
The file was addedllvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-not-really-equiv-insts.mir
Commit 49688b3c306d0bf918c0abeee030cfd56a17c348 by michael.hliao
Fix `-Wpedantic` warning. NFC.
The file was modifiedllvm/tools/llvm-cov/CoverageFilters.h
Commit c6fa2efd481a58c979a8e9f95119b4278b13d99a by ravishankarm
[mlir][Linalg] Fix build failure from D80188

Differential Revision: https://reviews.llvm.org/D80657
The file was modifiedmlir/lib/Dialect/Linalg/Utils/Utils.cpp
Commit 79aa9bfdb819c02faa3c6c78e307b20ae7f69057 by ntv
[mlir] Fix RunnerUtils template specialization

Undoing a spurious change that broke SFINAE for some out of core use
cases.
The file was modifiedmlir/include/mlir/ExecutionEngine/CRunnerUtils.h
Commit 54b64572407c8305c7bb8cc20c46a5e0c66b2979 by aqjune
[TargetPassConfig] Add CanonicalizeFreezeInLoops before LSR

Summary:
This patch adds CanonicalizeFreezeInLoops before LSR.
Relevant patch: https://reviews.llvm.org/D77523

Reviewers: spatel, efriedma, jdoerfert, fhahn, nikic, reames, xbolva00

Reviewed By: nikic

Subscribers: xbolva00, nikic, lebedev.ri, hiraditya, llvm-commits, sanwou01, nlopes

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D77524
The file was modifiedllvm/lib/CodeGen/TargetPassConfig.cpp
The file was modifiedllvm/test/Transforms/CanonicalizeFreezeInLoops/aarch64.ll
The file was modifiedllvm/test/CodeGen/X86/O3-pipeline.ll
The file was modifiedllvm/test/CodeGen/ARM/O3-pipeline.ll
The file was modifiedllvm/test/CodeGen/AArch64/O3-pipeline.ll
Commit b2773823116157aa73ea4ac01270b22042d6bb42 by silvasean
Remove error-prone mlir::ExecutionEngine::invoke overload.

I just spent a bunch of time debugging a mysterious bug that ended being due to my SmallVector getting passed to the Args&... overload instead of the MutableArrayRef overload, with disastrous results.

I appreciate the intent of this API, but for a function that does a bunch of unsafe casts, adding in potential overload confusion is just too much C++ footgun. If we end up needing this functionality, having something like a separate `packArgs(Args&...) -> SmallVector` overload would be preferable.

Turns out this API is unused and untested (even out of tree as far as I can tell, modulo the optional passing of no args to the other invoke as I fixed in this patch), so it's an easy fix -- just delete it and touch up the other overload.

Differential Revision: https://reviews.llvm.org/D80607
The file was modifiedmlir/include/mlir/ExecutionEngine/ExecutionEngine.h
Commit 14f33575868556f928434192bd6141f4be16a7a4 by Vitaly Buka
[StackSafety] Bailout more aggressively
Many edge cases, e.g. wrapped ranges, can be processed
precisely without bailout. However it's very unlikely that
memory access with min/max integer offsets will be
classified as safe anyway.
Early bailout may help with ThinLTO where we can
drop unsafe parameters from summaries.
The file was modifiedllvm/lib/Analysis/StackSafetyAnalysis.cpp
Commit 804a39a201567f5f615246bf99cf8e8ff7e006c8 by Vitaly Buka
[NFC,StackSafety] Rename some variables
The file was modifiedllvm/lib/Analysis/StackSafetyAnalysis.cpp
Commit 03481287ca530494512d128cbbdc9c87f2d84921 by michael.hliao
Refactor argument attribute specification in intrinsic definition. NFC.

- Argument attribute needs specifiying through `ArgIndex<n>`
  (corresponding to `FirstArgIndex`) to distinguish explicitly from the
  index number from the overloaded type list.
- In addition, `RetIndex` (corresponding to `ReturnIndex`) and
  `FuncIndex` (corresponding to `FunctionIndex`) are introduced for us
  to associate attributes on the return value and potentially function
  itself.

Differential Revision: https://reviews.llvm.org/D80422
The file was modifiedllvm/utils/TableGen/IntrinsicEmitter.cpp
The file was modifiedllvm/include/llvm/IR/IntrinsicsHexagonDep.td
The file was modifiedllvm/include/llvm/IR/IntrinsicsPowerPC.td
The file was modifiedllvm/test/TableGen/GlobalISelEmitter-SDNodeXForm-timm.td
The file was modifiedllvm/include/llvm/IR/Intrinsics.td
The file was modifiedllvm/include/llvm/IR/IntrinsicsAMDGPU.td
The file was modifiedllvm/utils/TableGen/CodeGenIntrinsics.h
The file was modifiedllvm/include/llvm/IR/IntrinsicsNVVM.td
The file was modifiedllvm/include/llvm/IR/IntrinsicsXCore.td
The file was modifiedllvm/test/TableGen/immarg.td
The file was modifiedllvm/utils/TableGen/CodeGenTarget.cpp
The file was modifiedllvm/include/llvm/IR/IntrinsicsBPF.td
The file was modifiedllvm/include/llvm/IR/IntrinsicsMips.td
The file was modifiedllvm/include/llvm/IR/IntrinsicsARM.td
The file was modifiedllvm/include/llvm/IR/IntrinsicsSystemZ.td
The file was modifiedllvm/test/TableGen/GlobalISelEmitter-immarg-literal-pattern.td
The file was modifiedllvm/include/llvm/IR/IntrinsicsHexagon.td
The file was modifiedllvm/include/llvm/IR/IntrinsicsAArch64.td
The file was modifiedllvm/include/llvm/IR/IntrinsicsX86.td
The file was modifiedllvm/include/llvm/IR/IntrinsicsWebAssembly.td
The file was modifiedllvm/include/llvm/IR/IntrinsicsRISCV.td
Commit fa342b5c8054dad4cfd1032ac580d71f0f4943d3 by michael.hliao
Enable `align <n>` to be used in the intrinsic definition.

- This allow us to specify the (minimal) alignment on an intrinsic's
  arguments and, more importantly, the return value.

Differential Revision: https://reviews.llvm.org/D80422
The file was modifiedllvm/include/llvm/IR/Intrinsics.td
The file was modifiedllvm/lib/IR/Attributes.cpp
The file was modifiedllvm/include/llvm/IR/Attributes.h
The file was modifiedllvm/utils/TableGen/IntrinsicEmitter.cpp
The file was modifiedllvm/include/llvm/IR/IntrinsicsAMDGPU.td
The file was modifiedllvm/utils/TableGen/CodeGenIntrinsics.h
The file was modifiedllvm/test/CodeGen/AMDGPU/reqd-work-group-size.ll
The file was modifiedllvm/utils/TableGen/CodeGenTarget.cpp
Commit 98ef93eabd768e51aa58c7623a9fe220ab471715 by mtrofin
[llvm] Add function feature extraction analysis

Summary:
This patch introduces an analysis pass to extract function features,
which will be needed by the ML InlineAdvisor.

RFC: http://lists.llvm.org/pipermail/llvm-dev/2020-April/140763.html

Reviewers: davidxl, dblaikie, jdoerfert

Subscribers: mgorny, hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D80579
The file was modifiedllvm/lib/Passes/PassRegistry.def
The file was addedllvm/lib/Analysis/ML/InlineFeaturesAnalysis.cpp
The file was modifiedllvm/lib/Analysis/CMakeLists.txt
The file was addedllvm/lib/Analysis/ML/CMakeLists.txt
The file was modifiedllvm/unittests/Analysis/CMakeLists.txt
The file was modifiedllvm/lib/Passes/PassBuilder.cpp
The file was addedllvm/unittests/Analysis/ML/InlineFeaturesAnalysisTest.cpp
The file was addedllvm/include/llvm/Analysis/ML/InlineFeaturesAnalysis.h
The file was addedllvm/unittests/Analysis/ML/CMakeLists.txt
Commit 9546d8b108dce03e03e0448cebbca5fa0fe4be21 by silvasean
[mlir][core] Add IndexElementsAttr helpers.

Summary:
In a follow-up, I'll update the Shape dialect to use this instead of
I64ElementsAttr.

Differential Revision: https://reviews.llvm.org/D80601
The file was modifiedmlir/include/mlir/IR/Builders.h
The file was modifiedmlir/test/lib/Dialect/Test/TestOps.td
The file was modifiedmlir/lib/IR/Attributes.cpp
The file was modifiedmlir/include/mlir/IR/OpBase.td
The file was modifiedmlir/test/mlir-tblgen/types.mlir
The file was modifiedmlir/lib/IR/Builders.cpp
Commit 25132b36a8b39e7c2b0b28aa73772e57191b6df4 by silvasean
[mlir][shape] Use IndexElementsAttr in Shape dialect.

Summary:
Index is the proper type for storing shapes when constant folding, so
this fixes the previous code (which was using i64).

Differential Revision: https://reviews.llvm.org/D80600
The file was modifiedmlir/include/mlir/Dialect/Shape/IR/ShapeOps.td
The file was modifiedmlir/lib/Dialect/Shape/IR/Shape.cpp
The file was modifiedmlir/test/Dialect/Shape/canonicalize.mlir
Commit 5f97a540ad8dd4baac47873fa4bdfba2f37e0f82 by Jonas Devlieghere
[lldb/Reproducers] Differentiate active and passive replay unexpected packet.
The file was modifiedlldb/test/API/functionalities/breakpoint/scripted_bkpt/TestScriptedResolver.py
The file was modifiedlldb/test/API/functionalities/step_scripted/TestStepScripted.py
The file was modifiedlldb/test/API/lang/objc/foundation/TestRuntimeTypes.py
The file was modifiedlldb/test/API/python_api/hello_world/TestHelloWorld.py
The file was modifiedlldb/test/API/commands/process/attach-resume/TestAttachResume.py
The file was modifiedlldb/test/API/commands/command/script/TestCommandScript.py
The file was modifiedlldb/test/API/functionalities/signal/TestSendSignal.py
The file was modifiedlldb/test/API/functionalities/conditional_break/TestConditionalBreak.py
The file was modifiedlldb/test/API/commands/expression/issue_11588/Test11588.py
The file was modifiedlldb/test/API/lang/objc/print-obj/TestPrintObj.py
The file was modifiedlldb/test/API/commands/process/attach/TestProcessAttach.py
The file was modifiedlldb/test/API/lang/objc/modules/TestObjCModules.py
The file was modifiedlldb/test/API/functionalities/gdb_remote_client/TestGDBRemoteClient.py
Commit f9bea9bc4acf4c412eab4767c31674d0caa60322 by Jonas Devlieghere
[lldb/Reproducers] Skip & add FIXME to tests failing with unexpected packet.

Add skip decorator to tests failing with an unexpected packet during
passive replay.
The file was modifiedlldb/test/API/commands/expression/unwind_expression/TestUnwindExpression.py
The file was modifiedlldb/test/API/functionalities/gdb_remote_client/TestRestartBug.py
The file was modifiedlldb/test/API/lang/objc/hidden-ivars/TestHiddenIvars.py
Commit f46bb9dd5ca0b5b553590da5ff177767be0b75b5 by Louis Dionne
[NFC] Reformat TEST_FOO macros in test_macros.h

To make them easier to read and to make it easier to add new ones.
The file was modifiedlibcxx/test/support/test_macros.h
Commit a57a67c59b3f7529f4aa30009b214248772b544b by Adrian Prantl
Fix a use-after-free in GetXcodeSDKPath

Introduced in https://reviews.llvm.org/D80595. Thanks Jonas for noticing!

Differential Revision: https://reviews.llvm.org/D80666
The file was modifiedlldb/source/Host/macosx/objcxx/HostInfoMacOSX.mm
Commit 0a072b8a0da7399eeeb670330b7baeddf1bb407a by ravishankarm
[mlir][Linalg] Add missing library linkage for shared library builds.

Differential Revision: https://reviews.llvm.org/D80664
The file was modifiedmlir/lib/Dialect/Linalg/Utils/CMakeLists.txt
Commit 2d068e534f1671459e1b135852c1b3c10502e929 by amccarth
Fix Windows command line bug when last token in response file is ""

Patch by Neil Dhar <dhar@alumni.duke.edu>

Current state machine for parsing tokens from response files in Windows
does not correctly handle the case where the last token is "". The current
implementation handles the last token by only adding it if it is not empty,
however this does not cover the case where the last token is meant to be
the empty string. We can cover this case by checking whether the state
machine was last in the UNQUOTED state, which indicates that the last
character of the input was a non-whitespace character.

Differential Revision: https://reviews.llvm.org/D78346
The file was modifiedllvm/lib/Support/CommandLine.cpp
The file was modifiedllvm/unittests/Support/CommandLineTest.cpp
Commit cf86a234ba86acf0bb875e21d27833be36e08be4 by mtrofin
Fix shared libs build break introduced in rG98ef93eabd76
The file was modifiedllvm/lib/Passes/CMakeLists.txt
The file was modifiedllvm/lib/Analysis/ML/CMakeLists.txt
Commit 993bbaf6a35baed4ad3d8422a76c4311140641a8 by maskray
[MLPolicies] Fix dependency and -DBUILD_SHARED_LIBS=on builds after D80579
The file was modifiedllvm/lib/Analysis/CMakeLists.txt
The file was modifiedllvm/lib/Passes/LLVMBuild.txt
The file was modifiedllvm/lib/Analysis/ML/CMakeLists.txt
The file was modifiedllvm/lib/Analysis/LLVMBuild.txt
The file was addedllvm/lib/Analysis/ML/LLVMBuild.txt
Commit be6bffe7293c63ec874aaf21b4f768dd3f77380a by maskray
[CMake] Revert cf86a234ba86acf0bb875e21d27833be36e08be4

It is unnecessary after 993bbaf6a35baed4ad3d8422a76c4311140641a8
The file was modifiedllvm/lib/Passes/CMakeLists.txt
The file was modifiedllvm/lib/Analysis/ML/CMakeLists.txt
Commit 8aa81aaebe533d0721f1c00deeb0fc452b0147a5 by Stanislav.Mekhanoshin
AMDGPU/GlobalISel: Fixed handling of non-standard vectors

We do not have register classes for all possible vector
sizes, so round it up for extract vector element.

Also fixes selection of G_MERGE_VALUES when vectors are
not a power of two.

This has required to refactor getRegSplitParts() in way
that it can handle not just power of two vectors.

Ideally we would like RegSplitParts to be generated by
tablegen.

Differential Revision: https://reviews.llvm.org/D80457
The file was modifiedllvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-concat-vectors.mir
The file was modifiedllvm/lib/Target/AMDGPU/SIRegisterInfo.h
Commit dda82986f97747350dce4e8ebd65c27a64a37c9d by Matthew.Arsenault
DAG: Fix expansion of DYNAMIC_STACKALLOC for StackGrowsUp targets

Can't test this since I can't directly use the default expansion for
AMDGPU. It needs to scale the amount by the wave size, rather than use
the raw byte size value.
The file was modifiedllvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Commit 5e007fe9980cc44e9c4a14c9baf3bdfb012d2c18 by Matthew.Arsenault
AMDGPU: Support non-entry block static sized allocas

OpenMP emits these for some reason, so handle them. Assume these use
4096 bytes by default, with a flag to override this. Also change the
related stack assumption for calls to have a flag.
The file was addedllvm/test/CodeGen/AMDGPU/non-entry-alloca.ll
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
The file was modifiedllvm/lib/Target/AMDGPU/SIISelLowering.h
The file was modifiedllvm/lib/Target/AMDGPU/SIISelLowering.cpp
Commit ef37444058550b0f49441b994c9e9368d8e42da8 by leonardchan
[Lexer] Fix invalid suffix diagnostic for fixed-point literals

Committing on behalf of nagart, who authored this patch.

Differential Revision: https://reviews.llvm.org/D80412
The file was modifiedclang/include/clang/Basic/DiagnosticLexKinds.td
The file was modifiedclang/test/Frontend/fixed_point_errors.c
The file was modifiedclang/include/clang/Lex/LiteralSupport.h
The file was modifiedclang/lib/Lex/LiteralSupport.cpp
Commit 7392bbc3014cd1b54852aa71ac971c6c92cd1914 by Stanislav.Mekhanoshin
AMDGPU/GlobalISel: Fixed insert element for non-standard vectors

Differential Revision: https://reviews.llvm.org/D80653
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll
The file was modifiedllvm/lib/Target/AMDGPU/SIInstrInfo.cpp
Commit 2bf3fe9b6dedf727990e68244a3d637518ea8bc3 by efriedma
[TRE] Allow elimination when the returned value is non-constant

Currently we can only eliminate call return pairs that either return the
result of the call or a dynamic constant. This patch removes that
limitation.

Differential Revision: https://reviews.llvm.org/D79660
The file was modifiedllvm/test/Transforms/TailCallElim/basic.ll
The file was modifiedllvm/lib/Transforms/Scalar/TailRecursionElimination.cpp
The file was modifiedllvm/test/Transforms/TailCallElim/2010-06-26-MultipleReturnValues.ll
Commit 54d289685260da85fc43c59db2550b18df7c33a5 by maskray
[ELF] --wrap: Drop __real_ symbol from the symbol table

In D34993, we discussed and concluded that we should drop `__real_
symbol from the symbol table, but I did the opposite in D50569.
This patch is to drop `__real_` symbol.

MaskRay's note: omitting `__real_` is important if it is undefined:
otherwise a subsequent link may error due to the undefined `__real_` in .dynsym

Differential Revision: https://reviews.llvm.org/D51283
The file was modifiedlld/ELF/SymbolTable.cpp
The file was modifiedlld/test/ELF/wrap.s
The file was modifiedlld/test/ELF/wrap-no-real.s
The file was modifiedlld/test/ELF/lto/wrap-2.ll