FailedChanges

Summary

  1. [AArch64][SVE] Re-arrange definitions in AArch64SVEInstrInfo.td (NFC) (details)
  2. [lldb] Add boilerplate to recognize the .debug_tu_index section (details)
  3. [lldb]: fix typo in lldb-gdb-remote.txt (details)
  4. [Sema] Demote call-site-based 'alignment is a power of two' check for AllocAlignAttr into a warning (details)
  5. Revert "Reland "[DebugInfo] Enable the debug entry values feature by default"" (details)
  6. [clang][Index] Fix the incomplete instantiations in libindex. (details)
  7. Regenerate rotate test. NFC. (details)
  8. [AMDGPU] Don’t marke the .note section as ALLOC (details)
  9. [Utils][x86] add an option to reduce scrubbing of shuffles with memops (details)
  10. AMDGPU: Fix v2i64<->v4f32 bitcast (details)
  11. [NFC][RDA] Break-up initialization code (details)
  12. [PowerPC][NFC] We do not save/restore vrsave for any remaining subtargets. (details)
  13. [x86] regenerate test checks with less shuffle scrubbing; NFC (details)
  14. Add #include <condition_variable> to fix build after 85fb997659b5 (details)
Commit 0e417b034ad2572e5a09dbc650d351393c2b574c by andrzej.warzynski
[AArch64][SVE] Re-arrange definitions in AArch64SVEInstrInfo.td (NFC)

Re-arrange definitions related to loads and stores so that they are
grouped together.

This patch implements only non-functional changes.
The file was modifiedllvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
Commit 7b59ff2fa0a56a0158f3f21aaed217118da669a3 by pavel
[lldb] Add boilerplate to recognize the .debug_tu_index section

It's just like debug_cu_index, only for type units.
The file was modifiedlldb/include/lldb/lldb-enumerations.h
The file was modifiedlldb/test/Shell/ObjectFile/ELF/section-types.yaml
The file was modifiedlldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp
The file was modifiedlldb/source/Core/Section.cpp
The file was modifiedlldb/source/Plugins/ObjectFile/Mach-O/ObjectFileMachO.cpp
The file was modifiedlldb/source/Symbol/ObjectFile.cpp
Commit c7b7f76ae6ae2a5f3d9753b37ef811da15386cd4 by kkleine
[lldb]: fix typo in lldb-gdb-remote.txt

Summary: The logic of the sentence made more sense when "with" is replaced with "without".

Reviewers: labath

Subscribers: lldb-commits

Tags: #lldb

Differential Revision: https://reviews.llvm.org/D74895
The file was modifiedlldb/docs/lldb-gdb-remote.txt
Commit 9ea5d17cc9544838c73e593de4ef224d54fa1cff by lebedev.ri
[Sema] Demote call-site-based 'alignment is a power of two' check for AllocAlignAttr into a warning

Summary:
As @rsmith notes in https://reviews.llvm.org/D73020#inline-672219
while that is certainly UB land, it may not be actually reachable at runtime, e.g.:
```
template<int N> void *make() {
  if ((N & (N-1)) == 0)
    return operator new(N, std::align_val_t(N));
  else
    return operator new(N);
}
void *p = make<7>();
```
and we shouldn't really error-out there.

That being said, i'm not really following the logic here.
Which ones of these cases should remain being an error?

Reviewers: rsmith, erichkeane

Reviewed By: erichkeane

Subscribers: cfe-commits, rsmith

Tags: #clang

Differential Revision: https://reviews.llvm.org/D73996
The file was modifiedclang/test/Sema/alloc-align-attr.c
The file was modifiedclang/lib/Sema/SemaChecking.cpp
The file was modifiedclang/lib/CodeGen/CGCall.cpp
The file was addedclang/test/CodeGen/non-power-of-2-alignment-assumptions.c
The file was modifiedclang/include/clang/Basic/DiagnosticSemaKinds.td
The file was modifiedclang/test/SemaCXX/alloc-align-attr.cpp
Commit 2f215cf36adced6bf1abda4bdbbc6422c1369353 by djordje.todorovic
Revert "Reland "[DebugInfo] Enable the debug entry values feature by default""

This reverts commit rGfaff707db82d.
A failure found on an ARM 2-stage buildbot.
The investigation is needed.
The file was modifiedllvm/test/DebugInfo/MIR/X86/dbgcall-site-partial-describe.mir
The file was modifiedllvm/test/DebugInfo/X86/dbg-value-range.ll
The file was modifiedllvm/test/DebugInfo/X86/loclists-dwp.ll
The file was modifiedllvm/test/CodeGen/MIR/X86/call-site-info-error2.mir
The file was modifiedllvm/include/llvm/Target/TargetOptions.h
The file was modifiedllvm/test/CodeGen/AArch64/arm64-tls-dynamics.ll
The file was modifiedllvm/test/DebugInfo/MIR/Hexagon/dbgcall-site-instr-before-bundled-call.mir
The file was modifiedllvm/test/DebugInfo/MIR/ARM/if-coverter-call-site-info.mir
The file was modifiedclang/lib/CodeGen/CGDebugInfo.cpp
The file was modifiedllvm/include/llvm/Target/TargetMachine.h
The file was modifiedllvm/test/DebugInfo/X86/dbgcall-site-zero-valued-imms.ll
The file was modifiedllvm/test/DebugInfo/MIR/ARM/dbgcall-site-interpretation.mir
The file was modifiedllvm/test/DebugInfo/MIR/X86/dbg-call-site-spilled-arg.mir
The file was modifiedllvm/test/tools/llvm-dwarfdump/X86/stats-dbg-callsite-info.ll
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
The file was modifiedllvm/test/CodeGen/MIR/X86/call-site-info-error3.mir
The file was modifiedllvm/include/llvm/CodeGen/CommandFlags.inc
The file was modifiedllvm/test/DebugInfo/AArch64/call-site-info-output.ll
The file was modifiedllvm/test/DebugInfo/MIR/X86/call-site-gnu-vs-dwarf5-attrs.mir
The file was modifiedllvm/test/DebugInfo/MIR/SystemZ/call-site-lzer.mir
The file was modifiedllvm/lib/CodeGen/MachineFunction.cpp
The file was modifiedllvm/test/DebugInfo/MIR/Hexagon/live-debug-values-bundled-entry-values.mir
The file was modifiedllvm/test/CodeGen/X86/statepoint-allocas.ll
The file was modifiedllvm/test/DebugInfo/MIR/X86/propagate-entry-value-cross-bbs.mir
The file was modifiedllvm/test/CodeGen/X86/call-site-info-output.ll
The file was modifiedclang/lib/Frontend/CompilerInvocation.cpp
The file was modifiedllvm/test/DebugInfo/MIR/X86/dbgcall-site-copy-super-sub.mir
The file was modifiedllvm/lib/Target/X86/X86TargetMachine.cpp
The file was modifiedllvm/test/DebugInfo/MIR/X86/multiple-param-dbg-value-entry.mir
The file was modifiedclang/test/CodeGen/debug-info-extern-call.c
The file was modifiedllvm/test/DebugInfo/MIR/X86/dbg-call-site-spilled-arg-multiple-defs.mir
The file was modifiedllvm/test/DebugInfo/MIR/ARM/dbgcall-site-propagated-value.mir
The file was modifiedllvm/test/DebugInfo/Sparc/entry-value-complex-reg-expr.ll
The file was modifiedllvm/test/DebugInfo/MIR/X86/unreachable-block-call-site.mir
The file was modifiedclang/lib/CodeGen/BackendUtil.cpp
The file was modifiedllvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
The file was modifiedclang/include/clang/Basic/CodeGenOptions.def
The file was modifiedllvm/test/CodeGen/MIR/Hexagon/bundled-call-site-info.mir
The file was modifiedllvm/test/DebugInfo/MIR/X86/dbgcall-site-lea-interpretation.mir
The file was modifiedllvm/test/tools/llvm-dwarfdump/X86/valid-call-site-GNU-extensions.ll
The file was modifiedllvm/test/CodeGen/MIR/X86/call-site-info-error4.mir
The file was removedllvm/test/DebugInfo/X86/no-entry-values-with-O0.ll
The file was modifiedllvm/test/CodeGen/X86/hoist-invariant-load.ll
The file was modifiedllvm/test/tools/llvm-dwarfdump/X86/locstats.ll
The file was modifiedllvm/lib/Target/AArch64/AArch64TargetMachine.cpp
The file was modifiedllvm/lib/Target/ARM/ARMTargetMachine.cpp
The file was modifiedllvm/test/DebugInfo/MIR/AArch64/dbgcall-site-interpret-movzxi.mir
The file was modifiedllvm/test/CodeGen/X86/xray-typed-event-log.ll
The file was modifiedllvm/test/DebugInfo/MIR/X86/dbginfo-entryvals.mir
The file was modifiedllvm/lib/CodeGen/AsmPrinter/DwarfDebug.h
The file was modifiedllvm/lib/CodeGen/LiveDebugValues.cpp
The file was modifiedllvm/test/DebugInfo/X86/dbg-value-regmask-clobber.ll
The file was modifiedclang/test/CodeGenCXX/dbg-info-all-calls-described.cpp
The file was modifiedllvm/test/DebugInfo/MIR/X86/DW_OP_entry_value.mir
The file was modifiedllvm/test/DebugInfo/MIR/X86/kill-entry-value-after-diamond-bbs.mir
The file was modifiedllvm/test/CodeGen/AArch64/arm64-anyregcc.ll
The file was modifiedllvm/test/CodeGen/X86/xray-custom-log.ll
The file was modifiedllvm/test/DebugInfo/MIR/X86/dbgcall-site-reference.mir
The file was modifiedllvm/test/CodeGen/ARM/smml.ll
The file was modifiedllvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
The file was modifiedclang/include/clang/Driver/CC1Options.td
The file was modifiedllvm/test/CodeGen/AArch64/arm64-patchpoint.ll
The file was modifiedllvm/test/DebugInfo/MIR/X86/dbgcall-site-interpretation.mir
The file was modifiedllvm/test/DebugInfo/MIR/X86/entry-values-diamond-bbs.mir
The file was modifiedllvm/test/DebugInfo/MIR/X86/entry-value-of-modified-param.mir
The file was modifiedllvm/lib/Target/ARM/ARMISelLowering.cpp
The file was modifiedllvm/test/DebugInfo/MIR/X86/dbgcall-site-two-fwd-reg-defs.mir
The file was modifiedllvm/test/CodeGen/X86/speculative-load-hardening-indirect.ll
The file was modifiedllvm/lib/CodeGen/MIRParser/MIRParser.cpp
The file was modifiedllvm/test/CodeGen/MIR/X86/call-site-info-error1.mir
The file was modifiedlldb/test/API/functionalities/param_entry_vals/basic_entry_values_x86_64/Makefile
The file was modifiedllvm/test/tools/llvm-locstats/locstats.ll
The file was modifiedllvm/test/DebugInfo/MIR/AArch64/dbgcall-site-orr-moves.mir
The file was modifiedllvm/test/DebugInfo/ARM/call-site-info-output.ll
The file was modifiedllvm/test/DebugInfo/MIR/X86/debug-call-site-param.mir
The file was modifiedlldb/packages/Python/lldbsuite/test/decorators.py
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.cpp
The file was modifiedllvm/test/DebugInfo/X86/dbgcall-site-64-bit-imms.ll
The file was modifiedllvm/test/DebugInfo/MIR/AArch64/dbgcall-site-interpretation.mir
The file was modifiedllvm/test/DebugInfo/MIR/X86/dbgcall-site-reg-shuffle.mir
The file was modifiedllvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
The file was modifiedllvm/lib/Target/AArch64/AArch64InstrInfo.cpp
The file was modifiedllvm/test/DebugInfo/ARM/entry-value-multi-byte-expr.ll
The file was modifiedllvm/lib/CodeGen/TargetOptionsImpl.cpp
The file was modifiedllvm/test/CodeGen/X86/tail-dup-repeat.ll
The file was removedllvm/test/DebugInfo/MIR/ARM/dbgcallsite-noreg-is-imm-check.mir
Commit bb9e92bad55f65f2de58bf29548bdfd3dea2d7ab by hokein.wu
[clang][Index] Fix the incomplete instantiations in libindex.

Summary:
libindex will canonicalize references to template instantiations:
- 1) reference to an explicit template specialization, report the specializatiion
- 2) otherwise, report the primary template

but 2) is not true for incomplete instantiations, this patch fixes this.

Fixes https://github.com/clangd/clangd/issues/287

Reviewers: kadircet

Subscribers: ilya-biryukov, jkorous, arphaman, usaxena95, cfe-commits

Tags: #clang

Differential Revision: https://reviews.llvm.org/D74830
The file was modifiedclang/test/Index/Core/index-instantiated-source.cpp
The file was modifiedclang-tools-extra/clangd/unittests/XRefsTests.cpp
The file was modifiedclang/lib/Index/IndexingContext.cpp
The file was modifiedclang/test/Index/Core/index-source.cpp
Commit fa221fc6b8ac5ecd344daac634f0db8f22ebf435 by llvm-dev
Regenerate rotate test. NFC.
The file was modifiedllvm/test/CodeGen/ARM/rotate.ll
Commit 977cd661cf019039dec7ffdd15bf0ac500828c87 by sebastian.neubauer
[AMDGPU] Don’t marke the .note section as ALLOC

Marking a section as ALLOC tells the ELF loader to load the section into memory.
As we do not want to load the notes into VRAM, the flag should not be there.

Differential Revision: https://reviews.llvm.org/D74600
The file was modifiedllvm/test/CodeGen/AMDGPU/hsa.ll
The file was modifiedllvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp
Commit 15e20dcb8f9decf1928871d562a3724e8cc1e343 by spatel
[Utils][x86] add an option to reduce scrubbing of shuffles with memops

I was drafting a patch that would increase broadcast load usage,
but our shuffle scrubbing makes it impossible to see if the memory
operand offset was getting created correctly. I'm proposing to make
that an option (defaulted to 'off' for now to reduce regression
test churn).

The updated files provide examples of tests where we can now verify
that the pointer offset for a loaded memory operand is correct. We
still have stack and constant scrubbing that can obscure the operand
even if we don't scrub the entire instruction.

Differential Revision: https://reviews.llvm.org/D74775
The file was modifiedllvm/utils/update_llc_test_checks.py
The file was modifiedllvm/utils/UpdateTestChecks/asm.py
The file was modifiedllvm/test/CodeGen/X86/avx-splat.ll
The file was modifiedllvm/test/CodeGen/X86/extractelement-load.ll
Commit 083717cf49968ebb973d73b448709d45e3fc0e99 by arsenm2
AMDGPU: Fix v2i64<->v4f32 bitcast

I'm not sure how to test the v2i64->v4f32 case since I can't think of
any v2i64 cases that won't legalize to v4i32.
The file was modifiedllvm/lib/Target/AMDGPU/SIInstructions.td
The file was modifiedllvm/test/CodeGen/AMDGPU/amdgcn.bitcast.ll
Commit 659500c0c9657fc6e8d2d184b507f4e4da99297e by sam.parker
[NFC][RDA] Break-up initialization code

Separate out the initialization code from the loop traversal so
that the analysis can be reset and re-run by a user.
The file was modifiedllvm/include/llvm/CodeGen/ReachingDefAnalysis.h
The file was modifiedllvm/lib/CodeGen/ReachingDefAnalysis.cpp
Commit 45f008704df2680660ee82a7c3543d3ac9499a99 by sd.fertile
[PowerPC][NFC] We do not save/restore vrsave for any remaining subtargets.

Extend lit test to show that we don't save or restore vrsave register
when expanding @llvm.eh.unwind.init().
The file was modifiedllvm/test/CodeGen/PowerPC/unwind-dw2.ll
Commit 216a6e05249544db4c1c3f30944aba3da7463eef by spatel
[x86] regenerate test checks with less shuffle scrubbing; NFC

For shuffles with memory operands, we generally don't want to
hide the asm because we want to verify that the address offsets
are as expected.
The file was modifiedllvm/test/CodeGen/X86/masked_gather.ll
The file was modifiedllvm/test/CodeGen/X86/avx512-shuffles/partial_permute.ll
Commit 1f984c83a41bb68b8af4998a7f68876d52bff872 by hans
Add #include <condition_variable> to fix build after 85fb997659b5

See https://reviews.llvm.org/D74300#1884614
The file was modifiedllvm/lib/ExecutionEngine/Orc/Core.cpp