Changes

Changes from Git (git https://github.com/llvm/llvm-project.git)

Summary

  1. [DAGCombiner] allow more store merging for non-i8 truncated ops (details)
Commit 7a06b166b1afb457a7df6ad73a6710b4dde4db68 by spatel
[DAGCombiner] allow more store merging for non-i8 truncated ops

This is a follow-up suggested in D86420 - if we have a pair of stores
in inverted order for the target endian, we can rotate the source
bits into place.
The "be_i64_to_i16_order" test shows a limitation of the current
function (which might be avoided if we integrate this function with
the other cases in mergeConsecutiveStores). In the earlier
"be_i64_to_i16" test, we skip the first 2 stores because we do not
match the full set as consecutive or rotate-able, but then we reach
the last 2 stores and see that they are an inverted pair of 16-bit
stores. The "be_i64_to_i16_order" test alters the program order of
the stores, so we miss matching the sub-pattern.

Differential Revision: https://reviews.llvm.org/D87112
The file was modifiedllvm/test/CodeGen/AArch64/merge-trunc-store.ll
The file was modifiedllvm/test/CodeGen/X86/stores-merging.ll
The file was modifiedllvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp