Changes

Changes from Git (git https://github.com/llvm/llvm-project.git)

Summary

  1. [LSR] Canonicalize a formula before insert it into the list (details)
  2. [clang] Remove a stray semicolon, fixing pedantic GCC warnings. NFC. (details)
  3. [PowerPC] Add parentheses to silence gcc warning (details)
  4. [AARCH64][RegisterCoalescer] clang miscompiles zero-extension to long long (details)
Commit 78071fb52456f5da9d044588e58a946c0ad96830 by weiwei64
[LSR] Canonicalize a formula before insert it into the list

In GenerateConstantOffsetsImpl, we may generate non canonical Formula
if BaseRegs of that Formula is updated and includes a recurrent expr reg
related with current loop while its ScaledReg is not.

Patched by: mdchen
Reviewed By: qcolombet

Differential Revision: https://reviews.llvm.org/D86939
The file was modifiedllvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
The file was addedllvm/test/Transforms/LoopStrengthReduce/AArch64/pr47329.ll
Commit 28b9ace85f6871cdb48f1483314d8342e099b136 by martin
[clang] Remove a stray semicolon, fixing pedantic GCC warnings. NFC.
The file was modifiedclang/include/clang/AST/IgnoreExpr.h
Commit ea795304ec073a63c3c5b4fd0c5579e667201dad by mikael.holmen
[PowerPC] Add parentheses to silence gcc warning

Without gcc 7.4 warns with

../lib/Target/PowerPC/PPCInstrInfo.cpp:2284:25: warning: suggest parentheses around '&&' within '||' [-Wparentheses]
          BaseOp1.isFI() &&
          ~~~~~~~~~~~~~~~^~
              "Only base registers and frame indices are supported.");
              ~
The file was modifiedllvm/lib/Target/PowerPC/PPCInstrInfo.cpp
Commit 8ee1419ab688ee2da2ac2cb0cf19db03f4c4742e by simon.wallis2
[AARCH64][RegisterCoalescer] clang miscompiles zero-extension to long long

Implement AArch64 variant of shouldCoalesce() to detect a known failing case
and prevent the coalescing of a 32-bit copy into a 64-bit sign-extending load.

Do not coalesce in the following case:
COPY where source is bottom 32 bits of a 64-register,
and destination is a 32-bit subregister of a 64-bit register,
ie it causes the rest of the register to be implicitly set to zero.

A mir test has been added.

In the test case, the 32-bit copy implements a 32 to 64 bit zero extension
and relies on the upper 32 bits being zeroed.

Coalescing to the result of the 64-bit load meant overwriting
the upper 32 bits incorrectly when the loaded byte was negative.

Reviewed By: john.brawn

Differential Revision: https://reviews.llvm.org/D85956
The file was addedllvm/test/CodeGen/AArch64/zext-reg-coalesce.mir
The file was modifiedllvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
The file was modifiedllvm/lib/Target/AArch64/AArch64RegisterInfo.h