Started 2 mo 24 days ago
Took 6 hr 50 min

Success Build #3830 (Mar 29, 2021 7:46:52 PM)

Changes
  1. [lldb] Remove lldb-cmake-reproducers (details / githubweb)
  2. Update python deps for buildbot-mlir-nvidia. (details / githubweb)
Changes
  1. Reapply "OpaquePtr: Turn inalloca into a type attribute" (details / githubweb)
  2. [SimpleLoopUnswitch] Fix wrong assertions in partial-unswitch.ll (details / githubweb)
  3. [LV] Move runtime pointer size check to LVP::plan(). (details / githubweb)
  4. [TableGen] Add support for the 'assert' statement in class definitions. (details / githubweb)
  5. [libc++] Use _EnableIf and __iter_value_type consistently. NFCI. (details / githubweb)
  6. [mlir][Linalg] Allow calling named ops when available and make it the default. (details / githubweb)
  7. [OPENMP]Fix PR49052: Clang crashed when compiling target code with assert(0). (details / githubweb)
  8. [SLP] allow matching integer min/max intrinsics as reduction ops (details / githubweb)
  9. Revert "[LV] Move runtime pointer size check to LVP::plan()." (details / githubweb)
  10. [SystemZ][z/OS] Set maximum value to truncate attribute aligned to for static variables on z/OS target (details / githubweb)
  11. [OPENMP]Fix PR49636: Assertion `(!Entry.getAddress() || Entry.getAddress() == Addr) && "Resetting with the new address."' failed. (details / githubweb)
  12. [flang][driver] Add default intrinsic module path in f18 to make f18 behave like flang-new (with respect to the module paths), make it possible to share more tests between the drivers and make using f18 easier (the default path means that users are no longer required to specify it) (details / githubweb)
  13. [OPENMP]Map data field with l-value reference types. (details / githubweb)
  14. [SelectionDAG][AArch64][SVE] Perform SETCC condition legalization in LegalizeVectorOps (details / githubweb)
  15. Recommit "[LV] Move runtime pointer size check to LVP::plan()." (details / githubweb)
  16. [libcxx] reworks invocable and regular_invocable tests (details / githubweb)
  17. [mlir][vector] Add lowering of Transfer_read with broadcast and permutation map (details / githubweb)
  18. [lldb] Include llvm-config.h instead of config.h (details / githubweb)
  19. [SystemZ][z/OS] Add test of leading zero length bitfield in const/volatile struct (details / githubweb)
  20. [libcxx] adds std::identity to <functional> (details / githubweb)
  21. [mlir][Linalg] Drop spurious error message (details / githubweb)
  22. [flang] Update output format test to use GTest (details / githubweb)
  23. [mlir][Linalg] Rewrite SubTensors that take a slice out of a unit-extend dimension. (details / githubweb)
  24. [OpenMP] Trim error messages in CUDA plugin (details / githubweb)
  25. [lldb] Move UpdateISAToDescriptorMap into ClassInfoExtractor (NFC) (details / githubweb)
  26. [Clang] Only run test when X86 backend is built. (details / githubweb)
  27. [SampleFDO] Do not scale the magic number NOMORE_ICP_MAGICNUM in value profile (details / githubweb)
  28. [Clang] Fix line numbers in CHECK lines. (details / githubweb)
  29. [CSSPGO][llvm-profgen] Context-sensitive global pre-inliner (details / githubweb)
  30. [NFC][RISCV] Pass file through update_llc_tests to fix whitespace issues (details / githubweb)
  31. [NFC][RISCV] Add test showing wrong stack slot for GPR and RVV spilled registers (details / githubweb)
  32. [RISCV] Fix offset computation for RVV (details / githubweb)
  33. [X86] Always use rip-relative addressing on 64-bit when rematerializing all zeros/ones registers using a folded load. (details / githubweb)
  34. [flang] Fix CHECK() calls on erroneous procedure declarations (details / githubweb)
  35. [RISCV] When custom iseling masked loads/stores, copy the mask into V0 instead of virtual register. (details / githubweb)
  36. [PrologEpilogInserter][AMDGPU] Only adjust offset for emergency spill slots if the stack grows down (details / githubweb)
  37. [lldb][NFC] Fix -Wdocumentation issue in ProcessMinidump (details / githubweb)
  38. [lldb][NFC] Fix -Wdocumentation issue in ModuleSpec.h/ThreadTrace.h (details / githubweb)
  39. [AArch64] Add a few more vector extension tests. (details / githubweb)
  40. [lld-macho] Implement -segprot (details / githubweb)
  41. [AMDGPU] Mark additional VOP3 as commutable (details / githubweb)
  42. NFC: Update MLIR python bindings docs to install deps via requirements.txt. (details / githubweb)
  43. fix comment typo to cycle bots (details / githubweb)
  44. [mlir] Enhance InferShapedTypeOpInterface and move LinalgOps to use them. (details / githubweb)
  45. [lsan][test] Add malloc(0) and realloc(p, 0) tests (details / githubweb)
  46. fix comment typo to cycle bots (details / githubweb)
  47. Revert "[AMDGPU] Mark additional VOP3 as commutable" (details / githubweb)
  48. [libcxx] Use integer division (details / githubweb)
  49. [llvm-reduce] Remove dso_local when possible (details / githubweb)
  50. [AMDGPU] Fix "Sequence" spelling. NFC. (details / githubweb)

Started by upstream project clang-stage2-Rthinlto_relay build number 5669
originally caused by:

This run spent:

  • 6 hr 50 min waiting;
  • 6 hr 50 min build duration;
  • 13 hr total from scheduled to completion.
Revision: 615fc2cff345848bc0193e1bea50839270635f51
  • refs/remotes/origin/main
Revision: 619b88849e14315a03902e5b2646e57328c2afcf
  • detached
Test Result (no failures)