Changes

Summary

  1. [zorg] Add buildbot for HIP (details)
Commit c531f51254be7309a3c698db86512ed4a90fa94b by enye.shi
[zorg] Add buildbot for HIP

Build HIP tests from llvm-test-suite using AMDGPU.
Will be extended to build external repo.

Reviewed by: gkistanova

Differential Revision: https://reviews.llvm.org/D99894
The file was modifiedbuildbot/osuosl/master/config/workers.py (diff)
The file was modifiedbuildbot/osuosl/master/config/builders.py (diff)
The file was modifiedbuildbot/osuosl/master/config/status.py (diff)

Summary

  1. [gn build] (manually) port 0b2bc69ba29 (details)
  2. [lld/mac] slightly improve weak-private-extern.s test (details)
  3. [lld/mac] Implement support for .weak_def_can_be_hidden (details)
  4. [InlineSpiller] Clean-up isSpillCandBB (details)
  5. [NFC] Suppress cpplint warning in test (details)
  6. [RISCV] Implement the vneg.v builtin. (details)
  7. [X86] Enable compilation of user interrupt handlers. (details)
  8. [X86][AMX] Try to hoist AMX shapes' def (details)
  9. [X86][AMX][NFC] Avoid assert for the same immidiate value (details)
  10. [RISCV] Implement the vnot.v builtin. (details)
  11. [LoopReroll] Fix rerolling loop with extra instructions (details)
  12. [cland] Dont emit missing newline warnings when building preamble (details)
  13. [AArch64] Fix for BTI landing pad insertion with PAC-RET+bkey. (details)
  14. [GlobalISel] Remove ConstantFoldingMIRBuilder (details)
  15. [Debug-Info] change return type to void for attribute adding functions. (details)
  16. [mlir] Handle strided 1D vector transfer ops in ProgressiveVectorToSCF (details)
  17. [MLIR][NFC] Fix warning, trim includes + cleanup in AffineOps.h (details)
  18. [lldb][NFC] Delete a checked-in build log in docs/testsuite (details)
  19. [mlir] Support dimension permutations in ProgressiveVectorToSCF (details)
  20. [NewGVN] Track simplification dependencies for phi-of-ops. (details)
  21. [mlir][docs] Update `add_mlir_doc` usage (details)
  22. [mlir] Use SCF for loops in ProgressiveVectorToSCF (details)
  23. Revert "[NewGVN] Track simplification dependencies for phi-of-ops." (details)
  24. [mlir] Support broadcast dimensions in ProgressiveVectorToSCF (details)
  25. [Clang] Propagate guaranteed alignment for malloc and others (details)
  26. [mlir] Support masked 1D vector transfer ops in ProgressiveVectorToSCF (details)
Commit d1bbb8533a2294e2d2434ba8f3bb07cb39d303ba by thakis
[gn build] (manually) port 0b2bc69ba29
The file was addedllvm/utils/gn/secondary/llvm/lib/Target/WebAssembly/Utils/BUILD.gn
The file was modifiedllvm/utils/gn/secondary/llvm/lib/Target/WebAssembly/BUILD.gn (diff)
The file was modifiedllvm/utils/gn/secondary/llvm/lib/Target/WebAssembly/Disassembler/BUILD.gn (diff)
The file was modifiedllvm/utils/gn/secondary/llvm/lib/Target/WebAssembly/AsmParser/BUILD.gn (diff)
The file was modifiedllvm/utils/gn/secondary/llvm/lib/Target/WebAssembly/MCTargetDesc/BUILD.gn (diff)
Commit 88b76cb130bb88bd20c9a07dc546f5a5efc3fc20 by thakis
[lld/mac] slightly improve weak-private-extern.s test

- __got is in --bind output, so print that too (makes the test
  a bit stronger)
- WEAK_DEFINES, BINDS_TO_WEAK are in the mach-o header, so
  --private-header is enough, no need for --all-headers
  (makes the test a bit easier to work with when it fails)

Differential Revision: https://reviews.llvm.org/D101065
The file was modifiedlld/test/MachO/weak-private-extern.s (diff)
Commit a38ebed2581c7dee22f626aaf196bdba9ef9638d by thakis
[lld/mac] Implement support for .weak_def_can_be_hidden

I first had a more invasive patch for this (D101069), but while trying
to get that polished for review I realized that lld's current symbol
merging semantics mean that only a very small code change is needed.
So this goes with the smaller patch for now.

This has no effect on projects that build with -fvisibility=hidden
(e.g.  chromium), since these see .private_extern symbols instead.

It does have an effect on projects that build with -fvisibility-inlines-hidden
(e.g. llvm) in -O2 builds, where LLVM's GlobalOpt pass will promote most inline
functions from .weak_definition to .weak_def_can_be_hidden.

Before this patch:

    % ls -l out/gn/bin/clang out/gn/lib/libclang.dylib
    -rwxr-xr-x  1 thakis  staff  113059936 Apr 22 11:51 out/gn/bin/clang
    -rwxr-xr-x  1 thakis  staff   86370064 Apr 22 11:51 out/gn/lib/libclang.dylib
    % out/gn/bin/llvm-objdump --macho --weak-bind out/gn/bin/clang | wc -l
        8291
    % out/gn/bin/llvm-objdump --macho --weak-bind out/gn/lib/libclang.dylib | wc -l
        5698

With this patch:

    % ls -l out/gn/bin/clang out/gn/lib/libclang.dylib
    -rwxr-xr-x  1 thakis  staff  111721096 Apr 22 11:55 out/gn/bin/clang
    -rwxr-xr-x  1 thakis  staff   85291208 Apr 22 11:55 out/gn/lib/libclang.dylib
    thakis@MBP llvm-project % out/gn/bin/llvm-objdump --macho --weak-bind out/gn/bin/clang | wc -l
         725
    thakis@MBP llvm-project % out/gn/bin/llvm-objdump --macho --weak-bind out/gn/lib/libclang.dylib | wc -l
         542

Linking clang becomes a tiny bit faster with this patch:

    x 100    0.67263818    0.77847815    0.69430709    0.69877208   0.017715892
    + 100    0.67209601    0.73323393    0.68600798    0.68917346   0.012824377
    Difference at 95.0% confidence
            -0.00959861 +/- 0.00428661
            -1.37364% +/- 0.613449%
            (Student's t, pooled s = 0.0154648)

This only happens if lld with the patch and lld without the patch are both
linked with an lld with the patch or both linked with an lld without the patch
(...or with ld64). I accidentally linked the lld with the patch with an lld
without the patch and the other way round at first. In that setup, no
difference is found. That makese sense, since having fewer weak imports will
make the linked output a bit faster too. So not only does this make linking
binaries such as clang a bit faster (since fewer exports need to be written to
the export trie by lld), the linked output binary binary is also a bit faster
(since dyld needs to process fewer dynamic imports).

This also happens to fix the one `check-clang` failure when using lld as host
linker, but mostly for silly reasons: See crbug.com/1183336, mostly comment 26.
The real bug here is that c-index-test links all of LLVM both statically and
dynamically, which is an ODR violation. Things just happen to work with this
patch.

So after this patch, check-clang, check-lld, check-llvm all pass with lld as
host linker :)

Differential Revision: https://reviews.llvm.org/D101080
The file was modifiedlld/MachO/InputFiles.cpp (diff)
The file was addedlld/test/MachO/weak-def-can-be-hidden.s
Commit 914c8328244477d68043f36107e98794e3b9dab7 by serguei.katkov
[InlineSpiller] Clean-up isSpillCandBB

This is mostly NFC except that for end of BB not previous slot is used.
Idx is used to find a def of sibling live interval in that slot.
The def on end of MBB and on previous slot of end MBB should be the same,
so it should be NFC.

Reviewers: reames, qcolombet, MatzeB, wmi, rnk
Reviewed By: rnk
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D100922
The file was modifiedllvm/lib/CodeGen/InlineSpiller.cpp (diff)
Commit a062140a9e1e82515cd84587522794a1a21925c4 by Vitaly Buka
[NFC] Suppress cpplint warning in test
The file was modifiedcompiler-rt/test/lsan/TestCases/use_globals_unused.cpp (diff)
Commit 14cc1cb22230de433bb9eb35624355a6d0bef2d2 by kai.wang
[RISCV] Implement the vneg.v builtin.

Differential Revision: https://reviews.llvm.org/D100819
The file was modifiedclang/utils/TableGen/RISCVVEmitter.cpp (diff)
The file was addedclang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vneg.c
The file was modifiedclang/include/clang/Basic/riscv_vector.td (diff)
The file was addedclang/test/CodeGen/RISCV/rvv-intrinsics/vneg.c
Commit e8bce83996313ed3f4f5fce43107530d49fc3b64 by pengfei.wang
[X86] Enable compilation of user interrupt handlers.

Add __uintr_frame structure and use UIRET instruction for functions with
x86 interrupt calling convention when UINTR is present.

Reviewed By: LuoYuanke

Differential Revision: https://reviews.llvm.org/D99708
The file was addedllvm/test/CodeGen/X86/x86-64-intrcc-uintr.ll
The file was modifiedllvm/lib/Target/X86/X86ExpandPseudo.cpp (diff)
The file was modifiedclang/lib/Headers/uintrintrin.h (diff)
Commit 90118563ad0f133c696e070ad72761fa0daa4517 by pengfei.wang
[X86][AMX] Try to hoist AMX shapes' def

We request no intersections between AMX instructions and their shapes'
def when we insert ldtilecfg. However, this is not always ture resulting
from not only users don't follow AMX API model, but also optimizations.

This patch adds a mechanism that tries to hoist AMX shapes' def as well.
It only hoists shapes inside a BB, we can improve it for cases across
BBs in future. Currently, it only hoists shapes of which all sources' def
above the first AMX instruction. We can improve for the case that only
source that moves an immediate value to a register below AMX instruction.

Differential Revision: https://reviews.llvm.org/D101067
The file was modifiedllvm/lib/Target/X86/X86PreTileConfig.cpp (diff)
The file was modifiedllvm/test/CodeGen/X86/AMX/amx-sched.ll (diff)
Commit 53673fd1bf6f2dd94d8bb6ced49cc54ec5fc866b by pengfei.wang
[X86][AMX][NFC] Avoid assert for the same immidiate value

The previous condition in the assert was over strict. We ought to allow
the same immidiate value being loaded more than once. The intention for
the assert is to check the same AMX register uses multiple different
immidiate shapes. So this fix supposes to be NFC.

Reviewed By: LuoYuanke

Differential Revision: https://reviews.llvm.org/D101124
The file was modifiedllvm/lib/Target/X86/X86TileConfig.cpp (diff)
Commit 43cd588c2d09fdad53d143b25ecf3ddeea297caf by kai.wang
[RISCV] Implement the vnot.v builtin.

Differential Revision: https://reviews.llvm.org/D100820
The file was modifiedclang/include/clang/Basic/riscv_vector.td (diff)
The file was addedclang/test/CodeGen/RISCV/rvv-intrinsics/vnot.c
The file was addedclang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vnot.c
Commit d9a9c992d190dd6645ea911b66cf0cadba0dadc3 by t-kawashima
[LoopReroll] Fix rerolling loop with extra instructions

Fixes PR47627

This fix suppresses rerolling a loop which has an unrerollable
instruction.

Sample IR for the explanation below:

```
define void @foo([2 x i32]* nocapture %a) {
entry:
  br label %loop

loop:
  ; base instruction
  %indvar = phi i64 [ 0, %entry ], [ %indvar.next, %loop ]

  ; unrerollable instructions
  %stptrx = getelementptr inbounds [2 x i32], [2 x i32]* %a, i64 %indvar, i64 0
  store i32 999, i32* %stptrx, align 4

  ; extra simple arithmetic operations, used by root instructions
  %plus20 = add nuw nsw i64 %indvar, 20
  %plus10 = add nuw nsw i64 %indvar, 10

  ; root instruction 0
  %ldptr0 = getelementptr inbounds [2 x i32], [2 x i32]* %a, i64 %plus20, i64 0
  %value0 = load i32, i32* %ldptr0, align 4
  %stptr0 = getelementptr inbounds [2 x i32], [2 x i32]* %a, i64 %plus10, i64 0
  store i32 %value0, i32* %stptr0, align 4

  ; root instruction 1
  %ldptr1 = getelementptr inbounds [2 x i32], [2 x i32]* %a, i64 %plus20, i64 1
  %value1 = load i32, i32* %ldptr1, align 4
  %stptr1 = getelementptr inbounds [2 x i32], [2 x i32]* %a, i64 %plus10, i64 1
  store i32 %value1, i32* %stptr1, align 4

  ; loop-increment and latch
  %indvar.next = add nuw nsw i64 %indvar, 1
  %exitcond = icmp eq i64 %indvar.next, 5
  br i1 %exitcond, label %exit, label %loop

exit:
  ret void
}
```

In the loop rerolling pass, `%indvar` and `%indvar.next` are appended
to the `LoopIncs` vector in the `LoopReroll::DAGRootTracker::findRoots`
function.

Before this fix, two instructions with `unrerollable instructions`
comment above are marked as `IL_All` at the end of the
`LoopReroll::DAGRootTracker::collectUsedInstructions` function,
as well as instructions with `extra simple arithmetic operations`
comment and `loop-increment and latch` comment. It is incorrect
because `IL_All` means that the instruction should be executed in all
iterations of the rerolled loop but the `store` instruction should
not.

This fix rejects instructions which may have side effects and don't
belong to def-use chains of any root instructions and reductions.

See https://bugs.llvm.org/show_bug.cgi?id=47627 for more information.
The file was addedllvm/test/Transforms/LoopReroll/extra_instr.ll
The file was modifiedllvm/lib/Transforms/Scalar/LoopRerollPass.cpp (diff)
Commit a46bbc14f004c06bd1317e6d7a486c29133f1c0b by kadircet
[cland] Dont emit missing newline warnings when building preamble

When building preamble, clangd truncates file contents. This yielded
errnous warnings in some cases.

This patch fixes the issue by turning off no-newline-at-eof warnings whenever
the file has more contents than the preamble.

Fixes https://github.com/clangd/clangd/issues/744.

Differential Revision: https://reviews.llvm.org/D100501
The file was modifiedclang-tools-extra/clangd/Preamble.cpp (diff)
The file was modifiedclang-tools-extra/clangd/unittests/DiagnosticsTests.cpp (diff)
Commit b1f463dcae3aafadac2b6a36583f38dea6a7136e by daniel.kiss
[AArch64] Fix for BTI landing pad insertion with PAC-RET+bkey.

EMITBKEY is emitted for PAC-RET+bkey, which is a non machine instructions.

PR: 49957

Reviewed By: eugenis

Differential Revision: https://reviews.llvm.org/D100996
The file was modifiedllvm/test/CodeGen/AArch64/sign-return-address.ll (diff)
The file was modifiedllvm/lib/Target/AArch64/AArch64BranchTargets.cpp (diff)
Commit 63af3c000b3399b16703da920d874834c402e281 by jay.foad
[GlobalISel] Remove ConstantFoldingMIRBuilder

ConstantFoldingMIRBuilder was an experiment which is not used for
anything. The constant folding functionality is now part of
CSEMIRBuilder.

Differential Revision: https://reviews.llvm.org/D101050
The file was removedllvm/include/llvm/CodeGen/GlobalISel/ConstantFoldingMIRBuilder.h
The file was modifiedllvm/unittests/CodeGen/GlobalISel/PatternMatchTest.cpp (diff)
The file was modifiedllvm/unittests/CodeGen/GlobalISel/ConstantFoldingTest.cpp (diff)
Commit 027d6735ae798900293059c9dc33ea6d3ebe3615 by czhengsz
[Debug-Info] change return type to void for attribute adding functions.

Make following function return void:

    addLabel()
    addSectionLabel()
    addSectionDelta()

This aligns with other attributes adding functions.

Reviewed By: dblaikie

Differential Revision: https://reviews.llvm.org/D101022
The file was modifiedllvm/lib/CodeGen/AsmPrinter/DwarfUnit.h (diff)
The file was modifiedllvm/lib/CodeGen/AsmPrinter/DwarfUnit.cpp (diff)
Commit afaf36b69eac614f858631513c27c3af62d99da5 by springerm
[mlir] Handle strided 1D vector transfer ops in ProgressiveVectorToSCF

Strided 1D vector transfer ops are 1D transfers operating on a memref dimension different from the last one. Such transfer ops do not accesses contiguous memory blocks (vectors), but access memory in a strided fashion. In the absence of a mask, strided 1D vector transfer ops can also be lowered using matrix.column.major.* LLVM instructions (in a later commit).

Subsequent commits will extend the pass to handle the remaining missing permutation maps (broadcasts, transposes, etc.).

Differential Revision: https://reviews.llvm.org/D100946
The file was modifiedmlir/lib/Conversion/VectorToSCF/ProgressiveVectorToSCF.cpp (diff)
The file was addedmlir/test/Integration/Dialect/Vector/CPU/test-transfer-read-1d.mlir
Commit 17f6b0c36a77b521bd405bb7cccf5cd239f4330e by uday
[MLIR][NFC] Fix warning, trim includes + cleanup in AffineOps.h

Fix style/clang-tidy warning, trim stale includes and forward
declarations, and cleanup/fix stale comments.

Differential Revision: https://reviews.llvm.org/D101021
The file was modifiedmlir/include/mlir/Dialect/Affine/IR/AffineOps.h (diff)
Commit f8f3fc1fbad608ee7c7e0c2a5af0637006e1ba0c by Raphael Isemann
[lldb][NFC] Delete a checked-in build log in docs/testsuite
The file was removedlldb/docs/testsuite/2010-10-19-14_10_49.059609/TestSettings.SettingsCommandTestCase.test_set_output_path.log
Commit ab154176bfc7891979b9cd406d2e952a1764f406 by springerm
[mlir] Support dimension permutations in ProgressiveVectorToSCF

This commit adds support for dimension permutations in permutation maps of vector transfer ops.

Differential Revision: https://reviews.llvm.org/D101007
The file was modifiedmlir/test/Integration/Dialect/Vector/CPU/test-transfer-read-3d.mlir (diff)
The file was modifiedmlir/lib/Conversion/VectorToSCF/ProgressiveVectorToSCF.cpp (diff)
The file was modifiedmlir/test/Integration/Dialect/Vector/CPU/test-transfer-to-loops.mlir (diff)
The file was modifiedmlir/test/Integration/Dialect/Vector/CPU/test-transfer-read-2d.mlir (diff)
Commit 4f5da356ff35a218f23f0b0c4d08aee90da7de6e by flo
[NewGVN] Track simplification dependencies for phi-of-ops.

If we are using a simplified value, we need to add an extra
dependency this value , because changes to the class of the
simplified value may require us to invalidate any decision based on
that value.

This is done by adding such values as additional users, however the
current code does not excludes temporary instructions.

At the moment, this means that we miss those dependencies for
phi-of-ops, because they are temporary instructions at this point. We
instead need to add the extra dependencies to the root instruction of
the phi-of-ops.

This patch pushes the responsibility of adding extra users to the
callers of createExpression & performSymbolicEvaluation. At those
points, it is clearer which real instruction to pick.

Alternatively we could either pass the 'real' instruction as additional
argument or use another map, but I think the approach in the patch makes
things a bit easier to follow.

Fixes PR35074.

Reviewed By: asbirlea

Differential Revision: https://reviews.llvm.org/D99987
The file was addedllvm/test/Transforms/NewGVN/phi-of-ops-simplification-dependencies.ll
The file was modifiedllvm/lib/Transforms/Scalar/NewGVN.cpp (diff)
Commit ab78e09b9463262254347d1f050b49b611848654 by marius.brehler
[mlir][docs] Update `add_mlir_doc` usage

Updates the docs to reflect the changes introduced to the `add_mlir_doc`
CMake macro with https://reviews.llvm.org/D100517.
The file was modifiedmlir/docs/Tutorials/CreatingADialect.md (diff)
Commit f6a3e92e0a19b04320572acf3e992d45c88fc1ec by springerm
[mlir] Use SCF for loops in ProgressiveVectorToSCF

Use SCF for loops instead of Affine for loops.

Differential Revision: https://reviews.llvm.org/D101013
The file was modifiedmlir/lib/Conversion/VectorToSCF/ProgressiveVectorToSCF.cpp (diff)
Commit 74854d00e854196445727a49df58fe5768d9ed5b by flo
Revert "[NewGVN] Track simplification dependencies for phi-of-ops."

This reverts commit 4f5da356ff35a218f23f0b0c4d08aee90da7de6e.

This causes some  buildbot failures, e.g.
https://lab.llvm.org/buildbot/#/builders/139/builds/3019
The file was removedllvm/test/Transforms/NewGVN/phi-of-ops-simplification-dependencies.ll
The file was modifiedllvm/lib/Transforms/Scalar/NewGVN.cpp (diff)
Commit a819e7339315687f06f686971a649f614afbd987 by springerm
[mlir] Support broadcast dimensions in ProgressiveVectorToSCF

This commit adds support for broadcast dimensions in permutation maps of vector transfer ops.

Also fixes a bug in VectorToSCF that generated incorrect in-bounds checks for broadcast dimensions.

Differential Revision: https://reviews.llvm.org/D101019
The file was modifiedmlir/test/Integration/Dialect/Vector/CPU/test-transfer-read-1d.mlir (diff)
The file was modifiedmlir/lib/Conversion/VectorToSCF/VectorToSCF.cpp (diff)
The file was modifiedmlir/test/Integration/Dialect/Vector/CPU/test-transfer-read-2d.mlir (diff)
The file was modifiedmlir/test/Integration/Dialect/Vector/CPU/test-transfer-read-3d.mlir (diff)
The file was modifiedmlir/lib/Conversion/VectorToSCF/ProgressiveVectorToSCF.cpp (diff)
Commit c2297544c04764237cedc523083c7be2fb3833d4 by Dávid Bolvanský
[Clang] Propagate guaranteed alignment for malloc and others

LLVM should be smarter about *known* malloc's alignment and this knowledge may enable other optimizations.

Originally started as LLVM patch - https://reviews.llvm.org/D100862 but this logic should be really in Clang.

Reviewed By: rjmccall

Differential Revision: https://reviews.llvm.org/D100879
The file was modifiedclang/include/clang/Basic/TargetInfo.h (diff)
The file was modifiedclang/lib/CodeGen/CGCall.cpp (diff)
The file was addedclang/test/CodeGen/alloc-fns-alignment.c
Commit 545f98efc74bb1fb5dfa6edd2ce80b8154664741 by springerm
[mlir] Support masked 1D vector transfer ops in ProgressiveVectorToSCF

Support for masked N-D vector transfer ops will be added in a subsequent commit.

Differential Revision: https://reviews.llvm.org/D101132
The file was modifiedmlir/test/Integration/Dialect/Vector/CPU/test-transfer-read-1d.mlir (diff)
The file was modifiedmlir/lib/Conversion/VectorToSCF/ProgressiveVectorToSCF.cpp (diff)