1. [SCEV] Add tests for and/or loop guards (NFC) (details)
  2. [AArch64] Prevent spilling between ldxr/stxr pairs (details)
  3. [IndVars] Remove redundant loop invariance check (NFC) (details)
  4. [SCEV] Simplify backedge count clearing (NFC) (details)
  5. [Verifier] Slightly refactor code to reduce duplication, NFC. (details)
  6. Fix type printing of array template args (details)
  7. [X86] AMD Zen 3 Scheduler Model (details)
  8. Microoptimize dominance a bit - NFC. (details)
  9. [RISCV] Add missing frontend tests for vcompress intrinsics. (details)
  10. [lldb] [Process/FreeBSD] Fix arm64 build after RegisterInfoPOSIX_arm64 changes (details)
  11. [CVP] Add tests for mask not equal zero guard (NFC) (details)
  12. [LVI] Handle mask not equal zero conditions (details)
  13. [X32][CET] Fix size and alignment of section (details)
Commit 87f017d69f5f7266fa261cfe469cadafeb74e121 by nikita.ppv
[SCEV] Add tests for and/or loop guards (NFC)
The file was modifiedllvm/test/Analysis/ScalarEvolution/max-backedge-taken-count-guard-info.ll (diff)
Commit 4751cadcca45984d7671e594ce95aed8fe030bf1 by thatlemon
[AArch64] Prevent spilling between ldxr/stxr pairs

Apply the same logic used to check if CMPXCHG nodes should be expanded
at -O0: the register allocator may end up spilling some register in
between the atomic load/store pairs, breaking the atomicity and possibly
stalling the execution.

Fixes PR48017

Reviewed By: efriedman

Differential Revision:
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.cpp (diff)
The file was addedllvm/test/CodeGen/AArch64/atomicrmw-O0.ll
The file was modifiedllvm/test/Transforms/AtomicExpand/AArch64/expand-atomicrmw-xchg-fp.ll (diff)
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic.ll (diff)
Commit ffa5a402a93bcd3aa08a9ff97765f2a056829939 by nikita.ppv
[IndVars] Remove redundant loop invariance check (NFC)

This is checked again directly below this condition.
The file was modifiedllvm/lib/Transforms/Scalar/IndVarSimplify.cpp (diff)
Commit cc58e8918b70d5698ec06c0b6e4c6e4c27971870 by nikita.ppv
[SCEV] Simplify backedge count clearing (NFC)

This seems to be a leftover from when the BackedgeTakenInfo
stored multiple exit counts with manual memory management. At
some point this was switchted to a simple vector, and there should
be no need to micro-manage the clearing anymore. We can simply
drop the loop from the map and the the destructor do its job.
The file was modifiedllvm/include/llvm/Analysis/ScalarEvolution.h (diff)
The file was modifiedllvm/lib/Analysis/ScalarEvolution.cpp (diff)
Commit be8ad4e98e1fd26057471a98d6404bfdb00235cd by clattner
[Verifier] Slightly refactor code to reduce duplication, NFC.
The file was modifiedmlir/lib/IR/Verifier.cpp (diff)
Commit 8518742104ab075296722ef6151f65aee7a0646d by v.g.vassilev
Fix type printing of array template args

The code example:
constexpr const char kEta[] = "Eta";
template <const char*, typename T> class Column {};
using quick = Column<kEta,double>;

void lookup() {
  quick c1;;

emits error: no member named 'ls' in 'Column<&kEta, double>'. The patch fixes
the printed type name by not printing the ampersand for array types.

Differential Revision:
The file was modifiedclang/test/CodeGenCXX/debug-info-codeview-display-name.cpp (diff)
The file was modifiedclang/lib/AST/TemplateBase.cpp (diff)
The file was modifiedclang/test/SemaTemplate/temp_arg_nontype_cxx11.cpp (diff)
Commit 2b93c9c16c586c26d20a5166c6ffbd71bc85b2e6 by lebedev.ri
[X86] AMD Zen 3 Scheduler Model

Introduce basic schedule model for AMD Zen 3 CPU's, a.k.a `znver3`.

This is fully built from scratch, from llvm-mca measurements
and documented reference materials.
Nothing was copied from `znver2`/`znver1`.

I believe this is in a reasonable state of completion for inclusion,
probably better than D52779 `bdver2` was :)

* uops are pretty spot-on (at least what llvm-mca can measure)
* latency is also pretty spot-on (at least what llvm-mca can measure)
* throughput is within reason

I haven't run much benchmarks with this,
however RawSpeed benchmarks says this is beneficial:

I'll call out the obvious problems there:
* i didn't really bother with X87 instructions
* i didn't really bother with obviously-microcoded/system instructions
* There are large discrepancy in throughput for `mr` and `rm` instructions.
  I'm not really sure if it's a modelling defect that needs to be fixed,
  or it's a defect of measurments.
* Pipe distributions are probably bad :)
  I can't do much here until AMD allows that to be fixed
  by documenting the appropriate counters and updating libpfm

That being said, as @RKSimon notes:
>>! In D94395#2647381, @RKSimon wrote:
> I'll mention again that all the znver* models appear to be very inaccurate wrt SIMD/FPU instructions <...>
so how much worse this could possibly be?!

Things that aren't there:
* Various tunings: zero idioms, etc. That is follow-ups.

Differential Revision:
The file was modifiedllvm/test/tools/llvm-mca/X86/register-file-statistics.s (diff)
The file was addedllvm/test/tools/llvm-mca/X86/Znver3/resources-clflushopt.s
The file was addedllvm/test/tools/llvm-mca/X86/Znver3/resources-lea.s
The file was addedllvm/test/tools/llvm-mca/X86/Znver3/resources-popcnt.s
The file was modifiedllvm/lib/Target/X86/ (diff)
The file was addedllvm/test/tools/llvm-mca/X86/Znver3/resources-sse42.s
The file was addedllvm/test/tools/llvm-mca/X86/Znver3/resources-avx1.s
The file was addedllvm/test/tools/llvm-mca/X86/Znver3/resources-fsgsbase.s
The file was modifiedllvm/test/CodeGen/X86/x86-64-double-shifts-var.ll (diff)
The file was addedllvm/test/tools/llvm-mca/X86/Znver3/resources-x86_32.s
The file was addedllvm/test/tools/llvm-mca/X86/Znver3/resources-x87.s
The file was addedllvm/test/tools/llvm-mca/X86/Znver3/resources-sse2.s
The file was addedllvm/test/tools/llvm-mca/X86/Znver3/resources-rdseed.s
The file was addedllvm/test/tools/llvm-mca/X86/Znver3/resources-prefetchw.s
The file was addedllvm/lib/Target/X86/
The file was addedllvm/test/tools/llvm-mca/X86/Znver3/resources-x86_64.s
The file was addedllvm/test/tools/llvm-mca/X86/Znver3/resources-mwaitx.s
The file was addedllvm/test/tools/llvm-mca/X86/Znver3/partial-reg-update-4.s
The file was addedllvm/test/tools/llvm-mca/X86/Znver3/resources-fma.s
The file was addedllvm/test/tools/llvm-mca/X86/Znver3/resources-aes.s
The file was addedllvm/test/tools/llvm-mca/X86/Znver3/resources-sse4a.s
The file was addedllvm/test/tools/llvm-mca/X86/Znver3/resources-sse41.s
The file was modifiedllvm/lib/Target/X86/ (diff)
The file was addedllvm/test/tools/llvm-mca/X86/Znver3/resources-adx.s
The file was addedllvm/test/tools/llvm-mca/X86/Znver3/resources-avx2.s
The file was modifiedllvm/test/tools/llvm-mca/X86/in-order-cpu.s (diff)
The file was modifiedllvm/test/CodeGen/X86/slow-unaligned-mem.ll (diff)
The file was addedllvm/test/tools/llvm-mca/X86/Znver3/partial-reg-update-2.s
The file was addedllvm/test/tools/llvm-mca/X86/Znver3/resources-clzero.s
The file was addedllvm/test/tools/llvm-mca/X86/Znver3/resources-sse3.s
The file was addedllvm/test/tools/llvm-mca/X86/Znver3/resources-lzcnt.s
The file was addedllvm/test/tools/llvm-mca/X86/Znver3/resources-movbe.s
The file was addedllvm/test/tools/llvm-mca/X86/Znver3/partial-reg-update-3.s
The file was addedllvm/test/tools/llvm-mca/X86/Znver3/resources-bmi2.s
The file was addedllvm/test/tools/llvm-mca/X86/Znver3/resources-cmpxchg.s
The file was addedllvm/test/tools/llvm-mca/X86/Znver3/resources-ssse3.s
The file was addedllvm/test/tools/llvm-mca/X86/Znver3/resources-sse1.s
The file was addedllvm/test/tools/llvm-mca/X86/Znver3/partial-reg-update-7.s
The file was addedllvm/test/tools/llvm-mca/X86/Znver3/resources-f16c.s
The file was modifiedllvm/test/tools/llvm-mca/X86/cpus.s (diff)
The file was addedllvm/test/tools/llvm-mca/X86/Znver3/resources-bmi1.s
The file was addedllvm/test/tools/llvm-mca/X86/Znver3/resources-pclmul.s
The file was addedllvm/test/tools/llvm-mca/X86/Znver3/resources-sha.s
The file was modifiedllvm/test/tools/llvm-mca/X86/scheduler-queue-usage.s (diff)
The file was modifiedllvm/test/tools/llvm-mca/X86/read-after-ld-1.s (diff)
The file was addedllvm/test/tools/llvm-mca/X86/Znver3/partial-reg-update-5.s
The file was addedllvm/test/tools/llvm-mca/X86/Znver3/partial-reg-update-6.s
The file was addedllvm/test/tools/llvm-mca/X86/Znver3/partial-reg-update.s
The file was addedllvm/test/tools/llvm-mca/X86/Znver3/resources-cmov.s
The file was addedllvm/test/tools/llvm-mca/X86/Znver3/resources-rdrand.s
The file was addedllvm/test/tools/llvm-mca/X86/Znver3/resources-mmx.s
Commit a4c8952e6d4c67cca8387e6951e41c1bd4d5960e by clattner
Microoptimize dominance a bit - NFC.

Don't get RegionKindInterface if we won't use it. Noticed by inspection.
The file was modifiedmlir/lib/IR/Dominance.cpp (diff)
Commit f36e6e16a86eceaab39b0ac38517feb04775e0d4 by craig.topper
[RISCV] Add missing frontend tests for vcompress intrinsics.
The file was addedclang/test/CodeGen/RISCV/rvv-intrinsics/vcompress.c
The file was addedclang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vcompress.c
Commit db457e64794ccbc248236c10333db9e13c082a78 by mgorny
[lldb] [Process/FreeBSD] Fix arm64 build after RegisterInfoPOSIX_arm64 changes

Commit 88a5b35d63f927db69ec953ff487a7ba2504a610 changed the API
of RegisterInfoPOSIX_arm64 and effectively broke the FreeBSD plugin.
Update it to work with the new API.

Differential Revision:
The file was modifiedlldb/source/Plugins/Process/FreeBSD/NativeRegisterContextFreeBSD_arm64.cpp (diff)
Commit 7aafd104bfb8b2f676d9cb56dc176118260e5114 by nikita.ppv
[CVP] Add tests for mask not equal zero guard (NFC)
The file was modifiedllvm/test/Transforms/CorrelatedValuePropagation/icmp.ll (diff)
Commit db9d00c5e7b02b5fe77cb8f3c7c40405c5f1222a by nikita.ppv
[LVI] Handle mask not equal zero conditions

If V & Mask != 0, we know that at least one of the bits in Mask
must be set, so the value must be >= the lowest bit in Mask.
The file was modifiedllvm/test/Transforms/CorrelatedValuePropagation/icmp.ll (diff)
The file was modifiedllvm/lib/Analysis/LazyValueInfo.cpp (diff)
Commit f30500632b299a8f8f8a53f06efb1038eb7fa48d by harald
[X32][CET] Fix size and alignment of section

X32 uses 32-bit ELF object files with 32-bit alignment, so the section needs to be emitted as it is for X86.

Reviewed By: MaskRay

Differential Revision:
The file was modifiedllvm/test/CodeGen/X86/note-cet-property.ll (diff)
The file was modifiedllvm/lib/Target/X86/X86AsmPrinter.cpp (diff)