Changes

Summary

  1. Move code for checking loop metadata into Analysis [nfc] (details)
  2. Move variable only used inside an assert into the assert. (details)
  3. [SCEV] Use mustprogress flag on loops (in addition to function attribute) (details)
  4. [ELF][RISCV] Resolve branch relocations referencing undefined weak to current location if not using PLT (details)
  5. [ELF] Simplify getAArch64UndefinedRelativeWeakVA. NFC (details)
  6. [libc++] Remove unnecessary header in enable_view.h (which caused a cycle) (details)
  7. [LI] Add a cover function for checking if a loop is mustprogress [nfc] (details)
  8. [ARM] Fix Changed status in MVEGatherScatterLoweringPass. (details)
  9. [clang] NRVO: Improvements and handling of more cases. (details)
  10. [SimplifyCFG] avoid 'tmp' variables in test file; NFC (details)
  11. [LV] Parallel annotated loop does not imply all loads can be hoisted. (details)
  12. 2d Arm Neon sdot op, and lowering to the intrinsic. (details)
  13. [MLIR] Document that Dialect Conversion traverses in preorder (details)
  14. [AArch64][GlobalISel] Legalize scalar G_CTTZ + G_CTTZ_ZERO_UNDEF (details)
  15. [libcxx][ranges] removes default_initializable from weakly_incrementable and view (details)
  16. Preserve more MD_mem_parallel_loop_access and MD_access_group in SROA (details)
  17. [clang] Implement P2266 Simpler implicit move (details)
  18. [Profile] Handle invalid profile data (details)
  19. [IR] make -warn-frame-size into a module attr (details)
  20. [Profile] Remove redundant check (details)
  21. LoadStoreVectorizer: support different operand orders in the add sequence match (details)
  22. [static initializers] Emit global_ctors and global_dtors in reverse order when .ctors/.dtors are used. (details)
  23. [IR] Value: Fix OpCode checks (details)
  24. [RISCV] Add test cases that show failure to use some W instructions if they are proceeded by a load. NFC (details)
  25. [SDAG] Fix pow2 assumption when splitting vectors (details)
  26. [ValueTypes] Define MVTs for v6i32, v6f32, v7i32, v7f32 (details)
  27. [AArch64][GlobalISel] Fix incorrectly generating uxtw/sxtw for addressing modes. (details)
  28. [mlir][IR] Move MemRefElementTypeInterface to a new BuiltinTypeInterfaces file (details)
  29. [mlir] Add new SubElementAttr/SubElementType Interfaces (details)
  30. [mlir-ir-printing] Prefix the dump message with the split marker(// -----) (details)
  31. [Flang] Compile fix after D99459. (details)
  32. [RISCV] Use ComputeNumSignBits/MaskedValueIsZero in RISCVDAGToDAGISel::selectSExti32/selectZExti32. (details)
  33. [VectorCombine] Fix alignment in single element store (details)
Commit b6ee5f2b1df66987e65e1b636ba9ae1554b0334b by listmail
Move code for checking loop metadata into Analysis [nfc]

I need the mustprogress loop metadata in ScalarEvolution and it makes sense to keep all the accessors for quering loop metadate together.
The file was modifiedllvm/include/llvm/Analysis/LoopInfo.h (diff)
The file was modifiedllvm/lib/Transforms/Utils/LoopUtils.cpp (diff)
The file was modifiedllvm/include/llvm/Transforms/Utils/LoopUtils.h (diff)
The file was modifiedllvm/lib/Analysis/LoopInfo.cpp (diff)
Commit 1d3873d41eca67e974bafbaa91866581bcc0d973 by saugustine
Move variable only used inside an assert into the assert.

This prevents build failures with -Wunused.
The file was modifiedclang/lib/Serialization/ASTReaderStmt.cpp (diff)
Commit aaaeb4b160fe94e0ad3bcd6073eea4807f84a33a by listmail
[SCEV] Use mustprogress flag on loops (in addition to function attribute)

This addresses a performance regression reported against 3c6e4191.  That change (correctly) limited a transform based on assumed finiteness to mustprogress loops, but the previous change (38540d7) which introduced the mustprogress check utility only handled function attributes, not the loop metadata form.

It turns out that clang uses the function attribute form for C++, and the loop metadata form for C.  As a result, 3c6e4191 ended up being a large regression in practice for C code as loops weren't being considered mustprogress despite the language semantics.
The file was modifiedllvm/lib/Analysis/ScalarEvolution.cpp (diff)
The file was modifiedllvm/test/Analysis/ScalarEvolution/trip-count-unknown-stride.ll (diff)
Commit c03b6305d8419fda84a67f4fe357b69a86e4b54f by i
[ELF][RISCV] Resolve branch relocations referencing undefined weak to current location if not using PLT

In a -no-pie link we optimize R_PLT_PC to R_PC. Currently we resolve a branch
relocation to the link-time zero address. However such a choice tends to cause
relocation overflow possibility for RISC architectures.

* aarch64: GNU ld: rewrite the instruction to a NOP; ld.lld: branch to the next instruction
* mips: GNU ld: branch to the start of the text segment (?); ld.lld: branch to zero
* ppc32: GNU ld: rewrite the instruction to a NOP; ld.lld: branch to the current instruction
* ppc64: GNU ld: rewrite the instruction to a NOP; ld.lld: branch to the current instruction
* riscv: GNU ld: branch to the absolute zero address (with instruction rewriting)
* i386/x86_64: GNU ld/ld.lld: branch to the link-time zero address

I think that resolving to the same location is a good choice. The instruction,
if triggered, is clearly an undefined behavior. Resolving to the same location
can cause an infinite loop (making the user aware of the issue) while ensuring
no overflow.

Reviewed By: jrtc27

Differential Revision: https://reviews.llvm.org/D103001
The file was modifiedlld/ELF/InputSection.cpp (diff)
The file was modifiedlld/test/ELF/riscv-undefined-weak.s (diff)
Commit 0995bbdb66ebd91097c344dfc6529cd05de4818d by i
[ELF] Simplify getAArch64UndefinedRelativeWeakVA. NFC
The file was modifiedlld/ELF/InputSection.cpp (diff)
Commit 859c924c5fd58865e824b02c8bea40e7cb55456e by Louis Dionne
[libc++] Remove unnecessary header in enable_view.h (which caused a cycle)
The file was modifiedlibcxx/include/__ranges/enable_view.h (diff)
Commit 7629b2a09c169bfd7f7295deb3678f3fa7755eee by listmail
[LI] Add a cover function for checking if a loop is mustprogress [nfc]

Essentially, the cover function simply combines the loop level check and the function level scope into one call.  This simplifies several callers and is (subjectively) less error prone.
The file was modifiedllvm/include/llvm/Analysis/LoopInfo.h (diff)
The file was modifiedllvm/lib/Analysis/LoopInfo.cpp (diff)
The file was modifiedllvm/lib/Analysis/ScalarEvolution.cpp (diff)
The file was modifiedllvm/lib/Transforms/Utils/LoopUtils.cpp (diff)
The file was modifiedllvm/lib/Transforms/Scalar/LoopIdiomRecognize.cpp (diff)
Commit 5d5b686f6bf6b15b8fbd9ccf957295397f27afc9 by david.green
[ARM] Fix Changed status in MVEGatherScatterLoweringPass.

Now that we are calling SimplifyInstructionsInBlock, make sure we update
Changed when it reports alterations.
The file was modifiedllvm/lib/Target/ARM/MVEGatherScatterLowering.cpp (diff)
Commit 667fbcdd0b2ee5e78f5ce9789b862e3bbca94644 by mizvekov
[clang] NRVO: Improvements and handling of more cases.

This expands NRVO propagation for more cases:

Parse analysis improvement:
* Lambdas and Blocks with dependent return type can have their variables
  marked as NRVO Candidates.

Variable instantiation improvements:
* Fixes crash when instantiating NRVO variables in Blocks.
* Functions, Lambdas, and Blocks which have auto return type have their
  variables' NRVO status propagated. For Blocks with non-auto return type,
  as a limitation, this propagation does not consider the actual return
  type.

This also implements exclusion of VarDecls which are references to
dependent types.

Signed-off-by: Matheus Izvekov <mizvekov@gmail.com>

Reviewed By: Quuxplusone

Differential Revision: https://reviews.llvm.org/D99696
The file was modifiedclang/lib/Sema/SemaTemplateInstantiateDecl.cpp (diff)
The file was modifiedclang/include/clang/Sema/Sema.h (diff)
The file was modifiedclang/lib/Sema/Sema.cpp (diff)
The file was modifiedclang/test/CodeGen/nrvo-tracking.cpp (diff)
The file was modifiedclang/lib/Sema/SemaCoroutine.cpp (diff)
The file was modifiedclang/lib/Sema/SemaExprCXX.cpp (diff)
The file was modifiedclang/lib/Sema/SemaStmt.cpp (diff)
Commit 7b969ef8b4eb93d7a2be093b27280f12b8cd9ccb by spatel
[SimplifyCFG] avoid 'tmp' variables in test file; NFC
The file was modifiedllvm/test/Transforms/SimplifyCFG/two-entry-phi-return.ll (diff)
Commit 4f01122c3f6c70beee8f736f196a09976602685f by joachim
[LV] Parallel annotated loop does not imply all loads can be hoisted.

As noted in https://bugs.llvm.org/show_bug.cgi?id=46666, the current behavior of assuming if-conversion safety if a loop is annotated parallel (`!llvm.loop.parallel_accesses`), is not expectable, the documentation for this behavior was since removed from the LangRef again, and can lead to invalid reads.
This was observed in POCL (https://github.com/pocl/pocl/issues/757) and would require similar workarounds in current work at hipSYCL.

The question remains why this was initially added and what the implications of removing this optimization would be.
Do we need an alternative mechanism to propagate the information about legality of if-conversion?
Or is the idea that conditional loads in `#pragma clang loop vectorize(assume_safety)` can be executed unmasked without additional checks flawed in general?
I think this implication is not part of what a user of that pragma (and corresponding metadata) would expect and thus dangerous.

Only two additional tests failed, which are adapted in this patch. Depending on the further direction force-ifcvt.ll should be removed or further adapted.

Reviewed By: jdoerfert

Differential Revision: https://reviews.llvm.org/D103907
The file was removedllvm/test/Transforms/LoopVectorize/X86/force-ifcvt.ll
The file was modifiedllvm/test/Transforms/LoopVectorize/X86/tail_folding_and_assume_safety.ll (diff)
The file was modifiedllvm/lib/Transforms/Vectorize/LoopVectorizationLegality.cpp (diff)
The file was modifiedllvm/include/llvm/Transforms/Vectorize/LoopVectorizationLegality.h (diff)
Commit 20daedacca803b81db6d8773b705345702bf0fc3 by ataei
2d Arm Neon sdot op, and lowering to the intrinsic.

This adds Sdot2d op, which is similar to the usual Neon
intrinsic except that it takes 2d vector operands, reflecting the
structure of the arithmetic that it's performing: 4 separate
4-dimensional dot products, whence the vector<4x4xi8> shape.

This also adds a new pass, arm-neon-2d-to-intr, lowering
this new 2d op to the 1d intrinsic.

Reviewed By: nicolasvasilache

Differential Revision: https://reviews.llvm.org/D102504
The file was addedmlir/lib/Conversion/ArmNeon2dToIntr/CMakeLists.txt
The file was modifiedmlir/lib/Conversion/CMakeLists.txt (diff)
The file was modifiedmlir/lib/Conversion/PassDetail.h (diff)
The file was modifiedmlir/include/mlir/Dialect/ArmNeon/ArmNeon.td (diff)
The file was addedmlir/test/Dialect/ArmNeon/invalid.mlir
The file was modifiedmlir/include/mlir/Conversion/Passes.td (diff)
The file was modifiedmlir/include/mlir/Conversion/Passes.h (diff)
The file was addedmlir/test/Target/LLVMIR/arm-neon-2d.mlir
The file was addedmlir/include/mlir/Conversion/ArmNeon2dToIntr/ArmNeon2dToIntr.h
The file was addedmlir/lib/Conversion/ArmNeon2dToIntr/ArmNeon2dToIntr.cpp
Commit 4f6ec382c8b7204f3b1f48060025f970925f5804 by gcmn
[MLIR] Document that Dialect Conversion traverses in preorder

Reviewed By: rriddle

Differential Revision: https://reviews.llvm.org/D102525
The file was modifiedmlir/docs/DialectConversion.md (diff)
Commit 933df6ca796c0ace889bcc64706ec53462bd859a by Jessica Paquette
[AArch64][GlobalISel] Legalize scalar G_CTTZ + G_CTTZ_ZERO_UNDEF

This adds legalization for scalar G_CTTZ and G_CTTZ_ZERO_UNDEF. Vector support
requires handling vector G_BITREVERSE, which I haven't gotten around to yet.

For G_CTTZ_ZERO_UNDEF, we just lower it to G_CTTZ.

For G_CTTZ, we match SelectionDAG's lowering to a G_BITREVERSE + G_CTLZ.

e.g. https://godbolt.org/z/nPEseYh1s

(With this patch, we have slightly worse codegen than SDAG for types smaller
than s32; it seems like we're missing a combine.)

Also, this adds in a function to build G_BITREVERSE to MachineIRBuilder.

Differential Revision: https://reviews.llvm.org/D104065
The file was modifiedllvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.h (diff)
The file was addedllvm/test/CodeGen/AArch64/GlobalISel/legalize-cttz-zero-undef.mir
The file was modifiedllvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h (diff)
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir (diff)
The file was addedllvm/test/CodeGen/AArch64/GlobalISel/legalize-cttz.mir
The file was modifiedllvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp (diff)
Commit 462f8f06113616ac5646144972d3f453639aac69 by cjdb
[libcxx][ranges] removes default_initializable from weakly_incrementable and view

also:

* removes default constructors from predefined iterators
* makes span and string_view views

Partially implements P2325.
Partially resolves LWG3326.

Differential Revision: https://reviews.llvm.org/D102468
The file was modifiedlibcxx/include/__ranges/enable_view.h (diff)
The file was removedlibcxx/test/std/iterators/predef.iterators/insert.iterators/back.insert.iter.ops/back.insert.iter.cons/default.pass.cpp
The file was modifiedlibcxx/include/iterator (diff)
The file was modifiedlibcxx/docs/Cxx2aStatusPaperStatus.csv (diff)
The file was removedlibcxx/test/std/iterators/stream.iterators/ostream.iterator/ostream.iterator.cons.des/default.pass.cpp
The file was modifiedlibcxx/docs/Cxx2aStatusIssuesStatus.csv (diff)
The file was modifiedlibcxx/include/string_view (diff)
The file was modifiedlibcxx/test/std/containers/views/range_concept_conformance.compile.pass.cpp (diff)
The file was modifiedlibcxx/include/__ranges/concepts.h (diff)
The file was removedlibcxx/test/std/iterators/predef.iterators/insert.iterators/front.insert.iter.ops/front.insert.iter.cons/default.pass.cpp
The file was modifiedlibcxx/test/std/iterators/iterator.requirements/iterator.concepts/iterator.concept.winc/weakly_incrementable.compile.pass.cpp (diff)
The file was modifiedlibcxx/test/std/ranges/range.req/range.view/view.compile.pass.cpp (diff)
The file was modifiedlibcxx/test/std/strings/string.view/range_concept_conformance.compile.pass.cpp (diff)
The file was removedlibcxx/test/std/iterators/iterator.requirements/iterator.concepts/iterator.concept.winc/subsumption.compile.pass.cpp
The file was removedlibcxx/test/std/iterators/predef.iterators/insert.iterators/insert.iter.ops/insert.iter.cons/default.pass.cpp
The file was modifiedlibcxx/include/span (diff)
The file was modifiedlibcxx/test/std/ranges/range.req/range.view/view.subsumption.compile.pass.cpp (diff)
The file was modifiedlibcxx/include/__iterator/concepts.h (diff)
The file was removedlibcxx/test/std/iterators/stream.iterators/ostreambuf.iterator/ostreambuf.iter.cons/default.pass.cpp
Commit 41555eaf65b12db00c8a18e7fe530f72ab9ebfc0 by andrew.kaylor
Preserve more MD_mem_parallel_loop_access and MD_access_group in SROA

SROA sometimes preserves MD_mem_parallel_loop_access and MD_access_group metadata on loads/stores, and sometimes fails to do so. This change adds copying of the MD after other CreateAlignedLoad/CreateAlignedStores. Also fix a case where the metadata was being copied from a load, rather than the store.

Added a LIT test to catch one case.

Patch by Mark Mendell

Differential Revision: https://reviews.llvm.org/D103254
The file was modifiedllvm/lib/Transforms/Scalar/SROA.cpp (diff)
The file was addedllvm/test/Transforms/SROA/mem-par-metadata-sroa-cast.ll
Commit cbd0054b9eb17ec48f0702e3828209646c8f5ebd by mizvekov
[clang] Implement P2266 Simpler implicit move

This Implements [[http://www.open-std.org/jtc1/sc22/wg21/docs/papers/2021/p2266r1.html|P2266 Simpler implicit move]].

Signed-off-by: Matheus Izvekov <mizvekov@gmail.com>

Reviewed By: Quuxplusone

Differential Revision: https://reviews.llvm.org/D99005
The file was modifiedclang/test/SemaCXX/warn-return-std-move.cpp (diff)
The file was modifiedclang/lib/Sema/SemaStmt.cpp (diff)
The file was modifiedclang/test/CXX/drs/dr3xx.cpp (diff)
The file was modifiedclang/include/clang/Sema/Sema.h (diff)
The file was modifiedclang/test/SemaCXX/constant-expression-cxx14.cpp (diff)
The file was modifiedclang/test/SemaCXX/return-stack-addr.cpp (diff)
The file was modifiedclang/lib/Sema/SemaCoroutine.cpp (diff)
The file was modifiedclang/test/SemaCXX/coroutine-rvo.cpp (diff)
The file was modifiedclang/test/CXX/expr/expr.prim/expr.prim.lambda/p4-cxx14.cpp (diff)
The file was modifiedclang/test/CXX/temp/temp.decls/temp.mem/p5.cpp (diff)
The file was modifiedclang/test/SemaCXX/constant-expression-cxx11.cpp (diff)
The file was modifiedclang/lib/Sema/SemaExprCXX.cpp (diff)
The file was modifiedclang/test/SemaCXX/coroutines.cpp (diff)
The file was modifiedclang/lib/Sema/SemaType.cpp (diff)
The file was modifiedclang/test/SemaCXX/deduced-return-type-cxx14.cpp (diff)
The file was modifiedclang/test/CXX/dcl.dcl/dcl.spec/dcl.type/dcl.spec.auto/p7-cxx14.cpp (diff)
The file was modifiedclang/test/CXX/class/class.init/class.copy.elision/p3.cpp (diff)
Commit 189428c8fc2465c25efbf4f0bb73e26fecf150ce by aeubanks
[Profile] Handle invalid profile data

This mostly follows LLVM's InstrProfReader.cpp error handling.
Previously, attempting to merge corrupted profile data would result in
crashes. See https://crbug.com/1216811#c4.

Reviewed By: rnk

Differential Revision: https://reviews.llvm.org/D104050
The file was modifiedcompiler-rt/test/profile/instrprof-merge.c (diff)
The file was modifiedcompiler-rt/lib/profile/InstrProfiling.h (diff)
The file was modifiedcompiler-rt/test/profile/Linux/instrprof-merge-vp.c (diff)
The file was addedcompiler-rt/test/profile/Linux/corrupted-profile.c
The file was modifiedcompiler-rt/lib/profile/InstrProfilingMerge.c (diff)
The file was modifiedcompiler-rt/lib/profile/InstrProfilingFile.c (diff)
The file was modifiedcompiler-rt/test/profile/instrprof-without-libc.c (diff)
Commit fc018ebb608ee0c1239b405460e49f1835ab6175 by ndesaulniers
[IR] make -warn-frame-size into a module attr

-Wframe-larger-than= is an interesting warning; we can't know the frame
size until PrologueEpilogueInsertion (PEI); very late in the compilation
pipeline.

-Wframe-larger-than= was propagated through CC1 as an -mllvm flag, then
was a cl::opt in LLVM's PEI pass; this meant it was dropped during LTO
and needed to be re-specified via -plugin-opt.

Instead, make it part of the IR proper as a module level attribute,
similar to D103048. Introduce -fwarn-stack-size CC1 option.

Reviewed By: rsmith, qcolombet

Differential Revision: https://reviews.llvm.org/D103928
The file was modifiedclang/lib/CodeGen/CodeGenModule.cpp (diff)
The file was modifiedclang/lib/Driver/ToolChains/Clang.cpp (diff)
The file was modifiedllvm/test/CodeGen/ARM/warn-stack.ll (diff)
The file was modifiedllvm/include/llvm/IR/Module.h (diff)
The file was modifiedclang/include/clang/Driver/Options.td (diff)
The file was modifiedllvm/lib/CodeGen/PrologEpilogInserter.cpp (diff)
The file was modifiedllvm/lib/IR/Module.cpp (diff)
The file was addedclang/test/Driver/Wframe-larger-than.c
The file was modifiedclang/test/Misc/backend-stack-frame-diagnostics-fallback.cpp (diff)
The file was addedllvm/test/Linker/warn-stack-frame.ll
The file was modifiedclang/include/clang/Basic/CodeGenOptions.def (diff)
The file was modifiedllvm/test/CodeGen/X86/warn-stack.ll (diff)
The file was modifiedclang/test/Frontend/backend-diagnostic.c (diff)
Commit b73742bc8d2ec53f0892f1609837c088f9cfcf64 by aeubanks
[Profile] Remove redundant check

This is already checked outside the loop.

Followup to D104050.
The file was modifiedcompiler-rt/lib/profile/InstrProfilingMerge.c (diff)
Commit 119965865cc730060e4cc95690ee7dab91c2c440 by vkeles
LoadStoreVectorizer: support different operand orders in the add sequence match

First we refactor the code which does no wrapping add sequences
match: we need to allow different operand orders for
the key add instructions involved in the match.

Then we use the refactored code trying 4 variants of matching operands.

Originally the code relied on the fact that the matching operands
of the two last add instructions of memory index calculations
had the same LHS argument. But which operand is the same
in the two instructions is actually not essential, so now we allow
that to be any of LHS or RHS of each of the two instructions.
This increases the chances of vectorization to happen.

Reviewed By: volkan

Differential Revision: https://reviews.llvm.org/D103912
The file was modifiedllvm/lib/Transforms/Vectorize/LoadStoreVectorizer.cpp (diff)
The file was modifiedllvm/test/Transforms/LoadStoreVectorizer/X86/vectorize-i8-nested-add.ll (diff)
Commit 5a1589fc6d1131e6d73c498cc5987433d1c5e098 by wolfgang_pieb
[static initializers] Emit global_ctors and global_dtors in reverse order when .ctors/.dtors are used.

Reviewed By: rnk, MaskRay, efriedma

Differential Revision: https://reviews.llvm.org/D103495
The file was modifiedllvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp (diff)
The file was modifiedllvm/test/CodeGen/SPARC/constructor.ll (diff)
The file was modifiedllvm/test/CodeGen/X86/constructor.ll (diff)
The file was modifiedllvm/test/CodeGen/X86/2011-08-29-InitOrder.ll (diff)
Commit ffaca140d01b0b93723c3322b08351b03b95831f by ndesaulniers
[IR] Value: Fix OpCode checks

Value::SubclassID cannot be directly compared to Instruction enums, such as
Instruction::{Call,Invoke,CallBr}. We have to first subtract InstructionVal
from the SubclassID to get the OpCode, similar to Instruction::getOpCode().

Reviewed By: nickdesaulniers

Differential Revision: https://reviews.llvm.org/D104043
The file was modifiedllvm/lib/IR/Value.cpp (diff)
Commit b35a842581f089daa57dd7e6b78ccb08d92709b2 by craig.topper
[RISCV] Add test cases that show failure to use some W instructions if they are proceeded by a load. NFC

The loads end up becoming sextload/zextload which prevent our
isel patterns from finding the sign_extend_inreg or AND instruction
we need.

The easiest way to fix this is to use computeKnownBits or
ComputeNumSignBits in our isel matching to catch this.
The file was modifiedllvm/test/CodeGen/RISCV/rv64zbb.ll (diff)
The file was modifiedllvm/test/CodeGen/RISCV/float-convert.ll (diff)
The file was modifiedllvm/test/CodeGen/RISCV/double-convert.ll (diff)
The file was modifiedllvm/test/CodeGen/RISCV/half-convert.ll (diff)
Commit cfbb92441f17d1f5a9d9c3e195646df4117cb0ca by carl.ritson
[SDAG] Fix pow2 assumption when splitting vectors

When reducing vector builds to shuffles it possible that
the DAG combiner may try to extract invalid subvectors.

This happens as the existing code assumes vectors will be power
of 2 sizes, which is already untrue, but becomes more noticable
with v6 and v7 types.
Specifically the existing code assumes that half PowerOf2Ceil of
a given vector index will fit twice into a given vector.

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D103880
The file was modifiedllvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (diff)
Commit 2c2d2922a24b7fa8a92f38d9043ab476d330210d by carl.ritson
[ValueTypes] Define MVTs for v6i32, v6f32, v7i32, v7f32

For use in AMDGPU selection DAG.

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D103881
The file was modifiedllvm/include/llvm/Support/MachineValueType.h (diff)
The file was modifiedllvm/lib/CodeGen/ValueTypes.cpp (diff)
The file was modifiedllvm/utils/TableGen/CodeGenTarget.cpp (diff)
The file was modifiedllvm/include/llvm/CodeGen/ValueTypes.td (diff)
Commit 670edf3ee0045ce007f2f6aec94a2c3344c5682e by Amara Emerson
[AArch64][GlobalISel] Fix incorrectly generating uxtw/sxtw for addressing modes.

When the extend is from 8 or 16 bits, the addressing modes don't support those
extensions, but we weren't checking that and therefore always generated the 32->64b
extension mode. Fun.

Differential Revision: https://reviews.llvm.org/D104070
The file was modifiedllvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp (diff)
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/select-arith-extended-reg.mir (diff)
Commit f8a1d652da00ecff448213c58522da5a61d9bc4b by riddleriver
[mlir][IR] Move MemRefElementTypeInterface to a new BuiltinTypeInterfaces file

This allows for using other type interfaces in the builtin dialect, which currently results in a compile time failure (as it generates duplicate interface declarations).
The file was modifiedmlir/lib/IR/CMakeLists.txt (diff)
The file was addedmlir/include/mlir/IR/BuiltinTypeInterfaces.td
The file was modifiedmlir/include/mlir/IR/BuiltinTypes.td (diff)
The file was modifiedmlir/include/mlir/IR/CMakeLists.txt (diff)
Commit c42dd5dbb015afaef99cf876195c474c63c2393e by riddleriver
[mlir] Add new SubElementAttr/SubElementType Interfaces

These interfaces allow for a composite attribute or type to opaquely provide access to any held attributes or types. There are several intended use cases for this interface. The first of which is to allow the printer to create aliases for non-builtin dialect attributes and types. In the future, this interface will also be extended to allow for SymbolRefAttr to be placed on other entities aside from just DictionaryAttr and ArrayAttr.

To limit potential test breakages, this revision only adds the new interfaces to the builtin attributes/types that are currently hardcoded during AsmPrinter alias generation. In a followup the remaining builtin attributes/types, and non-builtin attributes/types can be extended to support it.

Differential Revision: https://reviews.llvm.org/D102945
The file was modifiedmlir/include/mlir/IR/BuiltinAttributes.td (diff)
The file was addedmlir/include/mlir/IR/SubElementInterfaces.td
The file was addedmlir/unittests/IR/SubElementInterfaceTest.cpp
The file was modifiedmlir/lib/IR/AsmPrinter.cpp (diff)
The file was modifiedmlir/include/mlir/IR/BuiltinAttributes.h (diff)
The file was modifiedmlir/lib/IR/BuiltinTypes.cpp (diff)
The file was modifiedmlir/lib/IR/BuiltinAttributes.cpp (diff)
The file was addedmlir/lib/IR/SubElementInterfaces.cpp
The file was modifiedmlir/include/mlir/IR/BuiltinTypes.h (diff)
The file was addedmlir/include/mlir/IR/SubElementInterfaces.h
The file was modifiedmlir/unittests/IR/CMakeLists.txt (diff)
The file was modifiedmlir/lib/IR/CMakeLists.txt (diff)
The file was modifiedmlir/include/mlir/IR/BuiltinTypes.td (diff)
The file was modifiedmlir/include/mlir/IR/CMakeLists.txt (diff)
Commit 8800047707a9cd86fb7143699af0e5564c28f4aa by riddleriver
[mlir-ir-printing] Prefix the dump message with the split marker(// -----)

This allows for better interaction with tools (such as mlir-lsp-server), as it separates the IR into separate modules for consecutive dumps.

Differential Revision: https://reviews.llvm.org/D104073
The file was modifiedmlir/test/Pass/ir-printing.mlir (diff)
The file was modifiedmlir/test/Pass/run-reproducer.mlir (diff)
The file was modifiedmlir/lib/Pass/IRPrinting.cpp (diff)
Commit 7836d058c7e115eace62e324ef6c01670326f518 by llvm-project
[Flang] Compile fix after D99459.

Fix Flang build after addition of a new OpenMP clauses for a Clang
patch (D99459). Flang is using TableGen to generation the declaration
of clause checks and the new clause was missing a definiton.
The file was modifiedflang/lib/Semantics/check-omp-structure.cpp (diff)
Commit 420bd5ee8ec996a2c2e305541e59465a5ba436e3 by craig.topper
[RISCV] Use ComputeNumSignBits/MaskedValueIsZero in RISCVDAGToDAGISel::selectSExti32/selectZExti32.

This helps us select W instructions in more cases. Most of the
affected tests have had the sign_extend_inreg or AND folded into
sextload/zextload.

Differential Revision: https://reviews.llvm.org/D104079
The file was modifiedllvm/test/CodeGen/RISCV/double-convert.ll (diff)
The file was modifiedllvm/test/CodeGen/RISCV/half-convert.ll (diff)
The file was modifiedllvm/test/CodeGen/RISCV/rv64zbb.ll (diff)
The file was modifiedllvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp (diff)
The file was modifiedllvm/test/CodeGen/RISCV/rem.ll (diff)
The file was modifiedllvm/test/CodeGen/RISCV/float-convert.ll (diff)
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfoB.td (diff)
Commit 2670c7dd5b25e87825edc0aca7729c1d3dba5afc by qiucofan
[VectorCombine] Fix alignment in single element store

This fixes the concern in single element store scalarization that the
alignment of new store may be larger than it should be. It calculates
the largest alignment if index is constant, and a safe one if not.

Reviewed By: lebedev.ri, spatel

Differential Revision: https://reviews.llvm.org/D103419
The file was modifiedllvm/test/Transforms/VectorCombine/load-insert-store.ll (diff)
The file was modifiedllvm/lib/Transforms/Vectorize/VectorCombine.cpp (diff)