Started 1 mo 27 days ago
Took 7 hr 37 min

Build #4303 (Jul 31, 2021 3:43:32 PM)

Changes
  1. tsan: remove "expected" races (details / githubweb)
  2. sanitizers: build tests with -g (details / githubweb)
  3. tsan: introduce Tid and StackID typedefs (details / githubweb)
  4. tsan: prevent insertion of memset into BenignRaceImpl (details / githubweb)
  5. [profile][test] Delete --path-equivalence=/tmp,%S (details / githubweb)
  6. [lldb] [DWARF-5] Be lazier about loading .dwo files (details / githubweb)
  7. [Clang][AArch64] Inline assembly support for the ACLE type 'data512_t' (details / githubweb)
  8. [AArch64] Add a Machine Value Type for 8 consecutive registers (details / githubweb)
  9. [AArch64] Legalize MVT::i64x8 in DAG isel lowering (details / githubweb)
  10. [MLIR] NFC Clean up doc comments on memref replacement utility (details / githubweb)
  11. GlobalISel: Have lowerStore handle some unaligned stores (details / githubweb)

Started by upstream project clang-stage2-Rthinlto_relay build number 6144
originally caused by:

This run spent:

  • 7 hr 46 min waiting;
  • 7 hr 37 min build duration;
  • 15 hr total from scheduled to completion.
Revision: 2ba285961959af1928e9d9535c869f3334a2030e
Repository: https://github.com/llvm/llvm-zorg.git
  • refs/remotes/origin/main
Revision: bc2cb91a20641f9685df1f3fb2ac4ea06756a252
Repository: https://github.com/llvm/llvm-project.git
  • detached
Test Result (no failures)