UnstableChanges

Summary

  1. [RISCV] Improve VMConstraint checking on more unary and nullary instructions. (details)
  2. [X86] Remove X86Fmadd SDNode from tablegen. Use standard fma instead. NFC (details)
  3. [GlobalISel] Fix assertion failures after "GlobalISel: Return APInt from getConstantVRegVal" landed. (details)
  4. [lldb] Surpress "ingoring result" warning in reproducer_handler (details)
  5. [lldb/test] Automatically skip remote lldb-server tests when applicable (details)
  6. [ARM] Add some NEON anyextend testing. NFC (details)
  7. [AArch64] Add some anyextend testing. NFC (details)
  8. [AArch64] Fix legalization of i128 ctpop without neon (details)
  9. [PatternMatch][LVI] Handle select-form and/or in LVI (details)
  10. [llvm-cov] Use is_contained (NFC) (details)
  11. [CodeGen, Transforms] Use *Map::lookup (NFC) (details)
  12. [Transforms] Use llvm::append_range (NFC) (details)
  13. [LV] Set up branch from middle block earlier. (details)
  14. [GVN] Add tests for select form of and/or (NFC) (details)
  15. [EarlyCSE] Add tests for select form of and/or (NFC) (details)
  16. [GVN] Use m_LogicalAnd/Or to propagate equality from branch conditions (details)
  17. [EarlyCSE] Use m_LogicalAnd/Or matchers to handle branch conditions (details)
  18. [ValueTracking] Add unit tests for isKnownNonZero, isImpliedCondition (NFC) (details)
  19. [GVN] Correctly set modified status when doing PRE on indices. (details)
  20. [ValueTracking] Use m_LogicalAnd/Or to look into conditions (details)
  21. [InstCombine] use poison as placeholder for undemanded elems (details)
  22. [RS4GC] Lazily set changed flag when folding single entry phis (details)
  23. [MachineSink] add threshold in machinesink pass to reduce compiling time. (details)
  24. [asan][memprof] Declare _DYNAMIC and fix -Wparentheses (details)
  25. [sanitizer] Defined SANITIZER_TEST_HAS_PVALLOC only on glibc (details)
  26. [compiler-rt][test] Make glibc-* feature detection work on a musl distribution (details)
  27. [msan] Delete unused glibc header <execinfo.h> (details)
  28. [RISCV] Pattern-match more vector-splatted constants (details)
  29. [benchmark] Fixed a build error when using CMake 3.15.1 + NDK-R20 (details)
  30. [AMDGPU][MC][NFC] Parser refactoring (details)
  31. [AMDGPU][MC] Improved errors handling for v_interp* operands (details)
  32. [RISCV] Define vmsbf.m/vmsif.m/vmsof.m/viota.m/vid.v intrinsics. (details)
  33. [AMDGPU] Split edge to make si_if dominate end_cf (details)
  34. [clangd] Add error handling (elog) in code completion. (details)
  35. [clang-tidy][NFC] Remove unnecessary headers (details)
  36. [PowerPC] Remove redundant COPY_TO_REGCLASS introduced by 8a58f21f5b6c (details)
  37. [MachO] Fix enum-int mismatch warning (details)
  38. [flang] Fix bugs in .mod file for abstract interface (details)
  39. [MIRPrinter] Fix incorrect output of unnamed stack names (details)
  40. [InstCombine] 'hoist xor-by-constant from xor-by-value': ignore constantexprs (details)
  41. [TableGen] Fix bug in !interleave operator (details)
  42. Revert "[benchmark] Fixed a build error when using CMake 3.15.1 + NDK-R20" (details)
  43. [AMDGPU][MC][NFC] Split large asm tests into smaller chunks (details)
  44. [ValueTracking] Fix isKnownNonEqual() with constexpr mul (details)
  45. [LV] Vectorize (some) early and multiple exit loops (details)
  46. Revert "[LV] Vectorize (some) early and multiple exit loops" (details)
  47. Reapply "[LV] Vectorize (some) early and multiple exit loops"" w/fix for builder (details)
  48. [libc++] Constexpr-proof some machinery in not_fn.pass.cpp. NFCI. (details)
  49. [libc++] [P1065] Constexpr invoke, reference_wrapper, mem_fn, not_fn, default_searcher. (details)
  50. [NewPM][AMDGPU] Port amdgpu-simplifylib/amdgpu-usenative (details)
  51. [libc++] Fix a test failure in 7b00e9fae3 (D93815). (details)
  52. [lldb] Deduplicate some lldb-server tests (details)
  53. [RISCV] Adjust tested vor ops for more stable tests. NFC. (details)
  54. [CodeGen][ObjC] Destroy callee-destroyed arguments in the caller (details)
  55. [AMDGPU][MC][NFC] Added more tests for flat_global (details)
  56. [PowerPC] Parse and ignore .machine (details)
  57. [SimplifyCFG] FoldBranchToCommonDest: gracefully handle unreachable code () (details)
  58. [IR] Make Value::getType() work better with invalid IR. (details)
  59. [InstSimplify] add tests for ctpop; NFC (PR48608) (details)
  60. [InstSimplify] remove ctpop of 1 (low) bit (details)
  61. [NFC][sanitizer] Remove unused typedef (details)
  62. [InstCombine] Disable unsafe select transform behind a flag (details)
  63. [ValueTracking] Implement impliesPoison (details)
  64. [WebAssembly][NFC] Finish cleaning up SIMD tablegen (details)
  65. [NewPM] Fix CGSCCOptimizerLateEPCallbacks place in pipeline (details)
  66. [WebAssembly] Prototype extending pairwise add instructions (details)
  67. [MLIR][NFC] Change FunctionLike::setAllArgAttrs/setAllResultAttrs to do a one-shot attribute update. (details)
  68. [IROutliner] Adding support for consolidating functions with different output arguments. (details)
  69. [test] Fix pr45360.ll under NPM (details)
  70. Fix PR35902: incorrect alignment used for ubsan check. (details)
  71. [libc++] Fix a test failure in 7b00e9fae3 (D93815). (details)
  72. [flang] Detect call to abstract interface (details)
  73. [NewPM][CodeGen] Introduce CodeGenPassBuilder to help build codegen pipeline (details)
  74. Revert "[NewPM][CodeGen] Introduce CodeGenPassBuilder to help build codegen pipeline" (details)
  75. [AMDGPU][NewPM] Port amdgpu-promote-alloca(-to-vector) (details)
  76. [PowerPC] Do not emit HW loop when TLS var accessed in PHI of loop exit (details)
  77. [UpdateTestChecks] Fix update_analyze_test_checks.py failure (details)
  78. [RISCV] Define vmclr.m/vmset.m intrinsics. (details)
  79. [IROutliner] Merging identical output blocks for extracted functions. (details)
  80. [CodeGen] Use llvm::append_range (NFC) (details)
  81. [Scalar] Construct SmallVector with iterator ranges (NFC) (details)
  82. [CFGPrinter] Use succ_empty (NFC) (details)
  83. [asan][test] Annotate glibc specific tests with REQUIRES: glibc-2.27 (details)
  84. [NewPM] Port infer-address-spaces (details)
  85. [test] Fix conditional-temporaries.cpp (details)
  86. [ubsan][test] FLush stdout before checking interleaved stdout/stderr (details)
  87. [lldb] Fix logging in lldb-server tests (details)
  88. [LLD][ELF] - Use LLVM_ELF_IMPORT_TYPES_ELFT instead of multiple types definitions. NFCI. (details)
  89. Precommit tests that have poison as shufflevector's placeholder (details)
  90. [lldb] Deduplicate some tests in TestLldbGdbServer (details)
  91. [ARM][AArch64] Add Cortex-A78C Support for Clang and LLVM (details)
  92. [PowerPC] Disable CTR loops containing operations on half-precision (details)
  93. [RISCV] Rewrite and simplify helper function. NFC. (details)
  94. [PowerPC] Provide patterns for permuted scalar to vector for pre-P8 (details)
  95. [InstCombine] 'hoist xor-by-constant from xor-by-value': completely give up on constant exprs (details)
  96. RegionInfo: use a range-based for loop [NFCI] (details)
Commit 76202f09b522b2c106b358570c97eee7797e1ba5 by craig.topper
[RISCV] Improve VMConstraint checking on more unary and nullary instructions.

We weren't consistently marking unary instructions as OneInput
and vid.v is really ZeroInput but we had no way to mark that.

This patch improves this by removing the error prone OneInput constraint.
Instead we just always look for the mask in the last operand.

It appears that the "CheckReg" variable used for the check on the broken
instruction was unitialized or garbage because it was also used for
VS1/VS2 constraints. I've scoped the variable locally to each check now.

I've gone through and set NoConstraint on instructions that don't have
a real VMConstraint and don't have a mask as the last operand.

I've also removed the unused enum values in RISCVBaseInfo.h. We
never use them in C++ and we have separate versions in a td file.

Reviewed By: HsiangKai

Differential Revision: https://reviews.llvm.org/D93784
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrFormats.td
The file was modifiedllvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfoV.td
The file was modifiedllvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h
The file was modifiedllvm/test/MC/RISCV/rvv/invalid.s
Commit 33051d5d61f23a21940325147d71bb816d3da3e8 by craig.topper
[X86] Remove X86Fmadd SDNode from tablegen. Use standard fma instead. NFC

I guess I missed this in 4252f7773a5b98b825d17e5f77c7d349cb2fb7c7
when I modified most patterns.
The file was modifiedllvm/lib/Target/X86/X86InstrFragmentsSIMD.td
The file was modifiedllvm/lib/Target/X86/X86InstrAVX512.td
Commit 7df3544e80fb40c742707613cd39ca77f7fea558 by Amara Emerson
[GlobalISel] Fix assertion failures after "GlobalISel: Return APInt from getConstantVRegVal" landed.

APInt binary ops don't promote types but instead assert, which a combine was
relying on.
The file was addedllvm/test/CodeGen/AArch64/GlobalISel/combine-shift-immed-mismatch-crash.mir
The file was modifiedllvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
Commit aca4488847b4ddceeda8d4ddb2cd9cb3defbab0c by pavel
[lldb] Surpress "ingoring result" warning in reproducer_handler
The file was modifiedlldb/tools/driver/Driver.cpp
Commit bd39a5cb30a34547eb56a81eb7ca8aca23544099 by pavel
[lldb/test] Automatically skip remote lldb-server tests when applicable

The tests don't work with remote debugservers. This isn't a problem with
any particular test, but the test infrastructure itself, which is why
each of these tests has a @skipIfDarwinEmbedded decorator.

This patch replaces that with a central category-based solution. It also
moves the ad-hoc windows skipping mechanism there too.
The file was modifiedlldb/test/API/tools/lldb-server/TestGdbRemoteHostInfo.py
The file was modifiedlldb/test/API/tools/lldb-server/TestGdbRemoteKill.py
The file was modifiedlldb/test/API/tools/lldb-server/TestGdbRemoteCompletion.py
The file was modifiedlldb/test/API/tools/lldb-server/TestGdbRemoteSingleStep.py
The file was modifiedlldb/test/API/tools/lldb-server/TestLldbGdbServer.py
The file was modifiedlldb/test/API/tools/lldb-server/TestGdbRemote_qThreadStopInfo.py
The file was modifiedlldb/packages/Python/lldbsuite/test/dotest.py
The file was modifiedlldb/test/API/tools/lldb-server/TestGdbRemoteProcessInfo.py
The file was modifiedlldb/test/API/tools/lldb-server/TestGdbRemoteAttach.py
The file was modifiedlldb/test/API/tools/lldb-server/TestGdbRemoteExitCode.py
The file was modifiedlldb/test/API/tools/lldb-server/inferior-crash/TestGdbRemoteAbort.py
The file was modifiedlldb/test/API/tools/lldb-server/TestGdbRemoteExpeditedRegisters.py
The file was modifiedlldb/test/API/tools/lldb-server/register-reading/TestGdbRemoteGPacket.py
The file was modifiedlldb/test/API/tools/lldb-server/inferior-crash/TestGdbRemoteSegFault.py
The file was modifiedlldb/packages/Python/lldbsuite/test/tools/lldb-server/gdbremote_testcase.py
The file was modifiedlldb/test/API/tools/lldb-server/TestGdbRemoteRegisterState.py
The file was modifiedlldb/test/API/tools/lldb-server/TestGdbRemoteThreadsInStopReply.py
The file was modifiedlldb/test/API/tools/lldb-server/commandline/TestGdbRemoteConnection.py
The file was modifiedlldb/test/API/tools/lldb-server/TestGdbRemoteAuxvSupport.py
Commit 7a3e11fe96dd4ede17a194c6f407b7867a1137b8 by david.green
[ARM] Add some NEON anyextend testing. NFC

This cleans up and regenerates the NEON addw/addl/subw/subl/mlal etc
tests, adding some tests that turn the zext into anyextend using an and
mask.
The file was modifiedllvm/test/CodeGen/ARM/vadd.ll
The file was modifiedllvm/test/CodeGen/ARM/vmls.ll
The file was modifiedllvm/test/CodeGen/ARM/vsub.ll
The file was modifiedllvm/test/CodeGen/ARM/vmla.ll
The file was modifiedllvm/test/CodeGen/ARM/vmul.ll
Commit 0c6e19b705819a42112bd2211e4bfa1310b24487 by david.green
[AArch64] Add some anyextend testing. NFC

This cleans up and regenerates the NEON addw/addl/subw/subl/mlal etc
tests, adding some tests that turn the zext into anyextend using an and
mask.
The file was modifiedllvm/test/CodeGen/AArch64/arm64-neon-3vdiff.ll
The file was modifiedllvm/test/CodeGen/AArch64/aarch64-smull.ll
Commit fb77d95022198edebde3e4cb2807eaeea2156d85 by nikita.ppv
[AArch64] Fix legalization of i128 ctpop without neon

If neon is disabled, LowerCTPOP will return SDValue() to indicate
that normal legalization should be used. However, ReplaceNodeResults
does not check for this and pushes the empty SDValue() onto the
result vector, which will subsequently result in a crash.

Differential Revision: https://reviews.llvm.org/D93825
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.cpp
The file was addedllvm/test/CodeGen/AArch64/ctpop-nonean.ll
Commit 0af42d3dc73e8f08e37811131c31358ecb9adf20 by nikita.ppv
[PatternMatch][LVI] Handle select-form and/or in LVI

Following the discussion in D93065, this adds m_LogicalAnd() and
m_LogicalOr() matchers, that match A && B and A || B logical
operations, either as bitwise operations or select expressions.
As an example usage, LVI is adapted to use these matchers for its
condition reasoning.

The plan here is to switch other parts of LLVM that reason about
and/or of conditions to also support the select forms, and then
merge D93065 (or a variant thereof) to disable the poison-unsafe
select to and/or transform.

Differential Revision: https://reviews.llvm.org/D93827
The file was modifiedllvm/lib/Analysis/LazyValueInfo.cpp
The file was modifiedllvm/include/llvm/IR/PatternMatch.h
The file was modifiedllvm/test/Transforms/CorrelatedValuePropagation/basic.ll
Commit 079923309c6e8ef054555f015a49f41f46b41b2e by kazu
[llvm-cov] Use is_contained (NFC)
The file was modifiedllvm/tools/llvm-size/llvm-size.cpp
Commit 789d25061363a737d6211f86f1e4a4bb10c6e4f8 by kazu
[CodeGen, Transforms] Use *Map::lookup (NFC)
The file was modifiedllvm/lib/Transforms/Utils/SSAUpdater.cpp
The file was modifiedllvm/lib/Transforms/Utils/Evaluator.cpp
The file was modifiedllvm/include/llvm/CodeGen/ScheduleDAGInstrs.h
The file was modifiedllvm/lib/CodeGen/AsmPrinter/DwarfDebug.h
The file was modifiedllvm/lib/Transforms/Vectorize/VPlan.h
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp
The file was modifiedllvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
The file was modifiedllvm/lib/CodeGen/MIRParser/MIParser.cpp
Commit 8299fb8f2564b807f7fd349f31d947930eabcaab by kazu
[Transforms] Use llvm::append_range (NFC)
The file was modifiedllvm/lib/Transforms/IPO/WholeProgramDevirt.cpp
The file was modifiedllvm/lib/Transforms/Instrumentation/DataFlowSanitizer.cpp
The file was modifiedllvm/lib/Transforms/Scalar/LoopSink.cpp
The file was modifiedllvm/lib/Transforms/Scalar/LoopUnswitch.cpp
The file was modifiedllvm/lib/Transforms/IPO/LowerTypeTests.cpp
The file was modifiedllvm/lib/Transforms/Instrumentation/ControlHeightReduction.cpp
The file was modifiedllvm/lib/Transforms/Scalar/GuardWidening.cpp
The file was modifiedllvm/lib/Transforms/IPO/ArgumentPromotion.cpp
The file was modifiedllvm/lib/Transforms/Utils/InlineFunction.cpp
The file was modifiedllvm/lib/Transforms/Utils/BuildLibCalls.cpp
The file was modifiedllvm/lib/Transforms/Scalar/PlaceSafepoints.cpp
The file was modifiedllvm/lib/Transforms/Scalar/RewriteStatepointsForGC.cpp
Commit 0ea3749b3cde16d70c5f66357b623c8edf521f2b by flo
[LV] Set up branch from middle block earlier.

Previously the branch from the middle block to the scalar preheader & exit
was being set-up at the end of skeleton creation in completeLoopSkeleton.
Inserting SCEV or runtime checks may result in LCSSA phis being created,
if they are required. Adjusting branches afterwards may break those
PHIs.

To avoid this, we can instead create the branch from the middle block
to the exit after we created the middle block, so we have the final CFG
before potentially adjusting/creating PHIs.

This fixes a crash for the included test case. For the non-crashing
case, this is almost a NFC with respect to the generated code. The
only change is the order of the predecessors of the involved branch
targets.

Note an assertion was moved from LoopVersioning() to
LoopVersioning::versionLoop. Adjusting the branches means loop-simplify
form may be broken before constructing LoopVersioning. But LV only uses
LoopVersioning to annotate the loop instructions with !noalias metadata,
which does not require loop-simplify form.

This is a fix for an existing issue uncovered by D93317.
The file was modifiedllvm/lib/Transforms/Utils/LoopVersioning.cpp
The file was modifiedllvm/test/Transforms/LoopVectorize/SystemZ/predicated-first-order-recurrence.ll
The file was modifiedllvm/lib/Transforms/Vectorize/LoopVectorize.cpp
The file was addedllvm/test/Transforms/LoopVectorize/skeleton-lcssa-crash.ll
The file was modifiedllvm/test/Transforms/LoopVectorize/first-order-recurrence.ll
Commit 0d05c1f40d691ad492383b6bc2fd7b0703099e07 by aqjune
[GVN] Add tests for select form of and/or (NFC)
The file was modifiedllvm/test/Transforms/GVN/condprop.ll
Commit 0060f1013453d4ecaac8b62fb54044285a16a379 by aqjune
[EarlyCSE] Add tests for select form of and/or (NFC)
The file was modifiedllvm/test/Transforms/EarlyCSE/and_or.ll
Commit f1d648b973d32ab0e70ef20efb0f146240e50f58 by aqjune
[GVN] Use m_LogicalAnd/Or to propagate equality from branch conditions

This patch makes GVN recognize `select c1, c2, false` as well as `select c1, true, c2`
branch condition and propagate equality from these.

See llvm.org/pr48353, D93065

Differential Revision: https://reviews.llvm.org/D93841
The file was modifiedllvm/test/Transforms/GVN/condprop.ll
The file was modifiedllvm/lib/Transforms/Scalar/GVN.cpp
Commit d3f1f7b6bca585b76d40422e8076d59113e3bb80 by aqjune
[EarlyCSE] Use m_LogicalAnd/Or matchers to handle branch conditions

EarlyCSE's handleBranchCondition says:

```
// If the condition is AND operation, we can propagate its operands into the
// true branch. If it is OR operation, we can propagate them into the false
// branch.
```

This holds for the corresponding select patterns as well.

This is a part of an ongoing work for disabling buggy select->and/or transformations.
See llvm.org/pr48353 and D93065 for more context

Proof:
and: https://alive2.llvm.org/ce/z/MQWodU
or: https://alive2.llvm.org/ce/z/9GLbB_

Reviewed By: nikic

Differential Revision: https://reviews.llvm.org/D93842
The file was modifiedllvm/lib/Transforms/Scalar/EarlyCSE.cpp
The file was modifiedllvm/test/Transforms/EarlyCSE/and_or.ll
Commit eca40c36ef1c02877d957e12135faec12a5b3c26 by aqjune
[ValueTracking] Add unit tests for isKnownNonZero, isImpliedCondition (NFC)
The file was modifiedllvm/unittests/Analysis/ValueTrackingTest.cpp
Commit 4ad41902e8c7481ccf3cdf6e618dfcd1e1fc10fc by flo
[GVN] Correctly set modified status when doing PRE on indices.

This patch updates GVN to correctly return the modified status, if PRE
is performed on indices. It fixes a crash when building the test-suite
with EXPENSIVE_CHECKS and LTO.
The file was modifiedllvm/test/Transforms/GVN/PRE/pre-gep-load.ll
The file was addedllvm/test/Transforms/GVN/PRE/modified-status.ll
The file was modifiedllvm/lib/Transforms/Scalar/GVN.cpp
Commit 860199dfbe60d78a7da6406622b635a2d4435db3 by aqjune
[ValueTracking] Use m_LogicalAnd/Or to look into conditions

This patch updates isImpliedCondition/isKnownNonZero to look into select form of
and/or as well.

See llvm.org/pr48353 and D93065 for more context

Reviewed By: nikic

Differential Revision: https://reviews.llvm.org/D93845
The file was modifiedllvm/unittests/Analysis/ValueTrackingTest.cpp
The file was modifiedllvm/lib/Analysis/ValueTracking.cpp
Commit 9d70dbdc2bf294abffd4b2c9ae524055f72d017a by aqjune
[InstCombine] use poison as placeholder for undemanded elems

Currently undef is used as a don’t-care vector when constructing a vector using a series of insertelement.
However, this is problematic because undef isn’t undefined enough.
Especially, a sequence of insertelement can be optimized to shufflevector, but using undef as its placeholder makes shufflevector a poison-blocking instruction because undef cannot be optimized to poison.
This makes a few straightforward optimizations incorrect, such as:

```
;  https://bugs.llvm.org/show_bug.cgi?id=44185

define <4 x float> @insert_not_undef_shuffle_translate_commute(float %x, <4 x float> %y, <4 x float> %q) {
  %xv = insertelement <4 x float> %q, float %x, i32 2
  %r = shufflevector <4 x float> %y, <4 x float> %xv, <4 x i32> { 0, 6, 2, undef }
  ret <4 x float> %r ; %r[3] is undef
}
=>
define <4 x float> @insert_not_undef_shuffle_translate_commute(float %x, <4 x float> %y, <4 x float> %q) {
  %r = insertelement <4 x float> %y, float %x, i32 1
  ret <4 x float> %r ; %r[3] = %y[3], incorrect if %y[3] = poison
}

Transformation doesn't verify!
ERROR: Target is more poisonous than source
```

I’d like to suggest
1. Using poison as insertelement’s placeholder value (IRBuilder::CreateVectorSplat should be patched too)
2. Updating shufflevector’s semantics to return poison element if mask is undef

Note that poison is currently lowered into UNDEF in SelDag, so codegen part is okay.
m_Undef() matches PoisonValue as well, so existing optimizations will still fire.

The only concern is hidden miscompilations that will go incorrect when poison constant is given.
A conservative way is copying all tests having `insertelement undef` & replacing it with `insertelement poison` & run Alive2 on it, but it will create many tests and people won’t like it. :(

Instead, I’ll simply locally maintain the tests and run Alive2.
If there is any bug found, I’ll report it.

Relevant links: https://bugs.llvm.org/show_bug.cgi?id=43958 , http://lists.llvm.org/pipermail/llvm-dev/2019-November/137242.html

Reviewed By: nikic

Differential Revision: https://reviews.llvm.org/D93586
The file was modifiedllvm/test/Transforms/InstCombine/X86/x86-pshufb.ll
The file was modifiedllvm/test/Transforms/InstCombine/X86/x86-vec_demanded_elts.ll
The file was modifiedllvm/test/Transforms/InstCombine/bitcast.ll
The file was modifiedllvm/test/Transforms/PhaseOrdering/X86/horiz-math.ll
The file was modifiedllvm/test/Transforms/InstCombine/X86/clmulqdq.ll
The file was modifiedllvm/test/Transforms/InstCombine/bitcast-bigendian.ll
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
The file was modifiedllvm/test/Transforms/InstCombine/X86/x86-vec_demanded_elts-inseltpoison.ll
The file was modifiedllvm/test/Transforms/InstCombine/X86/x86-sse41-inseltpoison.ll
The file was modifiedllvm/test/Transforms/InstCombine/getelementptr.ll
The file was modifiedllvm/test/Transforms/InstCombine/X86/x86-sse4a.ll
The file was modifiedllvm/test/Transforms/LoopVectorize/induction.ll
The file was modifiedllvm/test/Transforms/InstCombine/bitcast-inseltpoison.ll
The file was modifiedllvm/test/Transforms/InstCombine/X86/x86-xop-inseltpoison.ll
The file was modifiedllvm/test/Transforms/InstCombine/vec_shuffle.ll
The file was modifiedllvm/test/Transforms/InstCombine/X86/x86-vector-shifts-inseltpoison.ll
The file was modifiedllvm/test/Transforms/LoopVectorize/X86/invariant-load-gather.ll
The file was modifiedllvm/test/Transforms/InstCombine/cast.ll
The file was modifiedllvm/test/Transforms/LoopVectorize/reduction-inloop-pred.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/alternate-int-inseltpoison.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/alternate-cast-inseltpoison.ll
The file was modifiedllvm/test/Transforms/InstCombine/ARM/tbl1.ll
The file was modifiedllvm/test/Transforms/InstCombine/X86/x86-sse41.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/AArch64/getelementptr.ll
The file was modifiedllvm/test/Transforms/InstCombine/vec_demanded_elts.ll
The file was modifiedllvm/test/Transforms/InstCombine/vector-casts-inseltpoison.ll
The file was modifiedllvm/test/Transforms/InstCombine/broadcast-inseltpoison.ll
The file was modifiedclang/test/CodeGen/SystemZ/builtins-systemz-zvector-constrained.c
The file was modifiedllvm/test/Transforms/InstCombine/insert-extract-shuffle.ll
The file was modifiedllvm/test/Transforms/InstCombine/pr2645-0.ll
The file was modifiedllvm/test/Transforms/InstCombine/X86/x86-addsub-inseltpoison.ll
The file was modifiedllvm/test/Transforms/InstCombine/insert-extract-shuffle-inseltpoison.ll
The file was modifiedllvm/test/Transforms/InstCombine/vector-casts.ll
The file was modifiedllvm/test/Transforms/InstCombine/shuffle_select.ll
The file was modifiedllvm/test/Transforms/InstCombine/sub-of-negatible.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/vector-alloca-bitcast.ll
The file was modifiedllvm/test/Transforms/InstCombine/bitcast-vec-canon-inseltpoison.ll
The file was modifiedllvm/test/Transforms/LoopVectorize/reduction-inloop.ll
The file was modifiedllvm/test/Transforms/InstCombine/vec_shuffle-inseltpoison.ll
The file was modifiedllvm/test/Transforms/InstCombine/X86/x86-avx512.ll
The file was modifiedclang/test/CodeGen/SystemZ/builtins-systemz-zvector2-constrained.c
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/alternate-cast.ll
The file was modifiedllvm/test/Transforms/InstCombine/X86/x86-muldq.ll
The file was modifiedllvm/test/Transforms/InstCombine/trunc.ll
The file was modifiedllvm/test/Transforms/InstCombine/AArch64/tbl1.ll
The file was modifiedllvm/test/Transforms/InstCombine/X86/x86-pack.ll
The file was modifiedllvm/test/Transforms/InstCombine/X86/x86-vpermil.ll
The file was modifiedllvm/test/Transforms/InstCombine/shufflevector-div-rem-inseltpoison.ll
The file was modifiedllvm/test/Transforms/InstCombine/X86/x86-vector-shifts.ll
The file was modifiedllvm/test/Transforms/InstCombine/masked_intrinsics.ll
The file was modifiedllvm/test/Transforms/PhaseOrdering/X86/horiz-math-inseltpoison.ll
The file was modifiedllvm/test/Transforms/InstCombine/X86/x86-addsub.ll
The file was modifiedllvm/test/Transforms/InstCombine/X86/x86-sse-inseltpoison.ll
The file was modifiedllvm/test/Transforms/InstCombine/vector_insertelt_shuffle.ll
The file was modifiedllvm/test/Transforms/InstCombine/insert-const-shuf.ll
The file was modifiedllvm/test/Transforms/InstCombine/minmax-fold.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/blending-shuffle-inseltpoison.ll
The file was modifiedllvm/test/Transforms/InstCombine/vector_insertelt_shuffle-inseltpoison.ll
The file was modifiedclang/test/CodeGen/SystemZ/builtins-systemz-zvector2.c
The file was modifiedllvm/test/Transforms/InstCombine/broadcast.ll
The file was modifiedllvm/test/Transforms/InstCombine/bitcast-vec-canon.ll
The file was modifiedllvm/test/Transforms/InstCombine/X86/x86-sse2.ll
The file was modifiedllvm/test/Transforms/InstCombine/X86/x86-avx512-inseltpoison.ll
The file was modifiedllvm/test/Transforms/InstCombine/vec_demanded_elts-inseltpoison.ll
The file was modifiedllvm/test/Transforms/InstCombine/X86/x86-masked-memops.ll
The file was modifiedllvm/test/Transforms/InstCombine/X86/x86-xop.ll
The file was modifiedllvm/test/Transforms/InstCombine/X86/x86-sse.ll
The file was modifiedllvm/test/Transforms/InstCombine/X86/x86-sse2-inseltpoison.ll
The file was modifiedllvm/test/Transforms/InstCombine/masked_intrinsics-inseltpoison.ll
The file was modifiedllvm/test/Transforms/InstCombine/X86/x86-pack-inseltpoison.ll
The file was modifiedllvm/test/Transforms/InstCombine/X86/x86-insertps.ll
The file was modifiedllvm/test/Transforms/InstCombine/shufflevector-div-rem.ll
The file was modifiedclang/test/CodeGen/SystemZ/builtins-systemz-zvector.c
Commit d76c1d2247af599a67fcfee6b1ebfcffed99ee7c by yrouban
[RS4GC] Lazily set changed flag when folding single entry phis

The function FoldSingleEntryPHINodes() is changed to return if
it has changed IR or not. This return value is used by RS4GC to
set the MadeChange flag respectively.

Reviewed By: reames
Differential Revision: https://reviews.llvm.org/D93810
The file was modifiedllvm/include/llvm/Transforms/Utils/BasicBlockUtils.h
The file was modifiedllvm/lib/Transforms/Scalar/RewriteStatepointsForGC.cpp
The file was modifiedllvm/lib/Transforms/Utils/BasicBlockUtils.cpp
Commit 31c2b93d83f63ce7f9bb4977f58de2e00bf18e0f by czhengsz
[MachineSink] add threshold in machinesink pass to reduce compiling time.
The file was modifiedllvm/lib/CodeGen/MachineSink.cpp
Commit fde3ae88ee4236d6ecb8178c6c893df5a5a04437 by i
[asan][memprof] Declare _DYNAMIC and fix -Wparentheses

Declare `extern ElfW(Dyn) _DYNAMIC[];` so that it will trivially work on musl.
The file was modifiedcompiler-rt/lib/asan/asan_linux.cpp
The file was modifiedcompiler-rt/lib/memprof/memprof_mapping.h
The file was modifiedcompiler-rt/lib/memprof/memprof_linux.cpp
Commit 0b56e3cdda501b19bbfee6ee3899f72d9bce121c by i
[sanitizer] Defined SANITIZER_TEST_HAS_PVALLOC only on glibc

This simplifies the condition and makes it work on musl.
The file was modifiedcompiler-rt/lib/sanitizer_common/tests/sanitizer_test_utils.h
Commit 99d650b3699eaf23adcff6b28ebbc7ec4b890b3b by i
[compiler-rt][test] Make glibc-* feature detection work on a musl distribution

... where `ldd --version` has empty stdout and non-empty stderr.
The file was modifiedcompiler-rt/test/lit.common.cfg.py
Commit 60afb58bfee6eed7b14d1a7c0594ae3688fb921a by i
[msan] Delete unused glibc header <execinfo.h>

The file does not call backtrace/backtrace_symbols.
The file was modifiedcompiler-rt/lib/msan/msan_linux.cpp
Commit d85a198e85253b6b39d9b86eb7afd3332637bcbe by fraser
[RISCV] Pattern-match more vector-splatted constants

This patch extends the pattern-matching capability of vector-splatted
constants. When illegally-typed constants are legalized they are
canonically sign-extended to XLenVT. This preserves the sign and allows
us to match simm5. If they were zero-extended for whatever reason we'd
lose that ability: e.g. `(i8 -1) -> (XLenVT 255)` would not be matched
under the current logic.

To address this we first manually sign-extend the splatted constant from
the vector element type to int64_t. This preserves the semantics while
removing any implicitly-truncated bits.

The corresponding logic for uimm5 was not updated, the rationale being
that neither sign- nor zero-extending a legal uimm5 immediate should
change that (unless we expect actual "garbage" upper bits).

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D93837
The file was modifiedllvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
Commit a485a59d2172daaee1d5e734da54fbb243f7d54c by lebedev.ri
[benchmark] Fixed a build error when using CMake 3.15.1 + NDK-R20

std::decay_t used by llvm/utils/benchmark/include/benchmark/benchmark.h
is a c++14 feature, but the CMakelist uses c++11,
it's the root-cause of build error.

There are two options to fix the error.
1) change the CMakelist to support c++14.
2) change std::decay_t to std::decay, it's what the patch done.

This bug can only be reproduced by CMake 3.15, we didn't observer the bug
with CMake 3.16. But based on the code's logic, it's an obvious bug of LLVM.

The upstream code is fine, the problem was introduced by
rG1bd6123b781120c9190b9ba58b900cdcb718cdd1.

Reviewed By: lebedev.ri

Differential Revision: https://reviews.llvm.org/D93794
The file was modifiedllvm/utils/benchmark/include/benchmark/benchmark.h
Commit 5b17263b6b9d25d02581c2e44efa0c4dcad5ecf4 by dmitry.preobrazhensky
[AMDGPU][MC][NFC] Parser refactoring

See bug 48515 (https://bugs.llvm.org/show_bug.cgi?id=48515)

Reviewers: rampitec

Differential Revision: https://reviews.llvm.org/D93756
The file was modifiedllvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
Commit 8c25bb3d0d5e956a3dc3a8d26b2e7ab509d0b72c by dmitry.preobrazhensky
[AMDGPU][MC] Improved errors handling for v_interp* operands

See bug 48596 (https://bugs.llvm.org/show_bug.cgi?id=48596)

Reviewers: rampitec

Differential Revision: https://reviews.llvm.org/D93757
The file was modifiedllvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
The file was modifiedllvm/test/MC/AMDGPU/vintrp-err.s
The file was modifiedllvm/test/MC/AMDGPU/gfx10_err_pos.s
Commit e673d40199477f48b78ed9ad790ce7356474f907 by zakk.chen
[RISCV] Define vmsbf.m/vmsif.m/vmsof.m/viota.m/vid.v intrinsics.

Define those intrinsics and lower to V instructions.

Use update_llc_test_checks.py for viota.m tests to check
earlyclobber is applied correctly.
mask viota.m tests uses the same argument as input and mask for
avoid dependency of D93364.

We work with @rogfer01 from BSC to come out this patch.

Reviewed By: HsiangKai

Differential Revision: https://reviews.llvm.org/D93823
The file was addedllvm/test/CodeGen/RISCV/rvv/vmsif-rv64.ll
The file was addedllvm/test/CodeGen/RISCV/rvv/vmsbf-rv64.ll
The file was modifiedllvm/include/llvm/IR/IntrinsicsRISCV.td
The file was addedllvm/test/CodeGen/RISCV/rvv/vmsof-rv32.ll
The file was addedllvm/test/CodeGen/RISCV/rvv/vid-rv32.ll
The file was addedllvm/test/CodeGen/RISCV/rvv/vmsbf-rv32.ll
The file was addedllvm/test/CodeGen/RISCV/rvv/viota-rv32.ll
The file was addedllvm/test/CodeGen/RISCV/rvv/vmsof-rv64.ll
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
The file was addedllvm/test/CodeGen/RISCV/rvv/vid-rv64.ll
The file was addedllvm/test/CodeGen/RISCV/rvv/vmsif-rv32.ll
The file was addedllvm/test/CodeGen/RISCV/rvv/viota-rv64.ll
Commit 644da789e364b338227a13b5cc11dd03c8ae5ba8 by Alexander Timofeev
[AMDGPU] Split edge to make si_if dominate end_cf

Basic block containing "if" not necessarily dominates block that is the "false" target for the if.

That "false" target block may have another predecessor besides the "if" block. IR value corresponding to the Exec mask is generated by the

si_if intrinsic and then used by the end_cf intrinsic. In this case IR verifier complains that 'Def does not dominate all uses'.

This change split the edge between the "if" block and "false" target block to make it dominated by the "if" block.

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D91435
The file was addedllvm/test/CodeGen/AMDGPU/unstructured-cfg-def-use-issue.ll
The file was modifiedllvm/lib/Target/AMDGPU/SIAnnotateControlFlow.cpp
Commit 0999408aea79dd69f182cfcb618006f6cf2b6d4e by adamcz
[clangd] Add error handling (elog) in code completion.

Differential Revision: https://reviews.llvm.org/D93220
The file was modifiedclang-tools-extra/clangd/CodeComplete.cpp
Commit c3b9d85bd4b7249af9efe3594c6c152a032f83f8 by n.james93
[clang-tidy][NFC] Remove unnecessary headers
The file was modifiedclang-tools-extra/clang-tidy/ClangTidy.cpp
The file was modifiedclang-tools-extra/clang-tidy/ClangTidyDiagnosticConsumer.cpp
The file was modifiedclang-tools-extra/clang-tidy/ClangTidyOptions.cpp
The file was modifiedclang-tools-extra/clang-tidy/ClangTidyCheck.cpp
The file was modifiedclang-tools-extra/clang-tidy/ClangTidyModule.h
The file was modifiedclang-tools-extra/clang-tidy/ClangTidyProfiling.cpp
Commit e73f885c988d7b94fcad64ddfa6a825e15e77a8f by nemanja.i.ibm
[PowerPC] Remove redundant COPY_TO_REGCLASS introduced by 8a58f21f5b6c
The file was modifiedllvm/lib/Target/PowerPC/PPCInstrPrefix.td
Commit 496fb70b141ccbfaba9761294f3b4b97717096a3 by mikael.holmen
[MachO] Fix enum-int mismatch warning

Change-Id: Ie637dc7761144e5552b05a9c286f1e736579823d

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D91520
The file was modifiedlld/lib/ReaderWriter/MachO/MachONormalizedFileFromAtoms.cpp
Commit d55627d221be8154cbdf454fa727afcc3f716b08 by tkeith
[flang] Fix bugs in .mod file for abstract interface

When an abstract interface is defined, add the ABSTRACT attribute to
subprogram symbols that define the interface body. Make use of that
when writing .mod files to include "abstract" on the interface statement.

Also, fix a problem with the order of symbols in a .mod file. Sometimes
a name is mentioned before the "real" declaration, e.g. in an access
statement. We want the order to be based on the real definitions. In
these cases we replace the symbol name with an identical name with a
different source location. Then by sorting based on the source location
we get symbols in the right order.

Differential Revision: https://reviews.llvm.org/D93572
The file was modifiedflang/test/Semantics/modfile10.f90
The file was modifiedflang/lib/Semantics/mod-file.cpp
The file was modifiedflang/test/Semantics/procinterface01.f90
The file was modifiedflang/lib/Semantics/resolve-names.cpp
The file was modifiedflang/test/Semantics/symbol15.f90
Commit b9a7c89d4322b261b65eb96d678a9d38b776cb60 by mikael.holmen
[MIRPrinter] Fix incorrect output of unnamed stack names

The MIRParser expects unnamed stack entries to have empty names ('').
In case of unnamed alloca instructions, the MIRPrinter would output
'<unnamed alloca>', which caused the MIRParser to reject the generated
code.

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D93685
The file was modifiedllvm/test/CodeGen/PowerPC/alloca-crspill.ll
The file was modifiedllvm/lib/CodeGen/MIRPrinter.cpp
The file was addedllvm/test/CodeGen/MIR/AArch64/unnamed-stack.ll
Commit d4ccef38d0bbcd70f56d586b4dfc988db863e388 by lebedev.ri
[InstCombine] 'hoist xor-by-constant from xor-by-value': ignore constantexprs

As it is being reported (in post-commit review) in
https://reviews.llvm.org/D93857
this fold (as i expected, but failed to come up with test coverage
despite trying) has issues with constant expressions.
Since we only care about true constants, which constantexprs are not,
don't perform such hoisting for constant expressions.
The file was modifiedllvm/test/Transforms/InstCombine/hoist-xor-by-constant-from-xor-by-value.ll
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
Commit 4820af99ddc3271198ecccce4fdd867dc65b11f5 by Paul C. Anagnostopoulos
[TableGen] Fix bug in !interleave operator

I forgot to account for unresolved elements of the list.

Differential Revision: https://reviews.llvm.org/D93814
The file was modifiedllvm/lib/TableGen/Record.cpp
The file was modifiedllvm/test/TableGen/interleave.td
Commit 38bfa25387f4d1292c12a574df6b3cd0f3c212d6 by lebedev.ri
Revert "[benchmark] Fixed a build error when using CMake 3.15.1 + NDK-R20"

Temporairly revert until a consensus on post-commit comments is achieved.

This reverts commit a485a59d2172daaee1d5e734da54fbb243f7d54c.
The file was modifiedllvm/utils/benchmark/include/benchmark/benchmark.h
Commit c7ff2c0da1a66d8bae52751c2af4135e67bf3519 by dmitry.preobrazhensky
[AMDGPU][MC][NFC] Split large asm tests into smaller chunks

The following large tests have been split into smaller parts by instruction formats:

    gfx7_asm_all.s
    gfx8_asm_all.s
    gfx9_asm_all.s
    gfx10_asm_all.s

This change results in noticeable lit testing speedup.
For example, on a debug Windows build, split asm tests are run 3.5 times faster.
The file was addedllvm/test/MC/AMDGPU/gfx9_asm_vop3_e64.s
The file was addedllvm/test/MC/AMDGPU/gfx9_asm_vop3p.s
The file was addedllvm/test/MC/AMDGPU/gfx8_asm_sop1.s
The file was addedllvm/test/MC/AMDGPU/gfx10_asm_sop.s
The file was addedllvm/test/MC/AMDGPU/gfx8_asm_vintrp.s
The file was addedllvm/test/MC/AMDGPU/gfx9_asm_vopc.s
The file was addedllvm/test/MC/AMDGPU/gfx7_asm_sop1.s
The file was addedllvm/test/MC/AMDGPU/gfx7_asm_vop1.s
The file was addedllvm/test/MC/AMDGPU/gfx9_asm_mtbuf.s
The file was addedllvm/test/MC/AMDGPU/gfx9_asm_vintrp.s
The file was addedllvm/test/MC/AMDGPU/gfx9_asm_sopk.s
The file was addedllvm/test/MC/AMDGPU/gfx9_asm_exp.s
The file was addedllvm/test/MC/AMDGPU/gfx10_asm_vopc.s
The file was addedllvm/test/MC/AMDGPU/gfx8_asm_exp.s
The file was addedllvm/test/MC/AMDGPU/gfx10_asm_flat.s
The file was addedllvm/test/MC/AMDGPU/gfx8_asm_smem.s
The file was addedllvm/test/MC/AMDGPU/gfx7_asm_ds.s
The file was addedllvm/test/MC/AMDGPU/gfx10_asm_vop3.s
The file was addedllvm/test/MC/AMDGPU/gfx7_asm_flat.s
The file was addedllvm/test/MC/AMDGPU/gfx8_asm_vop3.s
The file was addedllvm/test/MC/AMDGPU/gfx9_asm_flat.s
The file was addedllvm/test/MC/AMDGPU/gfx10_asm_mubuf.s
The file was addedllvm/test/MC/AMDGPU/gfx7_asm_vintrp.s
The file was addedllvm/test/MC/AMDGPU/gfx8_asm_sop2.s
The file was addedllvm/test/MC/AMDGPU/gfx9_asm_mimg.s
The file was addedllvm/test/MC/AMDGPU/gfx9_asm_smem.s
The file was addedllvm/test/MC/AMDGPU/gfx8_asm_mubuf.s
The file was addedllvm/test/MC/AMDGPU/gfx7_asm_vopc.s
The file was addedllvm/test/MC/AMDGPU/gfx8_asm_ds.s
The file was addedllvm/test/MC/AMDGPU/gfx9_asm_sopp.s
The file was addedllvm/test/MC/AMDGPU/gfx7_asm_mtbuf.s
The file was addedllvm/test/MC/AMDGPU/gfx7_asm_vop3_e64.s
The file was addedllvm/test/MC/AMDGPU/gfx8_asm_vop2.s
The file was addedllvm/test/MC/AMDGPU/gfx9_asm_sop1.s
The file was removedllvm/test/MC/AMDGPU/gfx10_asm_all.s
The file was addedllvm/test/MC/AMDGPU/gfx7_asm_sop2.s
The file was addedllvm/test/MC/AMDGPU/gfx7_asm_sopk.s
The file was addedllvm/test/MC/AMDGPU/gfx7_asm_vop2.s
The file was addedllvm/test/MC/AMDGPU/gfx9_asm_sopc.s
The file was addedllvm/test/MC/AMDGPU/gfx7_asm_exp.s
The file was addedllvm/test/MC/AMDGPU/gfx10_asm_vop1.s
The file was addedllvm/test/MC/AMDGPU/gfx8_asm_vop3_e64.s
The file was addedllvm/test/MC/AMDGPU/gfx10_asm_ds.s
The file was addedllvm/test/MC/AMDGPU/gfx8_asm_mtbuf.s
The file was addedllvm/test/MC/AMDGPU/gfx10_asm_vopc_sdwa.s
The file was addedllvm/test/MC/AMDGPU/gfx8_asm_mimg.s
The file was addedllvm/test/MC/AMDGPU/gfx9_asm_vop3.s
The file was addedllvm/test/MC/AMDGPU/gfx7_asm_mubuf.s
The file was addedllvm/test/MC/AMDGPU/gfx9_asm_mubuf.s
The file was addedllvm/test/MC/AMDGPU/gfx8_asm_sopk.s
The file was addedllvm/test/MC/AMDGPU/gfx10_asm_vopcx.s
The file was removedllvm/test/MC/AMDGPU/gfx9_asm_all.s
The file was addedllvm/test/MC/AMDGPU/gfx9_asm_vop2.s
The file was addedllvm/test/MC/AMDGPU/gfx8_asm_vopc.s
The file was addedllvm/test/MC/AMDGPU/gfx10_asm_vop2.s
The file was addedllvm/test/MC/AMDGPU/gfx8_asm_sopp.s
The file was addedllvm/test/MC/AMDGPU/gfx9_asm_ds.s
The file was addedllvm/test/MC/AMDGPU/gfx8_asm_vop1.s
The file was addedllvm/test/MC/AMDGPU/gfx9_asm_vop1.s
The file was addedllvm/test/MC/AMDGPU/gfx7_asm_mimg.s
The file was addedllvm/test/MC/AMDGPU/gfx7_asm_sopp.s
The file was addedllvm/test/MC/AMDGPU/gfx7_asm_vop3.s
The file was addedllvm/test/MC/AMDGPU/gfx7_asm_sopc.s
The file was addedllvm/test/MC/AMDGPU/gfx8_asm_flat.s
The file was addedllvm/test/MC/AMDGPU/gfx8_asm_sopc.s
The file was addedllvm/test/MC/AMDGPU/gfx10_asm_smem.s
The file was addedllvm/test/MC/AMDGPU/gfx9_asm_sop2.s
The file was addedllvm/test/MC/AMDGPU/gfx10_asm_vopc_e64.s
The file was removedllvm/test/MC/AMDGPU/gfx8_asm_all.s
The file was removedllvm/test/MC/AMDGPU/gfx7_asm_all.s
The file was addedllvm/test/MC/AMDGPU/gfx7_asm_smrd.s
Commit dcd21572f971ae5b5f1bf1f1abefafa0085404e1 by nikita.ppv
[ValueTracking] Fix isKnownNonEqual() with constexpr mul

Confusingly, BinaryOperator is not an Operator,
OverflowingBinaryOperator is... We were implicitly assuming that
the multiply is an Instruction here.

This fixes the assertion failure reported in
https://reviews.llvm.org/D92726#2472827.
The file was modifiedllvm/lib/Analysis/ValueTracking.cpp
The file was modifiedllvm/test/Analysis/ValueTracking/known-non-equal.ll
Commit e4df6a40dad66e989a4333c11d39cf3ed9635135 by listmail
[LV] Vectorize (some) early and multiple exit loops

This patch is a major step towards supporting multiple exit loops in the vectorizer. This patch on it's own extends the loop forms allowed in two ways:

    single exit loops which are not bottom tested
    multiple exit loops w/ a single exit block reached from all exits and no phis in the exit block (because of LCSSA this implies no values defined in the loop used later)

The restrictions on multiple exit loop structures will be removed in follow up patches; disallowing cases for now makes the code changes smaller and more obvious. As before, we can only handle loops with entirely analyzable exits. Removing that restriction is much harder, and is not part of currently planned efforts.

The basic idea here is that we can force the last iteration to run in the scalar epilogue loop (if we have one). From the definition of SCEV's backedge taken count, we know that no earlier iteration can exit the vector body. As such, we can leave the decision on which exit to be taken to the scalar code and generate a bottom tested vector loop which runs all but the last iteration.

The existing code already had the notion of requiring one iteration in the scalar epilogue, this patch is mainly about generalizing that support slightly, making sure we don't try to use this mechanism when tail folding, and updating the code to reflect the difference between a single exit block and a unique exit block (very mechanical).

Differential Revision: https://reviews.llvm.org/D93317
The file was modifiedllvm/lib/Transforms/Vectorize/LoopVectorize.cpp
The file was modifiedllvm/lib/Transforms/Vectorize/LoopVectorizationLegality.cpp
The file was modifiedllvm/test/Transforms/LoopVectorize/control-flow.ll
The file was modifiedllvm/test/Transforms/LoopVectorize/loop-form.ll
The file was modifiedllvm/test/Transforms/LoopVectorize/loop-legality-checks.ll
Commit 4ffcd4fe9ac2ee948948f732baa16663eb63f1c7 by aeubanks
Revert "[LV] Vectorize (some) early and multiple exit loops"

This reverts commit e4df6a40dad66e989a4333c11d39cf3ed9635135.

Breaks Windows bots, e.g. http://45.33.8.238/win/30472/step_4.txt
and http://lab.llvm.org:8011/#/builders/83/builds/2078/steps/5/logs/stdio
The file was modifiedllvm/lib/Transforms/Vectorize/LoopVectorize.cpp
The file was modifiedllvm/test/Transforms/LoopVectorize/control-flow.ll
The file was modifiedllvm/test/Transforms/LoopVectorize/loop-form.ll
The file was modifiedllvm/test/Transforms/LoopVectorize/loop-legality-checks.ll
The file was modifiedllvm/lib/Transforms/Vectorize/LoopVectorizationLegality.cpp
Commit 4b33b2387787aef5020450cdcc8dde231eb0a5fc by listmail
Reapply "[LV] Vectorize (some) early and multiple exit loops"" w/fix for builder

This reverts commit 4ffcd4fe9ac2ee948948f732baa16663eb63f1c7 thus restoring e4df6a40dad.

The only change from the original patch is to add "llvm::" before the call to empty(iterator_range).  This is a speculative fix for the ambiguity reported on some builders.
The file was modifiedllvm/test/Transforms/LoopVectorize/control-flow.ll
The file was modifiedllvm/test/Transforms/LoopVectorize/loop-legality-checks.ll
The file was modifiedllvm/test/Transforms/LoopVectorize/loop-form.ll
The file was modifiedllvm/lib/Transforms/Vectorize/LoopVectorizationLegality.cpp
The file was modifiedllvm/lib/Transforms/Vectorize/LoopVectorize.cpp
Commit 30f589c912115b4653f596eb3fd5bf62412f8aa7 by arthur.j.odwyer
[libc++] Constexpr-proof some machinery in not_fn.pass.cpp. NFCI.

We don't need to use global variables here; we can store the "State"
of this machinery on the stack, so that it's constexpr-friendly.
The file was modifiedlibcxx/test/std/utilities/function.objects/func.not_fn/not_fn.pass.cpp
Commit 7b00e9fae3853d4693e608cc52f6d6da5059f5ff by arthur.j.odwyer
[libc++] [P1065] Constexpr invoke, reference_wrapper, mem_fn, not_fn, default_searcher.

This completes the implementation of P1065 "constexpr INVOKE":
http://www.open-std.org/jtc1/sc22/wg21/docs/papers/2019/p1065r2.html

This doesn't yet complete the implementation of P1032 "Misc constexpr bits,"
http://www.open-std.org/jtc1/sc22/wg21/docs/papers/2018/p1032r1.html
but it does complete all of the <functional> bits, which means
that we can now set `__cpp_lib_constexpr_functional` for C++20.

This could use more constexpr tests for `std::reference_wrapper<T>`,
but the existing tests are extremely non-constexpr-friendly and
so I don't want to get into that rabbit-hole today.

Differential Revision: https://reviews.llvm.org/D93815
The file was modifiedlibcxx/docs/FeatureTestMacroTable.rst
The file was modifiedlibcxx/test/std/utilities/function.objects/func.memfn/member_function_const.pass.cpp
The file was modifiedlibcxx/include/functional
The file was modifiedlibcxx/test/std/language.support/support.limits/support.limits.general/version.version.pass.cpp
The file was addedlibcxx/test/std/utilities/function.objects/func.invoke/invoke_constexpr.pass.cpp
The file was modifiedlibcxx/test/std/language.support/support.limits/support.limits.general/iterator.version.pass.cpp
The file was modifiedlibcxx/test/std/language.support/support.limits/support.limits.general/array.version.pass.cpp
The file was modifiedlibcxx/test/std/utilities/function.objects/func.not_fn/not_fn.pass.cpp
The file was modifiedlibcxx/test/std/language.support/support.limits/support.limits.general/tuple.version.pass.cpp
The file was modifiedlibcxx/test/std/utilities/function.objects/func.search/func.search.default/default.pred.pass.cpp
The file was modifiedlibcxx/test/std/utilities/function.objects/func.memfn/member_data.pass.cpp
The file was modifiedlibcxx/test/std/utilities/function.objects/func.search/func.search.default/default.pass.cpp
The file was modifiedlibcxx/include/version
The file was modifiedlibcxx/test/std/language.support/support.limits/support.limits.general/utility.version.pass.cpp
The file was modifiedlibcxx/test/std/utilities/function.objects/func.memfn/member_function.pass.cpp
The file was modifiedlibcxx/test/std/language.support/support.limits/support.limits.general/string_view.version.pass.cpp
The file was modifiedlibcxx/docs/Cxx2aStatusPaperStatus.csv
The file was modifiedlibcxx/include/type_traits
The file was modifiedlibcxx/utils/generate_feature_test_macro_components.py
The file was modifiedlibcxx/test/std/language.support/support.limits/support.limits.general/functional.version.pass.cpp
The file was modifiedlibcxx/include/__functional_base
Commit 9abc457724bd54014328a6f0b7ed230bacd9f610 by aeubanks
[NewPM][AMDGPU] Port amdgpu-simplifylib/amdgpu-usenative

And add them to the pipeline via
AMDGPUTargetMachine::registerPassBuilderCallbacks(), which mirrors
AMDGPUTargetMachine::adjustPassManager().

These passes can't be unconditionally added to PassRegistry.def since
they are only present when the AMDGPU backend is enabled. And there are
no target-specific headers in llvm/include, so parsing these pass names
must occur somewhere in the AMDGPU directory. I decided the best place
was inside the TargetMachine, since the PassBuilder invokes
TargetMachine::registerPassBuilderCallbacks() anyway. If we come up with
a cleaner solution for target-specific passes in the future that's fine,
but there aren't too many target-specific IR passes living in
target-specific directories so it shouldn't be too bad to change in the
future.

Reviewed By: ychen, arsenm

Differential Revision: https://reviews.llvm.org/D93863
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h
The file was modifiedllvm/test/CodeGen/AMDGPU/simplify-libcalls2.ll
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPULibCalls.cpp
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPU.h
The file was modifiedllvm/test/CodeGen/AMDGPU/simplify-libcalls.ll
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
The file was modifiedllvm/utils/gn/secondary/llvm/lib/Target/AMDGPU/BUILD.gn
The file was modifiedllvm/lib/Target/AMDGPU/CMakeLists.txt
Commit dd756e3e84812bd962a5b5eaf4f10e9c9338c232 by arthur.j.odwyer
[libc++] Fix a test failure in 7b00e9fae3 (D93815).

"LLVM Buildbot on libcxx-libcxxabi-x86_64-linux-debian" is not happy
with default-initializing the `double` member of `A` in a constexpr
function. At least I'm pretty sure that's what it's complaining about.
The file was modifiedlibcxx/test/std/utilities/function.objects/func.memfn/member_data.pass.cpp
Commit 76a718ee939ed84d95b005f36cfbd103a702522f by pavel
[lldb] Deduplicate some lldb-server tests

Merge llgs and debugserver flavours
The file was modifiedlldb/test/API/tools/lldb-server/TestGdbRemoteAttach.py
The file was modifiedlldb/test/API/tools/lldb-server/commandline/TestGdbRemoteConnection.py
The file was modifiedlldb/test/API/tools/lldb-server/signal-filtering/TestGdbRemote_QPassSignals.py
The file was modifiedlldb/test/API/tools/lldb-server/TestGdbRemote_qThreadStopInfo.py
The file was modifiedlldb/test/API/tools/lldb-server/TestGdbRemoteExpeditedRegisters.py
The file was modifiedlldb/test/API/tools/lldb-server/TestGdbRemoteCompletion.py
The file was modifiedlldb/test/API/tools/lldb-server/TestGdbRemoteHostInfo.py
Commit cf8f682c2dd478d76e729f5d998e56b9acef8aa4 by fraser
[RISCV] Adjust tested vor ops for more stable tests. NFC.
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vor-sdnode-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vor-sdnode-rv32.ll
Commit 34405b41d61580ff893057784b1b19f81f66bad3 by Akira
[CodeGen][ObjC] Destroy callee-destroyed arguments in the caller
function when the receiver is nil

Callee-destroyed arguments to a method have to be destroyed in the
caller function when the receiver is nil as the method doesn't get
executed. This fixes PR48207.

rdar://71808391

Differential Revision: https://reviews.llvm.org/D93273
The file was modifiedclang/test/CodeGenObjCXX/objc-struct-cxx-abi.mm
The file was modifiedclang/test/CodeGenObjC/strong-in-c-struct.m
The file was modifiedclang/test/CodeGenObjC/weak-in-c-struct.m
The file was addedclang/test/CodeGenObjC/objc-dispatch-null-check.m
The file was modifiedclang/include/clang/AST/Decl.h
The file was modifiedclang/lib/CodeGen/CGObjCMac.cpp
The file was modifiedclang/lib/AST/Decl.cpp
Commit 6d02d12e172ac85d750e1abe48a0c24559c63158 by dmitry.preobrazhensky
[AMDGPU][MC][NFC] Added more tests for flat_global

Restored tests from 7898803c638497ad32e2d4a189d5597d4eb4506e
The file was modifiedllvm/test/MC/AMDGPU/flat-global.s
Commit f931290308abd0eebecae385cd32ca3a25ddd9be by i
[PowerPC] Parse and ignore .machine

glibc/sysdeps/powerpc/powerpc64 has .machine
{altivec,power4,power5,power6,power7,power8} (.machine power9 is planned in
sysdeps/powerpc/powerpc64/power9/strcmp.S).
The diagnostic is not useful anyway so just delete it.
The file was modifiedllvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
The file was modifiedllvm/test/MC/PowerPC/ppc-machine.s
Commit ef93f7a11c347534ac768ec8bbbed64cd20c41d2 by lebedev.ri
[SimplifyCFG] FoldBranchToCommonDest: gracefully handle unreachable code ()

We might be dealing with an unreachable code,
so the bonus instruction we clone might be self-referencing.

There is a sanity check that all uses of bonus instructions
that are not in the original block with said bonus instructions
are PHI nodes, and that is obviously not the case
for self-referencing instructions..

So if we find such an use, just rewrite it.

Thanks to Mikael Holmén for the reproducer!

Fixes https://bugs.llvm.org/show_bug.cgi?id=48450#c8
The file was modifiedllvm/test/Transforms/SimplifyCFG/fold-branch-to-common-dest.ll
The file was modifiedllvm/lib/Transforms/Utils/SimplifyCFG.cpp
Commit 87c032f7b449cee97751d86739e249738029bf63 by clattner
[IR] Make Value::getType() work better with invalid IR.

The asmprinter would crash when dumping IR objects that had their
operands dropped.  With this change, we now get this output, which
makes op->dump() style debugging more useful.

%5 = "firrtl.eq"(<<NULL>>, <<NULL>>) : (<<NULL TYPE>>, <<NULL TYPE>>) -> !firrtl.uint<1>

Previously the asmprinter would crash getting the types of the null operands.

Differential Revision: https://reviews.llvm.org/D93869
The file was modifiedmlir/lib/IR/Value.cpp
Commit 1351f719d49642f7f1254d13e90d8d3a2824dcde by spatel
[InstSimplify] add tests for ctpop; NFC (PR48608)
The file was modifiedllvm/test/Transforms/InstSimplify/call.ll
Commit 236c4524a7cd3051a150690b4f4f55f496e7e248 by spatel
[InstSimplify] remove ctpop of 1 (low) bit

https://llvm.org/PR48608

As noted in the test comment, we could handle a more general
case in instcombine and remove this, but I don't have evidence
that we need to do that.

https://alive2.llvm.org/ce/z/MRW9gD
The file was modifiedllvm/lib/Analysis/InstructionSimplify.cpp
The file was modifiedllvm/test/Transforms/InstCombine/ctpop.ll
The file was modifiedllvm/test/Transforms/InstSimplify/call.ll
Commit b4655a0815d0cd75297cfe323526397ee7a03dca by Vitaly Buka
[NFC][sanitizer] Remove unused typedef
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_stacktrace.h
Commit 4a16c507cb68e425226e81598d91963aacdd57ed by nikita.ppv
[InstCombine] Disable unsafe select transform behind a flag

This disables the poison-unsafe select -> and/or transform behind
a flag (we continue to perform the fold by default). This is intended
to simplify evaluation and testing while we teach various passes
to directly recognize the select pattern.

This only disables the main select -> and/or transform. A number of
related ones are instead changed to canonicalize to the a ? b : false
and a ? true : b forms which represent and/or respectively. This
requires a bit of care to avoid infinite loops, as we do not want
!a ? b : false to be converted into a ? false : b.

The basic idea here is the same as D93065, but keeps the change
behind a flag for now.

Differential Revision: https://reviews.llvm.org/D93840
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
The file was modifiedllvm/include/llvm/Transforms/InstCombine/InstCombiner.h
The file was addedllvm/test/Transforms/InstCombine/select-and-or.ll
Commit 0f2c180163a2cc3d6239a32d379ec3d773e56a2f by aqjune
[ValueTracking] Implement impliesPoison

This PR adds impliesPoison(ValAssumedPoison, V) that returns true if V is
poison under the assumption that ValAssumedPoison is poison.

For example, impliesPoison('icmp X, 10', 'icmp X, Y') return true because
'icmp X, Y' is poison if 'icmp X, 10' is poison.

impliesPoison can be used for sound optimization of select, as discussed in
D77868.

Reviewed By: nikic

Differential Revision: https://reviews.llvm.org/D78152
The file was modifiedllvm/lib/Analysis/ValueTracking.cpp
The file was modifiedllvm/unittests/Analysis/ValueTrackingTest.cpp
The file was modifiedllvm/include/llvm/Analysis/ValueTracking.h
Commit 44ee14f993ff093c3c3ef65ab5aa1fdd3f7a1dc6 by tlively
[WebAssembly][NFC] Finish cleaning up SIMD tablegen

This commit is a follow-on to c2c2e9119e73, using the `Vec` records introduced
in that commit in the rest of the SIMD instruction definitions. Also removes
unnecessary types in output patterns.

Differential Revision: https://reviews.llvm.org/D93771
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
Commit 6c36286a2e180443005d31a9cec2ca182963bcad by aeubanks
[NewPM] Fix CGSCCOptimizerLateEPCallbacks place in pipeline

CGSCCOptimizerLateEPCallbacks are supposed to be run before the function
simplification pipeline, like in the legacy PM and as specified in the
comments for registerCGSCCOptimizerLateEPCallback().

Reviewed By: ychen

Differential Revision: https://reviews.llvm.org/D93871
The file was modifiedllvm/test/Other/new-pm-defaults.ll
The file was modifiedllvm/lib/Passes/PassBuilder.cpp
Commit 5e09e9979bc60f0fca0e80e7f72f1260bd1bbca5 by tlively
[WebAssembly] Prototype extending pairwise add instructions

As proposed in https://github.com/WebAssembly/simd/pull/380. This commit makes
the new instructions available only via clang builtins and LLVM intrinsics to
make their use opt-in while they are still being evaluated for inclusion in the
SIMD proposal.

Depends on D93771.

Differential Revision: https://reviews.llvm.org/D93775
The file was modifiedclang/include/clang/Basic/BuiltinsWebAssembly.def
The file was modifiedllvm/test/CodeGen/WebAssembly/simd-intrinsics.ll
The file was modifiedclang/lib/CodeGen/CGBuiltin.cpp
The file was modifiedllvm/test/MC/WebAssembly/simd-encodings.s
The file was modifiedclang/test/CodeGen/builtins-wasm.c
The file was modifiedllvm/include/llvm/IR/IntrinsicsWebAssembly.td
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
Commit 25007b4d7e094c569d512770bd2397d8667fd3db by jurahul
[MLIR][NFC] Change FunctionLike::setAllArgAttrs/setAllResultAttrs to do a one-shot attribute update.

- Change FunctionLike::setAllArgAttrs() and setAllResultAttrs() to rebuild the new list of
  function attributes locally and call setAttr() just once instead of calling
  setArgAttr()/setResultAttrs() for each argument which incrementally build the
  attribute dictionary and can end up creating a lot of unused DictionaryAttr's (which are
  uniqued and nor garbage collected).

Differential Revision: https://reviews.llvm.org/D93870
The file was modifiedmlir/include/mlir/IR/FunctionSupport.h
Commit e6ae623314bab3ddd983ed941bf63a6d4c63a1f4 by andrew.litteken
[IROutliner] Adding support for consolidating functions with different output arguments.

Certain regions can have values introduced inside the region that are
used outside of the region. These may not be the same for each similar
region, so we must create one over arching set of arguments for the
consolidated function.

We do this by iterating over the outputs for each extracted function,
and creating as many different arguments to encapsulate the different
outputs sets. For each output set, we create a different block with the
necessary stores from the value to the output register. There is then
one switch statement, controlled by an argument to the function, to
differentiate which block to use.

Changed Tests for consistency:
llvm/test/Transforms/IROutliner/extraction.ll
llvm/test/Transforms/IROutliner/illegal-assumes.ll
llvm/test/Transforms/IROutliner/illegal-memcpy.ll
llvm/test/Transforms/IROutliner/illegal-memmove.ll
llvm/test/Transforms/IROutliner/illegal-vaarg.ll

Tests to test new functionality:
llvm/test/Transforms/IROutliner/outlining-different-output-blocks.ll
llvm/test/Transforms/IROutliner/outlining-remapped-outputs.ll
llvm/test/Transforms/IROutliner/outlining-same-output-blocks.ll

Reviewers: jroelofs, paquette

Differential Revision: https://reviews.llvm.org/D87296
The file was modifiedllvm/test/Transforms/IROutliner/extraction.ll
The file was modifiedllvm/test/Transforms/IROutliner/illegal-memmove.ll
The file was modifiedllvm/lib/Transforms/IPO/IROutliner.cpp
The file was addedllvm/test/Transforms/IROutliner/outlining-remapped-outputs.ll
The file was modifiedllvm/test/Transforms/IROutliner/illegal-memcpy.ll
The file was addedllvm/test/Transforms/IROutliner/outlining-different-output-blocks.ll
The file was modifiedllvm/include/llvm/Transforms/IPO/IROutliner.h
The file was modifiedllvm/test/Transforms/IROutliner/illegal-assumes.ll
The file was modifiedllvm/test/Transforms/IROutliner/illegal-vaarg.ll
The file was addedllvm/test/Transforms/IROutliner/outlining-same-output-blocks.ll
Commit 85af1d6257fac0741002f0144622f05c4ee1632c by aeubanks
[test] Fix pr45360.ll under NPM

The IR is the same under the NPM, but some basic block labels and value
names are different.
The file was modifiedllvm/test/Transforms/IndVarSimplify/X86/pr45360.ll
Commit 4ddf140c00408ecee9d20f4470e69e0f696d8f8a by jyknight
Fix PR35902: incorrect alignment used for ubsan check.

UBSan was using the complete-object align rather than nv alignment
when checking the "this" pointer of a method.

Furthermore, CGF.CXXABIThisAlignment was also being set incorrectly,
due to an incorrectly negated test. The latter doesn't appear to have
had any impact, due to it not really being used anywhere.

Differential Revision: https://reviews.llvm.org/D93072
The file was modifiedclang/lib/CodeGen/CodeGenFunction.cpp
The file was modifiedclang/lib/CodeGen/CGCXXABI.cpp
The file was modifiedclang/test/CodeGenCXX/catch-undef-behavior.cpp
Commit c0a2d3b90b3b024247cb38f73219ed595e974431 by arthur.j.odwyer
[libc++] Fix a test failure in 7b00e9fae3 (D93815).

"LLVM Buildbot on libcxx-libcxxabi-libunwind-armv7-linux" is not happy
with comparing `unsigned` and `int` [-Werror,-Wsign-compare].
The file was modifiedlibcxx/test/std/utilities/function.objects/func.search/func.search.default/default.pred.pass.cpp
Commit f782d5ea86f6fc82b51a0de688bf292f39cc4814 by tkeith
[flang] Detect call to abstract interface

A subroutine call or function reference to an abstract interface is
not legal.

Differential Revision: https://reviews.llvm.org/D93872
The file was modifiedflang/lib/Semantics/resolve-names.cpp
The file was modifiedflang/test/Semantics/resolve20.f90
Commit 4646de5d75cfce3da4ddeffb6eb8e66e38238800 by Yuanfang Chen
[NewPM][CodeGen] Introduce CodeGenPassBuilder to help build codegen pipeline

Following up on D67687.
Please refer to the RFC here http://lists.llvm.org/pipermail/llvm-dev/2020-July/143309.html

`CodeGenPassBuilder` is the NPM counterpart of `TargetPassConfig` with below differences.
- Debugging features (MIR print/verify, disable pass, start/stop-before/after, etc.) living in `TargetPassConfig` are moved to use PassInstrument as much as possible. (Implementation also lives in `TargetPassConfig.cpp`)
- `TargetPassConfig` is a polymorphic base (virtual inheritance) to build the target-dependent pipeline whereas `CodeGenPassBuilder` is the CRTP base/helper to implement the target-dependent pipeline. The motivation is flexibility for targets to customize the pipeline, inlining opportunity, and fits the overall NPM value semantics design.
- `TargetPassConfig` is a legacy immutable pass to declare hooks for targets to customize some target-independent codegen layer behavior. This is partially ported to TargetMachine::options. The rest, such as `createMachineScheduler/createPostMachineScheduler`, are left out for now. They should be implemented in LLVMTargetMachine in the future.

Reviewed By: arsenm, aeubanks

Differential Revision: https://reviews.llvm.org/D83608
The file was modifiedllvm/lib/CodeGen/TargetPassConfig.cpp
The file was addedllvm/include/llvm/CodeGen/MachinePassRegistry.def
The file was modifiedllvm/lib/CodeGen/LLVMTargetMachine.cpp
The file was modifiedllvm/include/llvm/CodeGen/TargetPassConfig.h
The file was addedllvm/include/llvm/CodeGen/CodeGenPassBuilder.h
The file was addedllvm/include/llvm/Target/CGPassBuilderOption.h
The file was modifiedllvm/lib/CodeGen/CMakeLists.txt
The file was modifiedllvm/include/llvm/Target/TargetMachine.h
The file was addedllvm/lib/CodeGen/CodeGenPassBuilder.cpp
Commit 94427af60c66ffea655a3084825c6c3a9deec1ad by Yuanfang Chen
Revert "[NewPM][CodeGen] Introduce CodeGenPassBuilder to help build codegen pipeline"

This reverts commit 4646de5d75cfce3da4ddeffb6eb8e66e38238800.

Some bots have build failure.
The file was removedllvm/lib/CodeGen/CodeGenPassBuilder.cpp
The file was removedllvm/include/llvm/Target/CGPassBuilderOption.h
The file was removedllvm/include/llvm/CodeGen/CodeGenPassBuilder.h
The file was modifiedllvm/lib/CodeGen/TargetPassConfig.cpp
The file was modifiedllvm/include/llvm/CodeGen/TargetPassConfig.h
The file was removedllvm/include/llvm/CodeGen/MachinePassRegistry.def
The file was modifiedllvm/lib/CodeGen/CMakeLists.txt
The file was modifiedllvm/lib/CodeGen/LLVMTargetMachine.cpp
The file was modifiedllvm/include/llvm/Target/TargetMachine.h
Commit 0e9abcfc1920f25a959eaa08116427b795e10dd8 by aeubanks
[AMDGPU][NewPM] Port amdgpu-promote-alloca(-to-vector)

And add to AMDGPU opt pipeline.

Don't pin an opt run to the legacy PM when -enable-new-pm=1 if these
passes (or passes introduced in https://reviews.llvm.org/D93863) are in
the list of passes.

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D93875
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPU.h
The file was modifiedllvm/test/CodeGen/AMDGPU/sroa-before-unroll.ll
The file was modifiedllvm/tools/opt/opt.cpp
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/vector-alloca.ll
Commit 4f568fbd21636c7c8d071f1901084cc0ae87f3ee by nemanja.i.ibm
[PowerPC] Do not emit HW loop when TLS var accessed in PHI of loop exit

If any PHI nodes in loop exit blocks have incoming values from the
loop that are accesses of TLS variables with local dynamic or general
dynamic TLS model, the address will be computed inside the loop. Since
this includes a call to __tls_get_addr, this will in turn cause the
CTR loops verifier to complain.
Disable CTR loops in such cases.

Fixes: https://bugs.llvm.org/show_bug.cgi?id=48527
The file was modifiedllvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
The file was addedllvm/test/CodeGen/PowerPC/pr48527.ll
Commit 8b67c98c4774313ab0ce5db1a975d2e69850368a by aqjune
[UpdateTestChecks] Fix update_analyze_test_checks.py failure
The file was modifiedllvm/utils/update_analyze_test_checks.py
Commit f3f9ce3b7948b250bc532818ed76a64cea8b6fbe by zakk.chen
[RISCV] Define vmclr.m/vmset.m intrinsics.

Define vmclr.m/vmset.m intrinsics and lower to vmxor.mm/vmxnor.mm.

Ideally all rvv pseudo instructions could be implemented in C header,
but those two instructions don't take an input, codegen can not guarantee
that the source register becomes the same as the destination.

We expand pseduo-v-inst into corresponding v-inst in
RISCVExpandPseudoInsts pass.

Reviewed By: craig.topper, frasercrmck

Differential Revision: https://reviews.llvm.org/D93849
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
The file was addedllvm/test/CodeGen/RISCV/rvv/vmset-rv64.ll
The file was addedllvm/test/CodeGen/RISCV/rvv/vmclr-rv32.ll
The file was modifiedllvm/include/llvm/IR/IntrinsicsRISCV.td
The file was modifiedllvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
The file was addedllvm/test/CodeGen/RISCV/rvv/vmclr-rv64.ll
The file was addedllvm/test/CodeGen/RISCV/rvv/vmset-rv32.ll
Commit 1e23802507d18ef8cb5a063325ff442ac7f527be by andrew.litteken
[IROutliner] Merging identical output blocks for extracted functions.

Many of the sets of output stores will be the same. When a block is
created, we check if there is an output block with the same set of store
instructions. If there is, we map the output block of the region back
to the block, so that the extra argument controlling the switch
statement can be set to the appropriate block value.

Tests:
- llvm/test/Transforms/IROutliner/outlining-same-output-blocks.ll

Reviewers: jroelofs, paquette

Differential Revision: https://reviews.llvm.org/D87298
The file was modifiedllvm/test/Transforms/IROutliner/outlining-remapped-outputs.ll
The file was modifiedllvm/test/Transforms/IROutliner/extraction.ll
The file was modifiedllvm/test/Transforms/IROutliner/illegal-memcpy.ll
The file was modifiedllvm/test/Transforms/IROutliner/illegal-vaarg.ll
The file was modifiedllvm/test/Transforms/IROutliner/outlining-same-output-blocks.ll
The file was modifiedllvm/test/Transforms/IROutliner/illegal-assumes.ll
The file was modifiedllvm/test/Transforms/IROutliner/illegal-memmove.ll
The file was modifiedllvm/lib/Transforms/IPO/IROutliner.cpp
Commit 1e3ed09165cf89b7f87318b4a5f7cab484661d49 by kazu
[CodeGen] Use llvm::append_range (NFC)
The file was modifiedllvm/lib/CodeGen/ReachingDefAnalysis.cpp
The file was modifiedllvm/lib/CodeGen/MachineModuleInfo.cpp
The file was modifiedllvm/lib/CodeGen/RDFLiveness.cpp
The file was modifiedllvm/lib/CodeGen/MachineOutliner.cpp
The file was modifiedllvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
The file was modifiedllvm/lib/CodeGen/MachineFunction.cpp
The file was modifiedllvm/lib/CodeGen/AsmPrinter/WinCFGuard.cpp
The file was modifiedllvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
The file was modifiedllvm/lib/CodeGen/SelectionDAG/StatepointLowering.cpp
The file was modifiedllvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
The file was modifiedllvm/lib/CodeGen/MachinePipeliner.cpp
The file was modifiedllvm/lib/CodeGen/CodeGenPrepare.cpp
The file was modifiedllvm/lib/CodeGen/RegAllocPBQP.cpp
Commit 5d2529f28f93a08c33bb3a22387e669075b66504 by kazu
[Scalar] Construct SmallVector with iterator ranges (NFC)
The file was modifiedllvm/lib/Transforms/Scalar/InferAddressSpaces.cpp
The file was modifiedllvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
The file was modifiedllvm/lib/Transforms/Scalar/GVN.cpp
The file was modifiedllvm/lib/Transforms/Scalar/Reassociate.cpp
The file was modifiedllvm/lib/Transforms/Scalar/SROA.cpp
Commit 2883cd98f3c04b6ee804a5c3ad897f7f0acf0bfa by kazu
[CFGPrinter] Use succ_empty (NFC)
The file was modifiedllvm/lib/Analysis/CFGPrinter.cpp
Commit 55d13e6a867450d4a131612e4e93d60458016c8d by i
[asan][test] Annotate glibc specific tests with REQUIRES: glibc-2.27
The file was modifiedcompiler-rt/test/asan/TestCases/Linux/printf-fortify-1.c
The file was modifiedcompiler-rt/test/asan/TestCases/malloc-no-intercept.c
The file was modifiedcompiler-rt/test/asan/TestCases/Linux/printf-fortify-5.c
The file was modifiedcompiler-rt/test/asan/TestCases/Linux/swapcontext_annotation.cpp
The file was modifiedcompiler-rt/test/asan/TestCases/Linux/printf-fortify-3.c
The file was modifiedcompiler-rt/test/asan/TestCases/Linux/swapcontext_test.cpp
The file was modifiedcompiler-rt/test/asan/TestCases/Linux/printf-fortify-2.c
The file was modifiedcompiler-rt/test/asan/TestCases/Linux/printf-fortify-4.c
Commit c2ef06d3dd09d4e4e9665ca9f61e7672ad937827 by aeubanks
[NewPM] Port infer-address-spaces

And add it to the AMDGPU opt pipeline.

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D93880
The file was modifiedllvm/test/Transforms/InferAddressSpaces/AMDGPU/infer-address-space.ll
The file was modifiedllvm/tools/opt/opt.cpp
The file was modifiedllvm/lib/Transforms/Scalar/InferAddressSpaces.cpp
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
The file was modifiedllvm/lib/Passes/PassBuilder.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/infer-addrpace-pipeline.ll
The file was modifiedllvm/lib/Passes/PassRegistry.def
The file was addedllvm/include/llvm/Transforms/Scalar/InferAddressSpaces.h
Commit c5d100fdf2d782886215061e1ae0b4b072babce0 by aeubanks
[test] Fix conditional-temporaries.cpp

Broken by https://reviews.llvm.org/D93880.
(but now the test is much better :) )
The file was modifiedclang/test/CodeGenCXX/conditional-temporaries.cpp
Commit a8970dff1aece1f83e63f723847098ba992ef185 by i
[ubsan][test] FLush stdout before checking interleaved stdout/stderr

Detected by musl.
The file was modifiedcompiler-rt/test/ubsan/TestCases/Misc/monitor.cpp
Commit 53f80d6b3a01a79a9d448ad117c4b54a15ad08af by pavel
[lldb] Fix logging in lldb-server tests
The file was modifiedlldb/packages/Python/lldbsuite/test/tools/lldb-server/gdbremote_testcase.py
Commit ed146d6291ce510ef954d350e2ca5a107890c2d2 by grimar
[LLD][ELF] - Use LLVM_ELF_IMPORT_TYPES_ELFT instead of multiple types definitions. NFCI.

We can reduce the number of "using" declarations.
`LLVM_ELF_IMPORT_TYPES_ELFT` was extended in D93801.

Differential revision: https://reviews.llvm.org/D93856
The file was modifiedlld/ELF/SyntheticSections.h
The file was modifiedlld/ELF/Writer.cpp
The file was modifiedlld/ELF/InputFiles.h
Commit ae6e89327b04a94b6d1a2533c598ec6be60eb922 by aqjune
Precommit tests that have poison as shufflevector's placeholder

This commit copies existing tests at llvm/Transforms containing
'shufflevector X, undef' and replaces them with 'shufflevector X, poison'.
The new copied tests have *-inseltpoison.ll suffix at its file name
(as db7a2f347f132b3920415013d62d1adfb18d8d58 did)
See https://reviews.llvm.org/D93793

Test files listed using

grep -R -E "^[^;]*shufflevector <.*> .*, <.*> undef" | cut -d":" -f1 | uniq

Test files copied & updated using

file_org=llvm/test/Transforms/$1
if [[ "$file_org" = *-inseltpoison.ll ]]; then
  file=$file_org
else
  file=${file_org%.ll}-inseltpoison.ll
  if [ ! -f $file ]; then
    cp $file_org $file
  fi
fi
sed -i -E 's/^([^;]*)shufflevector <(.*)> (.*), <(.*)> undef/\1shufflevector <\2> \3, <\4> poison/g' $file
head -1 $file | grep "Assertions have been autogenerated by utils/update_test_checks.py" -q
if [ "$?" == 1 ]; then
  echo "$file : should be manually updated"
  # The test is manually updated
  exit 1
fi
python3 ./llvm/utils/update_test_checks.py --opt-binary=./build-releaseassert/bin/opt $file
The file was modifiedllvm/test/Transforms/LoopUnroll/PowerPC/p8-unrolling-legalize-vectors-inseltpoison.ll
The file was addedllvm/test/Transforms/InstCombine/nsw-inseltpoison.ll
The file was modifiedllvm/test/Transforms/InstCombine/shift-add-inseltpoison.ll
The file was addedllvm/test/Transforms/InterleavedAccess/X86/interleaved-accesses-64bits-avx-inseltpoison.ll
The file was addedllvm/test/Transforms/InstCombine/X86/x86-pshufb-inseltpoison.ll
The file was modifiedllvm/test/Transforms/InstCombine/X86/x86-vector-shifts-inseltpoison.ll
The file was addedllvm/test/Transforms/InstCombine/X86/x86-muldq-inseltpoison.ll
The file was addedllvm/test/Transforms/InstCombine/X86/x86-sse4a-inseltpoison.ll
The file was addedllvm/test/Transforms/InstCombine/vector-concat-binop-inseltpoison.ll
The file was addedllvm/test/Transforms/InstCombine/bswap-inseltpoison.ll
The file was addedllvm/test/Transforms/VectorCombine/X86/shuffle-inseltpoison.ll
The file was addedllvm/test/Transforms/InstCombine/shuffle_select-inseltpoison.ll
The file was modifiedllvm/test/Transforms/InstCombine/scalarization-inseltpoison.ll
The file was modifiedllvm/test/Transforms/InstCombine/trunc-extractelement-inseltpoison.ll
The file was modifiedllvm/test/Transforms/InstCombine/vector_gep1-inseltpoison.ll
The file was addedllvm/test/Transforms/InterleavedAccess/AArch64/binopshuffles-inseltpoison.ll
The file was addedllvm/test/Transforms/InterleavedAccess/X86/interleavedLoad-inseltpoison.ll
The file was addedllvm/test/Transforms/VectorCombine/AArch64/vscale-bitcast-shuffle-inseltpoison.ll
The file was addedllvm/test/Transforms/InstCombine/shuffle-select-narrow-inseltpoison.ll
The file was modifiedllvm/test/Transforms/CodeGenPrepare/X86/x86-shuffle-sink-inseltpoison.ll
The file was modifiedllvm/test/Transforms/InstCombine/vec_shuffle-inseltpoison.ll
The file was modifiedllvm/test/Transforms/InstCombine/vec_demanded_elts-inseltpoison.ll
The file was modifiedllvm/test/Transforms/InstSimplify/vscale-inseltpoison.ll
The file was modifiedllvm/test/Transforms/SpeculativeExecution/spec-other-inseltpoison.ll
The file was modifiedllvm/test/Transforms/CodeGenPrepare/ARM/sinkchain-inseltpoison.ll
The file was modifiedllvm/test/Transforms/InstCombine/vscale_extractelement-inseltpoison.ll
The file was addedllvm/test/Transforms/PhaseOrdering/X86/shuffle-inseltpoison.ll
The file was modifiedllvm/test/Transforms/Scalarizer/dbgloc-bug-inseltpoison.ll
The file was modifiedllvm/test/Transforms/InstCombine/vec_phi_extract-inseltpoison.ll
The file was modifiedllvm/test/Transforms/Scalarizer/order-bug-inseltpoison.ll
The file was addedllvm/test/Transforms/InterleavedAccess/X86/interleavedStore-inseltpoison.ll
The file was addedllvm/test/Transforms/LoopSimplify/do-preheader-dbg-inseltpoison.ll
The file was addedllvm/test/Transforms/InstSimplify/ConstProp/vector-undef-elts-inseltpoison.ll
The file was modifiedllvm/test/Transforms/Scalarizer/basic-inseltpoison.ll
The file was modifiedllvm/test/Transforms/InstCombine/masked_intrinsics-inseltpoison.ll
The file was addedllvm/test/Transforms/InstCombine/X86/x86-avx2-inseltpoison.ll
The file was addedllvm/test/Transforms/InterleavedAccess/ARM/interleaved-accesses-extract-user-inseltpoison.ll
The file was modifiedllvm/test/Transforms/PhaseOrdering/X86/scalarization-inseltpoison.ll
The file was modifiedllvm/test/Transforms/InstSimplify/ConstProp/vscale-inseltpoison.ll
The file was addedllvm/test/Transforms/InstCombine/pr2645-0-inseltpoison.ll
The file was addedllvm/test/Transforms/CodeGenPrepare/AArch64/sink-free-instructions-inseltpoison.ll
The file was addedllvm/test/Transforms/InterleavedAccess/AArch64/interleaved-accesses-extract-user-inseltpoison.ll
The file was addedllvm/test/Transforms/Scalarizer/phi-bug-inseltpoison.ll
The file was addedllvm/test/Transforms/InstCombine/shufflevec-constant-inseltpoison.ll
The file was addedllvm/test/Transforms/InstCombine/logical-select-inseltpoison.ll
The file was addedllvm/test/Transforms/DeadStoreElimination/masked-dead-store-inseltpoison.ll
The file was modifiedllvm/test/Transforms/CodeGenPrepare/ARM/sink-add-mul-shufflevector-inseltpoison.ll
The file was modifiedllvm/test/Transforms/InstCombine/AMDGPU/amdgcn-demanded-vector-elts-inseltpoison.ll
The file was modifiedllvm/test/Transforms/InstCombine/vscale_insertelement-inseltpoison.ll
The file was addedllvm/test/Transforms/InstCombine/assume-inseltpoison.ll
The file was addedllvm/test/Transforms/InstCombine/X86/x86-f16c-inseltpoison.ll
The file was addedllvm/test/Transforms/InstCombine/sub-of-negatible-inseltpoison.ll
The file was modifiedllvm/test/Transforms/InstCombine/X86/x86-addsub-inseltpoison.ll
The file was addedllvm/test/Transforms/Inline/inlined-loop-metadata-inseltpoison.ll
The file was modifiedllvm/test/Transforms/InstCombine/shufflevector-div-rem-inseltpoison.ll
The file was addedllvm/test/Transforms/VectorCombine/X86/no-sse-inseltpoison.ll
The file was modifiedllvm/test/Transforms/InstCombine/X86/x86-pack-inseltpoison.ll
The file was addedllvm/test/Transforms/InstCombine/trunc-inseltpoison.ll
The file was addedllvm/test/Transforms/InterleavedAccess/AArch64/interleaved-accesses-inseltpoison.ll
The file was modifiedllvm/test/Transforms/InstCombine/extractelement-inseltpoison.ll
The file was modifiedllvm/test/Transforms/InstCombine/icmp-bc-vec-inseltpoison.ll
The file was addedllvm/test/Transforms/CodeGenPrepare/ARM/sink-free-instructions-inseltpoison.ll
The file was addedllvm/test/Transforms/InstCombine/mul-inseltpoison.ll
The file was addedllvm/test/Transforms/InstCombine/shuffle-cast-inseltpoison.ll
The file was addedllvm/test/Transforms/InstCombine/vec-binop-select-inseltpoison.ll
The file was modifiedllvm/test/Transforms/InstCombine/select-extractelement-inseltpoison.ll
The file was addedllvm/test/Transforms/LoopUnroll/X86/pr46430-inseltpoison.ll
The file was addedllvm/test/Transforms/InstCombine/obfuscated_splat-inseltpoison.ll
The file was modifiedllvm/test/Transforms/CodeGenPrepare/X86/vec-shift-inseltpoison.ll
The file was addedllvm/test/Transforms/InstCombine/icmp-vec-inseltpoison.ll
The file was addedllvm/test/Transforms/InstCombine/shufflevec-bitcast-inseltpoison.ll
The file was modifiedllvm/test/Transforms/LoopStrengthReduce/ARM/vctp-chains-inseltpoison.ll
The file was addedllvm/test/Transforms/CodeGenPrepare/X86/cgp_shuffle_crash-inseltpoison.ll
The file was addedllvm/test/Transforms/InstCombine/X86/shufflemask-undef-inseltpoison.ll
The file was addedllvm/test/Transforms/InstCombine/type_pun-inseltpoison.ll
The file was modifiedllvm/test/Transforms/CodeGenPrepare/X86/gather-scatter-opt-inseltpoison.ll
The file was addedllvm/test/Transforms/InstCombine/X86/x86-vpermil-inseltpoison.ll
The file was addedllvm/test/Transforms/InstCombine/fmul-inseltpoison.ll
The file was addedllvm/test/Transforms/InterleavedAccess/ARM/interleaved-accesses-inseltpoison.ll
The file was addedllvm/test/Transforms/LoopStrengthReduce/AMDGPU/lsr-void-inseltpoison.ll
The file was modifiedllvm/test/Transforms/CodeGenPrepare/AArch64/gather-scatter-opt-inseltpoison.ll
The file was modifiedllvm/test/Transforms/InstCombine/insert-extract-shuffle-inseltpoison.ll
The file was modifiedllvm/test/Transforms/InstCombine/vec_gep_scalar_arg-inseltpoison.ll
The file was addedllvm/test/Transforms/InstSimplify/shufflevector-inseltpoison.ll
Commit a0b68a2925fbe31f4b0af27677d55feaff6b1362 by pavel
[lldb] Deduplicate some tests in TestLldbGdbServer

Use the new gdb-remote test case factory to generate debugserver and
llgs variants, handling the simple cases first.
The file was modifiedlldb/test/API/tools/lldb-server/TestLldbGdbServer.py
Commit 5abfeccf10bcbc0d673ece21ddd8d4ac4a0e7594 by mark.murray
[ARM][AArch64] Add Cortex-A78C Support for Clang and LLVM

This patch upstreams support for the Armv8-a Cortex-A78C
processor for AArch64 and ARM.

In detail:

Adding cortex-a78c as cpu option for aarch64 and arm targets in clang
Adding Cortex-A78C CPU name and ProcessorModel in llvm
Details of the CPU can be found here:
https://www.arm.com/products/silicon-ip-cpu/cortex-a/cortex-a78c
The file was modifiedclang/test/Driver/aarch64-cpus.c
The file was modifiedllvm/lib/Target/AArch64/AArch64Subtarget.cpp
The file was modifiedllvm/lib/Target/AArch64/AArch64Subtarget.h
The file was modifiedllvm/unittests/Support/TargetParserTest.cpp
The file was modifiedllvm/lib/Target/ARM/ARMSubtarget.cpp
The file was modifiedllvm/lib/Target/ARM/ARMSubtarget.h
The file was modifiedllvm/lib/Target/AArch64/AArch64.td
The file was modifiedllvm/include/llvm/Support/ARMTargetParser.def
The file was modifiedllvm/include/llvm/Support/AArch64TargetParser.def
The file was modifiedllvm/lib/Target/ARM/ARM.td
Commit 0a19fc3088f58f9a73fdb39a373cba7885be557f by nemanjai
[PowerPC] Disable CTR loops containing operations on half-precision

On subtargets prior to Power9, conversions to/from half precision
are lowered to libcalls. This makes loops containing such operations
invalid candidates for HW loops.

Fixes: https://bugs.llvm.org/show_bug.cgi?id=48519
The file was addedllvm/test/CodeGen/PowerPC/pr48519.ll
The file was modifiedllvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
Commit aebb4a60522615ca4fd542e8ece8df1e4f42d657 by fraser
[RISCV] Rewrite and simplify helper function. NFC.

Reviewed By: luismarques

Differential Revision: https://reviews.llvm.org/D93851
The file was modifiedllvm/lib/Target/RISCV/RISCVISelLowering.cpp
Commit 7486de1b2eced2cccc7b0b95598e9ab45039d700 by nemanja.i.ibm
[PowerPC] Provide patterns for permuted scalar to vector for pre-P8

We will emit these permuted nodes on all VSX little endian subtargets
but don't have the patterns available to match them on subtargets
that don't have direct moves.

Fixes: https://bugs.llvm.org/show_bug.cgi?id=47916
The file was modifiedllvm/test/CodeGen/PowerPC/load-and-splat.ll
The file was modifiedllvm/lib/Target/PowerPC/PPCInstrVSX.td
The file was modifiedllvm/test/CodeGen/PowerPC/canonical-merge-shuffles.ll
The file was addedllvm/test/CodeGen/PowerPC/pr47916.ll
The file was modifiedllvm/lib/Target/PowerPC/PPCVSXSwapRemoval.cpp
Commit 374ef57f1379d3d3bbe5bfb19f1d2ea7e79b6db9 by lebedev.ri
[InstCombine] 'hoist xor-by-constant from xor-by-value': completely give up on constant exprs

As Mikael Holmén is noting in the post-commit review for the first fix
https://reviews.llvm.org/rGd4ccef38d0bb#967466
not hoisting constantexprs is not enough,
because if the xor originally was a constantexpr (i.e. X is a constantexpr).
`SimplifyAssociativeOrCommutative()` in `visitXor()` will immediately
undo this transform, thus again causing an infinite combine loop.

This transform has resulted in a surprising number of constantexpr failures.
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
The file was modifiedllvm/test/Transforms/InstCombine/hoist-xor-by-constant-from-xor-by-value.ll
Commit b76014a4f15ad9f3151862fcc6c6ab2f0f505199 by nicolai.haehnle
RegionInfo: use a range-based for loop [NFCI]

Change-Id: I9985d72191a2b0680195032acf8a14ad2ba954ed

Differential Revision: https://reviews.llvm.org/D92932
The file was modifiedllvm/include/llvm/Analysis/RegionInfoImpl.h