UnstableChanges

Summary

  1. [mlir][linalg] Add vectorization for linalg on tensor ops (details)
  2. sanitizer: fix typo/spelling: Dissassemble → Disassemble (details)
  3. [RISCV] Add earlyclobber of destination register to vmsbf.m/vmsif.m/vmsof.m instructions (details)
  4. [MSSAUpdater] Skip renaming when inserting def in unreachable block. (details)
  5. [NewPM][AMDGPU] Port amdgpu-lower-kernel-attributes (details)
  6. [RISCV] Don't use tail agnostic policy on instructions where destination is tied to source (details)
  7. [IROutliner] Adding a cost model, and debug option to turn the model off. (details)
  8. [IR] Let IRBuilder's CreateVectorSplat/CreateShuffleVector use poison as placeholder (details)
  9. [RISCV] Fill out basic integer RVV ISel patterns (details)
  10. [SLP] replace local reduction enum with RecurrenceKind; NFCI (details)
  11. [mlir][python] Add FlatSymbolRef attribute. (details)
Commit cf216670a0bd1f2ce561a315e00649740f117e1c by thomasraoux
[mlir][linalg] Add vectorization for linalg on tensor ops

Support vectorization of linalg ops using tensor inputs/outputs.

Differential Revision: https://reviews.llvm.org/D93890
The file was modifiedmlir/test/Dialect/Linalg/vectorization.mlir
The file was modifiedmlir/lib/Dialect/Linalg/Transforms/Vectorization.cpp
The file was modifiedmlir/lib/Dialect/Vector/VectorOps.cpp
Commit c1e85b6c1b4d83d24b130b191112e1b99cf74a8a by thakis
sanitizer: fix typo/spelling: Dissassemble → Disassemble

Differential Revision: https://reviews.llvm.org/D93902
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_symbolizer_report.cpp
Commit 2ae760e27e6ad27cf16603e2fa805bec45efc68c by craig.topper
[RISCV] Add earlyclobber of destination register to vmsbf.m/vmsif.m/vmsof.m instructions

The spec for these instructions include this note. "The destination register
cannot overlap either the source register or the mask register ('v0') if the
instruction is masked." So we need earlyclobber to enforce this constraint.

I've regenerated the tests with update_llc_test_checks.py to show the
effects of the earlyclobber.

Reviewed By: khchen, frasercrmck

Differential Revision: https://reviews.llvm.org/D93867
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmsof-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmsif-rv32.ll
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmsbf-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmsif-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmsof-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmsbf-rv64.ll
Commit b980bed34b96a9a85c256b1627ef9339d82829eb by flo
[MSSAUpdater] Skip renaming when inserting def in unreachable block.

This fixes a updater crash when moving memory defs between unreachable
blocks.

Fixes PR48616.
The file was modifiedllvm/test/Transforms/GVN/preserve-memoryssa.ll
The file was modifiedllvm/lib/Analysis/MemorySSAUpdater.cpp
Commit 7ecbe0c7a01848fce88dcf3b6977cec866e9938b by aeubanks
[NewPM][AMDGPU] Port amdgpu-lower-kernel-attributes

And add it to the AMDGPU opt pipeline.

This is a function pass instead of a module pass (like the legacy pass)
because it's getting added to a CGSCCPassManager, and you can't put a
module pass in a CGSCCPassManager.

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D93885
The file was modifiedllvm/tools/opt/opt.cpp
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPU.h
The file was modifiedllvm/test/CodeGen/AMDGPU/reqd-work-group-size.ll
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPULowerKernelAttributes.cpp
Commit 79cbb003c53009e5ca35b804bb7655dba97776e7 by craig.topper
[RISCV] Don't use tail agnostic policy on instructions where destination is tied to source

If the destination is tied, then user has some control of the
register used for input. They would have the ability to control
the value of any tail elements. By using tail agnostic we take
this option away from them.

Its not clear that the intrinsics are defined such that this isn't
supposed to work. And undisturbed is a valid implementation for agnostic
so code wouldn't even fail to work on all systems if we always used
agnostic.

The vcompress intrinsic is defined to require tail undisturbed so
at minimum we need this for that instruction or need to redefine
the intrinsic.

I've made an exception here for vmv.s.x/fmv.s.f and reduction
instructions which only write to element 0 regardless of the tail
policy. This allows us to keep the agnostic policy on those which
should allow better redundant vsetvli removal.

An enhancement would be to check for undef input and keep the
agnostic policy, but we don't have good test coverage for that yet.

Reviewed By: khchen

Differential Revision: https://reviews.llvm.org/D93878
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfmacc-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmsltu-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmsbf-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmfge-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmin-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vlse-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vor-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfnmsac-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vwsubu-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vdivu-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfdiv-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vle-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vsub-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vnmsac-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vwmaccus-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmflt-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfwmacc-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmfne-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmfle-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vnmsub-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vasub-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfnmsac-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmadd-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmsne-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vsaddu-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vasub-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vwaddu-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmfgt-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vwadd.w-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfsgnj-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfwmul-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmsle-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfmax-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vwsubu.w-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfdiv-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfslide1up-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vwsub-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfwsub-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmacc-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfsgnjx-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmflt-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfrdiv-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfmacc-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmsle-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vremu-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vwadd.w-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vwmaccus-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vsra-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmacc-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vsmul-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vlxe-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmsleu-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vdiv-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfwadd-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmax-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vslide1up-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmsif-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vnsrl-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfsgnjn-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vssrl-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vrem-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfadd-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vminu-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vxor-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vwsub.w-rv32.ll
The file was modifiedllvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vslideup-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfmul-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vdivu-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vwsubu-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vsll-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vwmaccu-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfnmsub-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vnsra-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vwaddu.w-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vdiv-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vwadd-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmadd-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmseq-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vnclip-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vnclipu-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vssra-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/viota-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmslt-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vwmaccsu-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vremu-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfwnmsac-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vslidedown-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vwadd-rv32.ll
The file was modifiedllvm/lib/Target/RISCV/RISCVISelLowering.cpp
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfnmacc-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vwsubu.w-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfmsub-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmsgt-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfmax-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmsgtu-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vsll-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmulhsu-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmulhu-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmulh-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vwmul-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfwmacc-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vlxe-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vid-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfmin-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfslide1up-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmin-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vsmul-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vminu-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vrem-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vor-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmul-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vrgather-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmsgtu-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmulhu-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vaadd-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfwnmacc-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfrdiv-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vwsub.w-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmfeq-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfmul-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vssub-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmsltu-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfslide1down-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vwmul-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vleff-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmsleu-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfwnmacc-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vaadd-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfwadd-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfwsub.w-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfmadd-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfrsub-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfsub-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmsif-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vslidedown-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vnclip-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfsgnj-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfrsub-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/viota-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfmadd-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vadd-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfwmsac-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmaxu-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vrgather-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vwsub-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmsgt-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vwmulsu-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vsub-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfnmadd-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vadd-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vslide1down-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vand-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfmin-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vwaddu-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vwmacc-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vle-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfnmacc-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vnclipu-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vrsub-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfwsub-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfnmsub-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfwsub.w-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vslide1down-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfmsac-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vaaddu-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmulhsu-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfwmsac-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmsbf-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmulh-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmsof-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfwadd.w-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vsaddu-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmseq-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vnsrl-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vwmulu-rv64.ll
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmul-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfwadd.w-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfsgnjn-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vslideup-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vssub-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfwmul-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vsra-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmfge-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmfle-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vwaddu.w-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vnmsac-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vwmacc-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vwmaccsu-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vaaddu-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vnmsub-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vssrl-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmsne-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vwmulsu-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfmsac-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vid-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vsrl-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vwmulu-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vrsub-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vlse-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vwmaccu-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vsrl-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vand-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfslide1down-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfwnmsac-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfadd-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vasubu-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfsub-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vnsra-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vxor-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfnmadd-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmfeq-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmfne-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmsof-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vasubu-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vleff-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfsgnjx-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmfgt-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vsadd-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmslt-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfmsub-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vsadd-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmaxu-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vssubu-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vssubu-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmax-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vssra-rv32.ll
Commit 6df161a2fbf62bd4ab7297fe1fb234cdc972a48b by andrew.litteken
[IROutliner] Adding a cost model, and debug option to turn the model off.

This adds a cost model that takes into account the total number of
machine instructions to be removed from each region, the number of
instructions added by adding a new function with a set of instructions,
and the instructions added by handling arguments.

Tests not adding flags:

llvm/test/Transforms/IROutliner/outlining-cost-model.ll

Reviewers: jroelofs, paquette

Differential Revision: https://reviews.llvm.org/D87299
The file was modifiedllvm/lib/Transforms/IPO/IROutliner.cpp
The file was modifiedllvm/test/Transforms/IROutliner/illegal-calls.ll
The file was modifiedllvm/test/Transforms/IROutliner/outlining-same-constants.ll
The file was modifiedllvm/test/Transforms/IROutliner/illegal-invoke.ll
The file was modifiedllvm/test/Transforms/IROutliner/illegal-memmove.ll
The file was modifiedllvm/test/Transforms/IROutliner/illegal-allocas.ll
The file was modifiedllvm/test/Transforms/IROutliner/illegal-catchpad.ll
The file was modifiedllvm/test/Transforms/IROutliner/illegal-frozen.ll
The file was modifiedllvm/test/Transforms/IROutliner/illegal-cleanup.ll
The file was modifiedllvm/test/Transforms/IROutliner/outlining-different-globals.ll
The file was modifiedllvm/test/Transforms/IROutliner/illegal-memcpy.ll
The file was addedllvm/test/Transforms/IROutliner/outlining-debug-statements.ll
The file was modifiedllvm/test/Transforms/IROutliner/outlining-address-taken.ll
The file was modifiedllvm/test/Transforms/IROutliner/illegal-phi-nodes.ll
The file was modifiedllvm/test/Transforms/IROutliner/illegal-assumes.ll
The file was modifiedllvm/test/Transforms/IROutliner/illegal-gep.ll
The file was modifiedllvm/test/Transforms/IROutliner/outlining-same-globals.ll
The file was modifiedllvm/test/Transforms/IROutliner/outlining-constants-vs-registers.ll
The file was modifiedllvm/include/llvm/Transforms/IPO/IROutliner.h
The file was modifiedllvm/test/Transforms/IROutliner/illegal-branches.ll
The file was modifiedllvm/test/Transforms/IROutliner/outlining-commutative-fp.ll
The file was modifiedllvm/test/Transforms/IROutliner/outlining-different-structure.ll
The file was modifiedllvm/test/Transforms/IROutliner/illegal-memset.ll
The file was modifiedllvm/test/Transforms/IROutliner/illegal-landingpad.ll
The file was modifiedllvm/test/Transforms/IROutliner/illegal-callbr.ll
The file was modifiedllvm/test/Transforms/IROutliner/outlining-same-output-blocks.ll
The file was modifiedllvm/test/Transforms/IROutliner/extraction.ll
The file was modifiedllvm/test/Transforms/IROutliner/legal-debug.ll
The file was modifiedllvm/test/Transforms/IROutliner/outlining-different-output-blocks.ll
The file was modifiedllvm/test/Transforms/IROutliner/outlining-remapped-outputs.ll
The file was modifiedllvm/test/Transforms/IROutliner/outlining-commutative.ll
The file was modifiedllvm/test/Transforms/IROutliner/illegal-vaarg.ll
The file was addedllvm/test/Transforms/IROutliner/outlining-cost-model.ll
The file was modifiedllvm/test/Transforms/IROutliner/outlining-different-constants.ll
Commit 278aa65cc495b2f548018eb2fd96351d36b4591f by aqjune
[IR] Let IRBuilder's CreateVectorSplat/CreateShuffleVector use poison as placeholder

This patch updates IRBuilder to create insertelement/shufflevector using poison as a placeholder.

Reviewed By: nikic

Differential Revision: https://reviews.llvm.org/D93793
The file was modifiedllvm/test/Transforms/LoopVectorize/scalable-loop-unpredicated-body-scalar-tail.ll
The file was modifiedllvm/test/Transforms/VectorCombine/X86/shuffle.ll
The file was modifiedllvm/test/Transforms/PhaseOrdering/X86/shuffle-inseltpoison.ll
The file was modifiedllvm/test/Transforms/VectorCombine/X86/shuffle-inseltpoison.ll
The file was modifiedllvm/test/Transforms/LoopVectorize/ARM/mve-gather-scatter-tailpred.ll
The file was modifiedllvm/test/Transforms/LoopVectorize/X86/tail_loop_folding.ll
The file was modifiedllvm/test/Transforms/LoopVectorize/X86/load-deref-pred.ll
The file was modifiedclang/test/CodeGenCXX/vector-conditional.cpp
The file was modifiedllvm/test/Transforms/LowerMatrixIntrinsics/multiply-double.ll
The file was modifiedllvm/test/Transforms/LowerMatrixIntrinsics/multiply-add-sub-double-row-major.ll
The file was modifiedllvm/test/Transforms/LowerMatrixIntrinsics/multiply-fused-loops.ll
The file was modifiedllvm/test/Transforms/InstCombine/getelementptr.ll
The file was modifiedllvm/test/Transforms/LoopVectorize/ARM/mve-reduction-types.ll
The file was modifiedllvm/test/Transforms/LoopVectorize/consecutive-ptr-uniforms.ll
The file was modifiedclang/test/CodeGen/arm-mve-intrinsics/vmulq.c
The file was modifiedllvm/test/Transforms/LoopVectorize/ARM/pointer_iv.ll
The file was modifiedllvm/test/Transforms/InstCombine/type_pun-inseltpoison.ll
The file was modifiedllvm/test/Transforms/LoopVectorize/X86/masked_load_store.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/jumbled-load-shuffle-placement.ll
The file was modifiedllvm/test/Transforms/LoopVectorize/X86/constant-fold.ll
The file was modifiedllvm/test/Transforms/LoopVectorize/float-induction.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/insert-element-build-vector-inseltpoison.ll
The file was modifiedllvm/test/Transforms/VectorCombine/AMDGPU/as-transition.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/extract.ll
The file was modifiedclang/test/CodeGen/arm-mve-intrinsics/dup.c
The file was modifiedllvm/test/Transforms/VectorCombine/X86/extract-cmp.ll
The file was modifiedllvm/test/Transforms/InstCombine/vec_shuffle.ll
The file was modifiedllvm/test/Transforms/LoopVectorize/PowerPC/optimal-epilog-vectorization.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/AArch64/PR38339.ll
The file was modifiedllvm/test/Transforms/LowerMatrixIntrinsics/multiply-fused.ll
The file was modifiedclang/test/CodeGenCXX/vector-splat-conversion.cpp
The file was modifiedllvm/test/Transforms/LoopVectorize/X86/small-size.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/external_user_jumbled_load.ll
The file was modifiedllvm/test/Transforms/LoopVectorize/invariant-store-vectorization.ll
The file was modifiedllvm/test/Transforms/LoopVectorize/AArch64/outer_loop_test1_no_explicit_vect_width.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/slp-max-phi-size.ll
The file was modifiedclang/test/CodeGenOpenCL/bool_cast.cl
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/PR39774.ll
The file was modifiedllvm/test/Transforms/LoopVectorize/float-minmax-instruction-flag.ll
The file was modifiedllvm/test/Transforms/LowerMatrixIntrinsics/multiply-float-contraction.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/external_user_jumbled_load-inseltpoison.ll
The file was modifiedllvm/test/Transforms/LoopVectorize/interleaved-accesses-pred-stores.ll
The file was modifiedclang/test/CodeGen/arm-mve-intrinsics/vaddq.c
The file was modifiedclang/test/CodeGen/arm-mve-intrinsics/compare.c
The file was modifiedllvm/test/Transforms/LowerMatrixIntrinsics/multiply-double-contraction.ll
The file was modifiedclang/test/CodeGen/arm-mve-intrinsics/vhaddq.c
The file was modifiedllvm/test/Transforms/InstCombine/gep-inbounds-null.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/stores_vectorize.ll
The file was modifiedllvm/test/Transforms/LoopVectorize/X86/invariant-store-vectorization.ll
The file was modifiedllvm/test/Transforms/LoopVectorize/pointer-induction.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/load-merge.ll
The file was modifiedllvm/test/Transforms/Scalarizer/vector-gep.ll
The file was modifiedclang/test/CodeGenOpenCL/shifts.cl
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/hoist.ll
The file was modifiedllvm/test/Transforms/VectorCombine/X86/load.ll
The file was modifiedclang/test/CodeGen/vecshift.c
The file was modifiedllvm/test/Transforms/LoopVectorize/X86/vect.omp.force.small-tc.ll
The file was modifiedllvm/test/Transforms/LoopVectorize/interleaved-accesses.ll
The file was modifiedllvm/test/Transforms/LoopVectorize/outer_loop_test2.ll
The file was modifiedllvm/test/Transforms/LoopVectorize/select-reduction.ll
The file was modifiedclang/test/CodeGenCXX/matrix-type-operators.cpp
The file was modifiedllvm/test/Transforms/LoopVectorize/vector-geps.ll
The file was modifiedllvm/test/Transforms/LoopVectorize/X86/metadata-enable.ll
The file was modifiedllvm/test/Transforms/LoopVectorize/interleaved-accesses-1.ll
The file was modifiedllvm/test/Transforms/PhaseOrdering/X86/vdiv.ll
The file was modifiedclang/test/CodeGen/arm-mve-intrinsics/vqdmulhq.c
The file was modifiedllvm/test/Transforms/LoopVectorize/pr44488-predication.ll
The file was modifiedllvm/test/Transforms/LoopVectorize/pr46525-expander-insertpoint.ll
The file was modifiedllvm/test/Transforms/InstCombine/type_pun.ll
The file was modifiedllvm/test/Transforms/LowerMatrixIntrinsics/multiply-fused-multiple-blocks.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/jumbled-load-multiuse.ll
The file was modifiedllvm/test/Transforms/PhaseOrdering/X86/vector-reductions.ll
The file was modifiedllvm/test/Transforms/LoopVectorize/X86/outer_loop_test1_no_explicit_vect_width.ll
The file was modifiedllvm/test/Transforms/LoopVectorize/optimal-epilog-vectorization.ll
The file was modifiedpolly/test/Isl/CodeGen/simple_vec_cast.ll
The file was modifiedclang/test/CodeGen/SystemZ/builtins-systemz-zvector.c
The file was modifiedllvm/lib/IR/IRBuilder.cpp
The file was modifiedllvm/test/Transforms/InstCombine/vscale_cmp.ll
The file was modifiedllvm/test/Transforms/LoopVectorize/induction.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/store-jumbled.ll
The file was modifiedllvm/test/Transforms/LowerMatrixIntrinsics/multiply-float-contraction-fmf.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/PR32086.ll
The file was modifiedllvm/test/Transforms/LoopVectorize/X86/x86-interleaved-accesses-masked-group.ll
The file was modifiedclang/test/CodeGen/arm-mve-intrinsics/vqaddq.c
The file was modifiedllvm/test/Transforms/VectorCombine/AMDGPU/as-transition-inseltpoison.ll
The file was modifiedllvm/test/Transforms/LoopVectorize/X86/uniform_mem_op.ll
The file was modifiedllvm/test/Transforms/PhaseOrdering/X86/scalarization-inseltpoison.ll
The file was modifiedllvm/test/Transforms/LoopVectorize/dont-fold-tail-for-const-TC.ll
The file was modifiedllvm/test/Transforms/LowerMatrixIntrinsics/multiply-i32.ll
The file was modifiedclang/test/CodeGen/arm-mve-intrinsics/cplusplus.cpp
The file was modifiedllvm/test/Transforms/VectorCombine/X86/extract-binop-inseltpoison.ll
The file was modifiedllvm/test/Transforms/LowerMatrixIntrinsics/bigger-expressions-double.ll
The file was modifiedclang/test/CodeGen/arm-mve-intrinsics/vqdmulltq.c
The file was modifiedllvm/test/Transforms/LowerMatrixIntrinsics/multiply-double-contraction-fmf.ll
The file was modifiedllvm/test/Transforms/LowerMatrixIntrinsics/multiply-float.ll
The file was modifiedclang/test/CodeGen/SystemZ/builtins-systemz-zvector2.c
The file was modifiedclang/test/CodeGen/arm-mve-intrinsics/vqrdmulhq.c
The file was modifiedllvm/test/Transforms/PhaseOrdering/X86/shuffle.ll
The file was modifiedclang/test/CodeGen/SystemZ/builtins-systemz-zvector-constrained.c
The file was modifiedllvm/test/Transforms/InstCombine/shuffle-select-narrow-inseltpoison.ll
The file was modifiedllvm/test/Transforms/LoopVectorize/X86/pr34438.ll
The file was modifiedllvm/test/Transforms/LoopVectorize/first-order-recurrence-complex.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/commutativity.ll
The file was modifiedclang/test/CodeGen/arm-mve-intrinsics/vsubq.c
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/jumbled_store_crash.ll
The file was modifiedllvm/test/Transforms/InstCombine/shuffle-select-narrow.ll
The file was modifiedllvm/test/Transforms/InstCombine/vec_shuffle-inseltpoison.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/jumbled-load-used-in-phi.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/reuse-extracts-in-wider-vect.ll
The file was modifiedclang/test/CodeGen/builtins-ppc-p10vector.c
The file was modifiedllvm/test/Transforms/LoopVectorize/X86/consecutive-ptr-uniforms.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/reorder_repeated_ops.ll
The file was modifiedllvm/test/Transforms/VectorCombine/X86/load-inseltpoison.ll
The file was modifiedllvm/test/Transforms/LoopVectorize/X86/cost-model-assert.ll
The file was modifiedllvm/test/Transforms/RewriteStatepointsForGC/scalar-base-vector.ll
The file was modifiedllvm/test/Transforms/PhaseOrdering/X86/scalarization.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/load-merge-inseltpoison.ll
The file was modifiedllvm/test/Transforms/LoopVectorize/ARM/tail-folding-not-allowed.ll
The file was modifiedclang/test/CodeGen/SystemZ/builtins-systemz-zvector2-constrained.c
The file was modifiedllvm/test/Transforms/LowerMatrixIntrinsics/const-gep.ll
The file was modifiedllvm/test/Transforms/LoopVectorize/dont-fold-tail-for-divisible-TC.ll
The file was modifiedllvm/test/Transforms/VectorCombine/X86/extract-cmp-binop.ll
The file was modifiedclang/test/CodeGen/arm-mve-intrinsics/vqsubq.c
The file was modifiedllvm/test/Transforms/LoopVectorize/loop-form.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/jumbled-load.ll
The file was modifiedllvm/test/Transforms/LowerMatrixIntrinsics/multiply-i32-row-major.ll
The file was modifiedllvm/test/Transforms/LoopVectorize/X86/interleaving.ll
The file was modifiedllvm/test/Transforms/InstCombine/X86/x86-vector-shifts.ll
The file was modifiedllvm/test/Transforms/VectorCombine/X86/extract-binop.ll
The file was modifiedllvm/test/Transforms/LoopVectorize/AArch64/arbitrary-induction-step.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/pr47623.ll
The file was modifiedllvm/include/llvm/IR/IRBuilder.h
The file was modifiedllvm/test/Transforms/LoopVectorize/induction-step.ll
The file was modifiedllvm/test/Transforms/LoopVectorize/optsize.ll
The file was modifiedclang/test/CodeGen/arm-mve-intrinsics/ternary.c
The file was modifiedllvm/test/Transforms/LoopVectorize/minmax_reduction.ll
The file was modifiedllvm/test/Transforms/LoopVectorize/if-pred-stores.ll
The file was modifiedllvm/test/Transforms/LoopVectorize/outer_loop_test1.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/PR40310.ll
The file was modifiedllvm/test/Transforms/InstCombine/X86/x86-vector-shifts-inseltpoison.ll
The file was modifiedllvm/test/Transforms/LoopVectorize/X86/invariant-load-gather.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/phi.ll
The file was modifiedclang/test/CodeGen/arm-mve-intrinsics/vhsubq.c
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/reduction_loads.ll
The file was modifiedclang/test/CodeGen/SystemZ/zvector.c
The file was modifiedllvm/test/Transforms/LoopVectorize/multiple-strides-vectorization.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/insert-element-build-vector.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/partail.ll
The file was modifiedllvm/test/Transforms/LoopVectorize/X86/optsize.ll
The file was modifiedllvm/test/Transforms/LowerMatrixIntrinsics/multiply-double-row-major.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/vectorize-reorder-reuse.ll
The file was modifiedclang/test/CodeGen/matrix-type-operators.c
The file was modifiedclang/test/CodeGen/arm-mve-intrinsics/vqdmullbq.c
The file was modifiedpolly/test/Isl/CodeGen/invariant_load_hoist_alignment.ll
The file was modifiedllvm/test/Transforms/LowerMatrixIntrinsics/multiply-fused-volatile.ll
The file was modifiedpolly/test/Isl/CodeGen/simple_vec_const.ll
The file was modifiedllvm/test/Transforms/LoopVectorize/pr39417-optsize-scevchecks.ll
The file was modifiedpolly/test/Isl/CodeGen/simple_vec_ptr_ptr_ty.ll
Commit f7f09e2b1c897f0b42be72939d0c97dcfd1577f7 by fraser
[RISCV] Fill out basic integer RVV ISel patterns

This complements the existing RVV ISel patterns for arithmetic, bitwise
and shifts with the remaining operations in those categories: sub, and,
xor, sra.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D93852
The file was addedllvm/test/CodeGen/RISCV/rvv/vsub-sdnode-rv64.ll
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
The file was addedllvm/test/CodeGen/RISCV/rvv/vsra-sdnode-rv32.ll
The file was addedllvm/test/CodeGen/RISCV/rvv/vxor-sdnode-rv32.ll
The file was addedllvm/test/CodeGen/RISCV/rvv/vxor-sdnode-rv64.ll
The file was addedllvm/test/CodeGen/RISCV/rvv/vand-sdnode-rv64.ll
The file was addedllvm/test/CodeGen/RISCV/rvv/vand-sdnode-rv32.ll
The file was addedllvm/test/CodeGen/RISCV/rvv/vsub-sdnode-rv32.ll
The file was addedllvm/test/CodeGen/RISCV/rvv/vrsub-sdnode-rv32.ll
The file was addedllvm/test/CodeGen/RISCV/rvv/vsra-sdnode-rv64.ll
The file was addedllvm/test/CodeGen/RISCV/rvv/vrsub-sdnode-rv64.ll
Commit 21a3a0225d84cd35227fc9d4d08234918a54f8d3 by spatel
[SLP] replace local reduction enum with RecurrenceKind; NFCI

I'm not sure if the SLP enum was created before the IVDescriptor
RecurrenceDescriptor / RecurrenceKind existed, but the code in
SLP is now redundant with that class, so it just makes things
more complicated to have both. We eventually call LoopUtils
createSimpleTargetReduction() to create reduction ops, so we
might as well standardize on those enum names.

There's still a question of whether we need to use TTI::ReductionFlags
vs. MinMaxRecurrenceKind, but that can be another clean-up step.

Another option would just be to flatten the enums in RecurrenceDescriptor
into a single enum. There isn't much benefit (smaller switches?) to
having a min/max subset.
The file was modifiedllvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
Commit df7ddeea668af7b25ee01f282fd8e6b388155103 by stellaraccident
[mlir][python] Add FlatSymbolRef attribute.

Reviewed By: mehdi_amini

Differential Revision: https://reviews.llvm.org/D93909
The file was modifiedmlir/lib/Bindings/Python/IRModules.cpp
The file was modifiedmlir/test/Bindings/Python/ir_attributes.py