UnstableChanges

Summary

  1. [RISCV] Match vmslt(u).vx intrinsics with a small immediate to vmsle(u).vx. (details)
  2. [SLP] delete unused pairwise reduction option (details)
  3. [RISCV] Don't print zext.b alias. (details)
  4. [NFC] Fix -Wrange-loop-analysis warnings. (details)
  5. [LoopNest] Allow empty basic blocks without loops (details)
  6. [mlir] Gen removeAttr methods with tablegen (details)
  7. [RISCV] Don't parse 'vmsltu.vi v0, v1, 0' as 'vmsleu.vi v0, v1, -1' (details)
  8. [NFC] Rename registerAliasAnalyses -> registerDefaultAliasAnalyses (details)
  9. [clang][cli] Specify correct integer width for -fbuild-session-timestamp (details)
  10. [WebAssembly] Prototype prefetch instructions (details)
  11. [Coverage] Fix test failures from commit rG9f2967bcfe2f (details)
  12. [RISCV] Move shift ComplexPatterns and custom isel to PatFrags with predicates (details)
  13. [LoopDeletion] Allows deletion of possibly infinite side-effect free loops (details)
  14. [LoopNest] Remove unused include. (details)
  15. [Hexagon] Silence unused function warning with gcc10, NFC (details)
  16. [SLP] reduce code duplication; NFC (details)
  17. [SLP] use reduction kind's opcode for cost model queries; NFC (details)
  18. [DAGCombiner] Don't speculatively create an all ones constant in visitREM that might not be used. (details)
  19. [Inliner] Compute the full cost for the cost benefit analsysis (details)
  20. [Coverage] Fix Profile test failures from commit rG9f2967bcfe2f (details)
  21. [android] Fix some tests for AOSP-master devices. (details)
  22. [NFC] Removed unused prefixes in CodeGen/AMDGPU/GlobalISel (details)
  23. scudo: Fix compilation for non-Linux aarch64 (details)
  24. [FuncAttrs] Infer noreturn (details)
  25. [ASTMatchers] Fix child traversal over range-for loops (details)
  26. [NFC] Removed unused prefixes in CodeGen/AMDGPU (details)
  27. [NFC] Removed unused prefixes in test/CodeGen/AMDGPU (details)
  28. [SLP] reduce code for finding reduction costs; NFC (details)
  29. AMDGPU: Annotate amdgpu.noclobber for global loads only (details)
  30. [SimplifyCFG] simplifyUnreachable(): switch to non-permissive DomTree updates (details)
  31. [NFC][SimplifyCFG] Add a test with same-destination condidional branch (details)
  32. [SimplifyCFG] simplifyUnreachable(): fix handling of degenerate same-destination conditional branch (details)
  33. [SimplifyCFG] FoldValueComparisonIntoPredecessors(): switch to non-permissive DomTree updates (details)
  34. [SimplifyCFG] FoldValueComparisonIntoPredecessors(): deal with each predecessor only once (details)
  35. [NFC][SimplifyCFG] SwitchToLookupTable(): pull out SI->getParent() into a variable (details)
  36. [SimplifyCFG] SwitchToLookupTable(): switch to non-permissive DomTree updates (details)
  37. [NFC][SimplifyCFG] Add a test where SimplifyEqualityComparisonWithOnlyPredecessor() deletes existing edge (details)
  38. [SimplifyCFG] SimplifyEqualityComparisonWithOnlyPredecessor(): really don't delete DomTree edges multiple times (details)
Commit c707716c049cd46bd89da102cf9444462487b490 by craig.topper
[RISCV] Match vmslt(u).vx intrinsics with a small immediate to vmsle(u).vx.

There are vmsle(u).vx and vmsle(u).vi instructions, but there is
only vmslt(u).vx and no vmslt(u).vi. vmslt(u).vi can be emulated
for some immediates by decrementing the immediate and using vmsle(u).vi.

To avoid the user needing to know about this, this patch does this
conversion.

The assembler does the same thing for vmslt(u).vi and vmsge(u).vi
pseudoinstructions. There is no vmsge(u).vx intrinsic or
instruction so this patch is limited to vmslt(u).

Reviewed By: frasercrmck

Differential Revision: https://reviews.llvm.org/D94070
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmsltu-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmsltu-rv32.ll
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmslt-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmslt-rv64.ll
Commit 3b8b2c7da2efb88d9f13e911e383af430ab463ef by spatel
[SLP] delete unused pairwise reduction option

SLP tries to model 2 forms of vector reductions: pairwise and splitting.
From the cost model code comments, those are defined using an example as:

  /// Pairwise:
  ///  (v0, v1, v2, v3)
  ///  ((v0+v1), (v2+v3), undef, undef)
  /// Split:
  ///  (v0, v1, v2, v3)
  ///  ((v0+v2), (v1+v3), undef, undef)

I don't know the full history of this functionality, but it was partly
added back in D29402. There are apparently no users at this point (no
regression tests change). X86 might have managed to work-around the need
for this through cost model and codegen improvements.

Removing this code makes it easier to continue the work that was started
in D87416 / D88193. The alternative -- if there is some target that is
silently using this option -- is to move this logic into LoopUtils. We
have related/duplicate functionality there via llvm::createTargetReduction().

Differential Revision: https://reviews.llvm.org/D93860
The file was modifiedllvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
Commit 249d7de1190f50178181d2477aa661cd252e294c by craig.topper
[RISCV] Don't print zext.b alias.

This alias for andi x, 255 was recently added to the spec. If we
print it, code we output can't be compiled with -fno-integrated-as
unless the GNU assembler is also a version that supports alias.

Reviewed By: lenary

Differential Revision: https://reviews.llvm.org/D93826
The file was modifiedllvm/test/MC/RISCV/rv32i-aliases-valid.s
The file was modifiedllvm/test/MC/RISCV/rv32b-aliases-valid.s
The file was modifiedllvm/test/CodeGen/RISCV/atomic-rmw.ll
The file was modifiedllvm/test/CodeGen/RISCV/bswap-ctlz-cttz-ctpop.ll
The file was modifiedllvm/test/MC/RISCV/rv64b-aliases-valid.s
The file was modifiedllvm/test/MC/RISCV/rv64i-aliases-valid.s
The file was modifiedllvm/test/CodeGen/RISCV/rv32Zbbp.ll
The file was modifiedllvm/test/CodeGen/RISCV/atomic-cmpxchg.ll
The file was modifiedllvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-ilp32d-common.ll
The file was modifiedllvm/test/CodeGen/RISCV/calling-conv-lp64-lp64f-lp64d-common.ll
The file was modifiedllvm/test/CodeGen/RISCV/alu8.ll
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfo.td
The file was modifiedllvm/test/CodeGen/RISCV/rv64Zbbp.ll
The file was modifiedllvm/test/CodeGen/RISCV/calling-conv-sext-zext.ll
The file was modifiedllvm/test/CodeGen/RISCV/sext-zext-trunc.ll
Commit 7afd5cfbc757b004cba99d234df4e76b06956b2d by joker.eph
[NFC] Fix -Wrange-loop-analysis warnings.

Remove unnecessary `&` from loop variables.

Fix warnings: "loop variable is always a copy because the range does not
return a reference".

```
[240/2862] Building CXX object tools/mlir/tools/mlir-tblgen/CMakeFiles/mlir-tblgen.dir/TypeDefGen.cpp.o
llvm-project/mlir/tools/mlir-tblgen/TypeDefGen.cpp:50:25: warning: loop variable 'typeDef' is always a copy because the range of type 'llvm::iterator_range<llvm::mapped_iterator<std::__1::__wrap_iter<llvm::Record **>, (lambda at llvm-project/mlir/tools/mlir-tblgen/TypeDefGen.cpp:40:16), mlir::tblgen::TypeDef> >' does not return a reference [-Wrange-loop-analysis]
    for (const TypeDef &typeDef : defs)
                        ^
llvm-project/mlir/tools/mlir-tblgen/TypeDefGen.cpp:50:10: note: use non-reference type 'mlir::tblgen::TypeDef'
    for (const TypeDef &typeDef : defs)
         ^~~~~~~~~~~~~~~~~~~~~~~~
llvm-project/mlir/tools/mlir-tblgen/TypeDefGen.cpp:64:23: warning: loop variable 'typeDef' is always a copy because the range of type 'llvm::iterator_range<llvm::mapped_iterator<std::__1::__wrap_iter<llvm::Record **>, (lambda at llvm-project/mlir/tools/mlir-tblgen/TypeDefGen.cpp:40:16), mlir::tblgen::TypeDef> >' does not return a reference [-Wrange-loop-analysis]
  for (const TypeDef &typeDef : defs)
                      ^
llvm-project/mlir/tools/mlir-tblgen/TypeDefGen.cpp:64:8: note: use non-reference type 'mlir::tblgen::TypeDef'
  for (const TypeDef &typeDef : defs)
       ^~~~~~~~~~~~~~~~~~~~~~~~
2 warnings generated.

[1934/2862] Building CXX object tools...Files/toyc-ch4.dir/mlir/MLIRGen.cpp.o
llvm-project/mlir/examples/toy/Ch4/mlir/MLIRGen.cpp:139:22: warning: loop variable 'name_value' is always a copy because the range of type 'detail::zippy<detail::zip_shortest, ArrayRef<unique_ptr<VariableExprAST, default_delete<VariableExprAST> > > &, MutableArrayRef<BlockArgument> >' does not return a reference [-Wrange-loop-analysis]
    for (const auto &name_value :
                     ^
llvm-project/mlir/examples/toy/Ch4/mlir/MLIRGen.cpp:139:10: note: use non-reference type 'std::__1::tuple<const std::__1::unique_ptr<toy::VariableExprAST, std::__1::default_delete<toy::VariableExprAST> > &, mlir::BlockArgument &>'
    for (const auto &name_value :
         ^~~~~~~~~~~~~~~~~~~~~~~~
1 warning generated.

[1940/2862] Building CXX object tools...Files/toyc-ch5.dir/mlir/MLIRGen.cpp.o
llvm-project/mlir/examples/toy/Ch5/mlir/MLIRGen.cpp:139:22: warning: loop variable 'name_value' is always a copy because the range of type 'detail::zippy<detail::zip_shortest, ArrayRef<unique_ptr<VariableExprAST, default_delete<VariableExprAST> > > &, MutableArrayRef<BlockArgument> >' does not return a reference [-Wrange-loop-analysis]
    for (const auto &name_value :
                     ^
llvm-project/mlir/examples/toy/Ch5/mlir/MLIRGen.cpp:139:10: note: use non-reference type 'std::__1::tuple<const std::__1::unique_ptr<toy::VariableExprAST, std::__1::default_delete<toy::VariableExprAST> > &, mlir::BlockArgument &>'
    for (const auto &name_value :
         ^~~~~~~~~~~~~~~~~~~~~~~~
1 warning generated.
```

Reviewed By: jpienaar

Differential Revision: https://reviews.llvm.org/D94003
The file was modifiedmlir/examples/toy/Ch5/mlir/MLIRGen.cpp
The file was modifiedmlir/examples/toy/Ch3/mlir/MLIRGen.cpp
The file was modifiedmlir/examples/toy/Ch6/mlir/MLIRGen.cpp
The file was modifiedmlir/examples/toy/Ch7/mlir/MLIRGen.cpp
The file was modifiedmlir/examples/toy/Ch7/mlir/Dialect.cpp
The file was modifiedmlir/tools/mlir-tblgen/TypeDefGen.cpp
The file was modifiedmlir/examples/toy/Ch2/mlir/MLIRGen.cpp
The file was modifiedmlir/examples/toy/Ch4/mlir/MLIRGen.cpp
Commit 601636de98061b53242b598fc2354905c8efbfb8 by whitneyt
[LoopNest] Allow empty basic blocks without loops

Addressed Florian's post commit review comments:
1. included STLExtras.h
2. changed std::all_of to llvm::all_of

Differential Revision: https://reviews.llvm.org/D93665
The file was modifiedllvm/include/llvm/Analysis/LoopNestAnalysis.h
Commit 86d68e288585964546d6382ecf71dcce10d018b7 by joker.eph
[mlir] Gen removeAttr methods with tablegen

If an operation defines an optional attribute (OptionalAttr or
UnitAttr), transformations may wish to remove these attributes while
maintaining invariants established by the operation. Currently, the only
way to do this is by calling `Operation::removeAttr("attrName")`, which
requires developers to know the exact name of the attribute used by
table-gen. Furthermore, if the attribute name changes, this won't be
detected at compile time. Instead, `removeAttr` would return an empty
attribute and no errors would be raised, unless the caller checks for
the returned value.

This patch adds table gen support for generating `remove<AttrName>Attr`
methods for OptionalAttributes defined by operations.

Implementation choice: to preserve camelCase for the method's name, the
first character of an attribute called `myAttr` is changed to upper case
in order to preserve the coding style, so the final method would be
called `removeMyAttr`.

Reviewed By: mehdi_amini

Differential Revision: https://reviews.llvm.org/D93903
The file was modifiedmlir/test/mlir-tblgen/op-decl.td
The file was modifiedmlir/test/mlir-tblgen/op-attribute.td
The file was modifiedmlir/tools/mlir-tblgen/OpDefinitionsGen.cpp
Commit 210bc3dc0eb3550fd99158e5747619ad9e91c548 by craig.topper
[RISCV] Don't parse 'vmsltu.vi v0, v1, 0' as 'vmsleu.vi v0, v1, -1'

vmsltu.vi v0, v1, 0 is always false there is no unsigned number
less than 0. vmsleu.vi v0, v1, -1 on the other hand is always true
since -1 will be considered unsigned max and all numbers are <=
unsigned max.

A similar problem exists for vmsgeu.vi v0, v1, 0 which is always true,
but becomes vmsgtu.vi v0, v1, -1 which is always false.

To match the GNU assembler we'll emit vmsne.vv and vmseq.vv with
the same register for these cases instead.

I'm using AsmParserOnly pseudo instructions here because we can't
match an explicit immediate in an InstAlias. And we can't use a
AsmOperand for the zero because the output we want doesn't use an
immediate so there's nowhere to name the AsmOperand we want to use.

To keep the implementations similar I'm also handling signed with
pseudo instructions even though they don't have this issue. This
way we can avoid the special renderMethod that decremented by 1 so
the immediate we see for the pseudo instruction in processInstruction
is 0 and not -1. Another option might have been to have a different
simm5_plus1 operand for the unsigned case or just live with the
immediate being pre-decremented. I felt this way was clearer, but I'm
open to other opinions.

Reviewed By: frasercrmck

Differential Revision: https://reviews.llvm.org/D94035
The file was modifiedllvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfoV.td
The file was modifiedllvm/test/MC/RISCV/rvv/compare.s
Commit 28a326eba0a9c367ab6a2d23ca0ae4fb8ab2b536 by aeubanks
[NFC] Rename registerAliasAnalyses -> registerDefaultAliasAnalyses

To clarify that this only affects the "default" AA.

Reviewed By: ychen

Differential Revision: https://reviews.llvm.org/D93980
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h
The file was modifiedllvm/include/llvm/Target/TargetMachine.h
The file was modifiedllvm/include/llvm/Passes/PassBuilder.h
The file was modifiedllvm/lib/Passes/PassBuilder.cpp
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
Commit f111cf992df4ec00acfdd026eac12b36c3831999 by Jan Svoboda
[clang][cli] Specify correct integer width for -fbuild-session-timestamp

This fixes an issue where large integer values were rejected as invalid.

Reviewed By: arphaman

Differential Revision: https://reviews.llvm.org/D94101
The file was modifiedclang/include/clang/Driver/Options.td
The file was modifiedclang/unittests/Frontend/CompilerInvocationTest.cpp
Commit 497026c90233e82ffd3ce2438c5f9567be6dabe7 by tlively
[WebAssembly] Prototype prefetch instructions

As proposed in https://github.com/WebAssembly/simd/pull/352 and using the
opcodes used in the V8 prototype:
https://chromium-review.googlesource.com/c/v8/v8/+/2543167. These instructions
are only usable via intrinsics and clang builtins to make them opt-in while they
are being benchmarked.

Differential Revision: https://reviews.llvm.org/D93883
The file was modifiedllvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.h
The file was modifiedllvm/include/llvm/IR/IntrinsicsWebAssembly.td
The file was addedllvm/test/CodeGen/WebAssembly/simd-prefetch-offset.ll
The file was modifiedclang/test/CodeGen/builtins-wasm.c
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
The file was modifiedllvm/test/MC/WebAssembly/simd-encodings.s
The file was modifiedllvm/lib/Target/WebAssembly/AsmParser/WebAssemblyAsmParser.cpp
The file was modifiedclang/include/clang/Basic/BuiltinsWebAssembly.def
The file was modifiedclang/lib/CodeGen/CGBuiltin.cpp
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
Commit 16f3401eae4310c95163269c41d9b45261f0c7c3 by a-phipps
[Coverage] Fix test failures from commit rG9f2967bcfe2f

Fix test failures with Branch Coverage tests from commit rG9f2967bcfe2f
that failed build on builder clang-x64-windows-msvc while building llvm:
    http://lab.llvm.org:8011/#builders/123/builds/2155
The file was modifiedclang/test/CoverageMapping/branch-constfolded.cpp
The file was modifiedclang/test/CoverageMapping/branch-mincounters.cpp
The file was modifiedclang/test/CoverageMapping/branch-templates.cpp
The file was modifiedclang/test/Profile/branch-logical-mixed.cpp
The file was modifiedclang/test/Profile/branch-profdup.cpp
The file was modifiedclang/test/CoverageMapping/branch-macros.cpp
Commit 7b5a0e2f88eedc1123f4027552940bdf1ab6c03e by craig.topper
[RISCV] Move shift ComplexPatterns and custom isel to PatFrags with predicates

ComplexPatterns are kind of weird, they don't call any of the predicates on their operands. And their "complexity" used for tablegen ordering purposes in the matcher table is hand specified.

This started as an attempt to just use sext_inreg + SLOIPat to implement SLOIW just to have one less Select function. The matching for the or+shl is the same as long as you know the immediate is less than 32 for SLOIW. But that didn't work out because using uimm5 with SLOIPat didn't do anything if it was a ComplexPattern.

I realized I could just use a PatFrag with the opcodes I wanted to match and an immediate predicate would then evaluate correctly. This also computes the complexity just like any other pattern does. Then I just needed to check the constraints on the immediates in the predicate. Conveniently the predicate is evaluated after the fragment has been matched. So the structure has already been checked, we just need to find the constants.

I'll note that this is unusual, I didn't find any other targets looking through operands in PatFrag predicate. There is a PredicateCodeUsesOperands feature that can be used to collect the operands into an array that is used by AMDGPU/VOP3Instructions.td. I believe that feature exists to handle commuted matching, but since the nodes here use constants, they aren't ever commuted

Differential Revision: https://reviews.llvm.org/D91901
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfoB.td
The file was modifiedllvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfo.td
The file was modifiedllvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
Commit f88a7975210fc995197af4b393e3bb5030e97a5c by atmndp
[LoopDeletion] Allows deletion of possibly infinite side-effect free loops

From C11 and C++11 onwards, a forward-progress requirement has been
introduced for both languages. In the case of C, loops with non-constant
conditionals that do not have any observable side-effects (as defined by
6.8.5p6) can be assumed by the implementation to terminate, and in the
case of C++, this assumption extends to all functions. The clang
frontend will emit the `mustprogress` function attribute for C++
functions (D86233, D85393, D86841) and emit the loop metadata
`llvm.loop.mustprogress` for every loop in C11 or later that has a
non-constant conditional.

This patch modifies LoopDeletion so that only loops with
the `llvm.loop.mustprogress` metadata or loops contained in functions
that are required to make progress (`mustprogress` or `willreturn`) are
checked for observable side-effects. If these loops do not have an
observable side-effect, then we delete them.

Loops without observable side-effects that do not satisfy the above
conditions will not be deleted.

Reviewed By: jdoerfert

Differential Revision: https://reviews.llvm.org/D86844
The file was modifiedclang/test/Misc/loop-opt-setup.c
The file was modifiedllvm/include/llvm/Transforms/Utils/LoopUtils.h
The file was modifiedllvm/lib/Transforms/Scalar/LoopDeletion.cpp
The file was addedllvm/test/Transforms/LoopDeletion/mustprogress.ll
The file was modifiedllvm/test/Transforms/LoopDeletion/no-exit-blocks.ll
The file was modifiedllvm/lib/Transforms/Utils/LoopUtils.cpp
Commit 314ccc00139a7f382db7b598dcd94883b366b7de by whitneyt
[LoopNest] Remove unused include.

Differential Revision: https://reviews.llvm.org/D93665
The file was modifiedllvm/lib/Analysis/LoopNestAnalysis.cpp
Commit ee11bf316f6be9dba29026b332fcde1dc3be4f9d by kparzysz
[Hexagon] Silence unused function warning with gcc10, NFC
The file was modifiedllvm/lib/Target/Hexagon/HexagonVectorCombine.cpp
Commit d4a999b453a4d3cfeee02f00f4900327fc7fcede by spatel
[SLP] reduce code duplication; NFC
The file was modifiedllvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
Commit 5a1d31a28490e85de440b55e2e257b61d32e85b9 by spatel
[SLP] use reduction kind's opcode for cost model queries; NFC

This should be no-functional-change because the reduction kind
opcodes are 1-for-1 mappings to the instructions we are matching
as reductions. But we want to remove the need for the
`OperationData` opcode field because that does not work when
we start matching intrinsics (eg, maxnum) as reduction candidates.
The file was modifiedllvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
Commit 4ef91f5871a3c38bb2324f89b47a2a845e8a33fd by craig.topper
[DAGCombiner] Don't speculatively create an all ones constant in visitREM that might not be used.

This looks to have been done to save some duplicated code under
two different if statements, but it ends up being harmful to D94073.
This speculative constant can be called on a scalable vector type
with i64 element size when i64 scalars aren't legal. The code tries
and fails to find a vector type with i32 elements that it can use.

So only create the node when we know it will be used.
The file was modifiedllvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Commit 65cd3cbb3fc9ee440234a5adbfea6cbe4834f3d3 by kazu
[Inliner] Compute the full cost for the cost benefit analsysis

This patch teaches the inliner to compute the full cost for a call
site where the newly introduced cost benefit analysis is enabled.

Note that the cost benefit analysis requires the full cost to be
computed.  However, without this patch or the -inline-cost-full
option, the early termination logic would kick in when the cost
exceeds the threshold, so we don't get to perform the cost benefit
analysis.  For this reason, we would need to specify four clang
options:

  -mllvm -inline-cost-full
  -mllvm -inline-enable-cost-benefit-analysis

This patch eliminates the need to specify -inline-cost-full.

Differential Revision: https://reviews.llvm.org/D93658
The file was modifiedllvm/lib/Analysis/InlineCost.cpp
Commit 216894211713bbb1e8beb249f2b008c11a9d8c2c by a-phipps
[Coverage] Fix Profile test failures from commit rG9f2967bcfe2f

Fix test failures with Branch Coverage tests from commit rG9f2967bcfe2f
that failed build on builder clang-x64-windows-msvc while building llvm:
    http://lab.llvm.org:8011/#/builders/123/builds/2162
The file was modifiedclang/test/Profile/branch-logical-mixed.cpp
Commit 1f8031cd74887025a5de1e7129718186369db769 by 31459023+hctim
[android] Fix some tests for AOSP-master devices.

Some tests are broken at API level 30 on AOSP-master devices. When we
change the buildbuit to API level 30, the following tests get enabled.
They're currently broken due to various issues, and so fix up those
issues.

Reviewed By: oontvoo, eugenis

Differential Revision: https://reviews.llvm.org/D94100
The file was modifiedcompiler-rt/test/lsan/TestCases/stale_stack_leak.cpp
The file was modifiedcompiler-rt/test/cfi/cross-dso/target_out_of_bounds.cpp
The file was modifiedcompiler-rt/test/lsan/TestCases/Linux/use_tls_dynamic.cpp
Commit a9543469d54e3dfa1c6b4e9d498b55bca947d51e by mtrofin
[NFC] Removed unused prefixes in CodeGen/AMDGPU/GlobalISel

Differential Revision: https://reviews.llvm.org/D94099
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/dynamic-alloca-uniform.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-lshr.s16.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/lds-global-non-entry-func.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zextload-flat.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.udot4.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ashr.s16.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.workgroup.id.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-fixed-function-abi-vgpr-args.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ds.gws.sema.v.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/frem.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/fmed3.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sdot4.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/load-local.96.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.kernarg.segment.ptr.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.udot2.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/zextload.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ds.gws.sema.release.all.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/store-local.128.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i8.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-shl.s16.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.fdot2.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.workitem.id.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/lds-misaligned-bug.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i16.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.fmul.legacy.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/load-local.128.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/load-unaligned.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sdot8.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.scale.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/store-local.96.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.set.inactive.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.fmas.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.udot8.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ds.gws.sema.br.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sdot2.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/smrd.ll
Commit 90b8fd6136078127f5b792ec64745e5ae54a12a4 by mcgrathr
scudo: Fix compilation for non-Linux aarch64

Linux-specific aarch64 code was deconditionalized in commit
dfa40840e0e2fa094c5d3f441affe0785cdc8d09.  This broke builds for
non-Linux aarch64 platforms.

Reviewed By: cryptoad

Differential Revision: https://reviews.llvm.org/D94108
The file was modifiedcompiler-rt/lib/scudo/standalone/memtag.h
Commit 8cf1cc578d3288f5b9cfe1584e524f8b1517dc97 by aeubanks
[FuncAttrs] Infer noreturn

A function is noreturn if all blocks terminating with a ReturnInst
contain a call to a noreturn function. Skip looking at naked functions
since there may be asm that returns.

This can be further refined in the future by checking unreachable blocks
and taking into account recursion. It looks like the attributor pass
does this, but that is not yet enabled by default.

This seems to help with code size under the new PM since PruneEH does
not run under the new PM, missing opportunities to mark some functions
noreturn, which in turn doesn't allow simplifycfg to clean up dead code.
https://bugs.llvm.org/show_bug.cgi?id=46858.

Reviewed By: rnk

Differential Revision: https://reviews.llvm.org/D93946
The file was addedllvm/test/Transforms/FunctionAttrs/noreturn.ll
The file was modifiedllvm/test/Transforms/PruneEH/simplenoreturntest.ll
The file was modifiedllvm/lib/Transforms/IPO/FunctionAttrs.cpp
Commit 16c6e9c58e9ae50a775945e6b407f1891f353d2f by steveire
[ASTMatchers] Fix child traversal over range-for loops

Differential Revision: https://reviews.llvm.org/D94031
The file was modifiedclang/lib/ASTMatchers/ASTMatchFinder.cpp
The file was modifiedclang/unittests/ASTMatchers/ASTMatchersTraversalTest.cpp
Commit bec987ea6727f18e1512636804367c3695f51b6f by mtrofin
[NFC] Removed unused prefixes in CodeGen/AMDGPU

This is part of the pertinent tests, more to follow in subsequent
patches.

Differential Revision: https://reviews.llvm.org/D94114
The file was modifiedllvm/test/CodeGen/AMDGPU/amdgcn.private-memory.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/amdpal-psenable.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/amdpal-cs.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/amdpal-msgpack-vs.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/anyext.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/amdpal-msgpack-ps.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/amdpal-msgpack-denormal.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/amdpal-vs.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/amdpal-es.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/atomic_cmp_swap_local.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/amdpal-msgpack-ls.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/amdpal-msgpack-gs.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/amdgpu.work-item-intrinsics.deprecated.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/amdpal-ls.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/amdpal-msgpack-hs.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/amdpal-msgpack-psenable.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/amdpal-msgpack-ieee.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/amdpal-msgpack-dx10-clamp.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/amdpal-gs.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/amdpal-msgpack-cs.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/andorn2.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/amdpal-msgpack-default.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/amdpal-msgpack-es.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/amdpal-ps.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/attr-amdgpu-num-sgpr.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/amdpal-hs.ll
Commit 1ebe86adf52cbddc03f535554b16585b2947b32c by mtrofin
[NFC] Removed unused prefixes in test/CodeGen/AMDGPU

More patches to follow.

Differential Revision: https://reviews.llvm.org/D94121
The file was modifiedllvm/test/CodeGen/AMDGPU/bfm.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/ctlz.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/bitreverse.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/bswap.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/ds-sub-offset.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/break-smem-soft-clauses.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/drop-mem-operand-move-smrd.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/byval-frame-setup.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/break-vmem-soft-clauses.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/call-encoding.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/copy-illegal-type.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/diverge-extra-formal-args.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/ds_read2.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/callee-frame-setup.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/commute-compares.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/cgp-addressing-modes-flat.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/ds_read2_superreg.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/ds_write2.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/code-object-v3.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/debug.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/commute-shifts.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/diverge-interp-mov-lower.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/clamp.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/concat_vectors.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/cube.ll
Commit 6a03f8ab629b34a2425764caaa46dbfcf3d8e1ef by spatel
[SLP] reduce code for finding reduction costs; NFC

We can get both (vector/scalar) costs in a single switch
instead of sequentially.
The file was modifiedllvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
Commit cb5b52a06eeb7cc868944bb08f71fffe13f33412 by changpeng.fang
AMDGPU: Annotate amdgpu.noclobber for global loads only

Summary:
  This is to avoid unnecessary analysis since amdgpu.noclobber is only used for globals.

Reviewers:
  arsenm

Fixes:
   SWDEV-239161

Differential Revision:
  https://reviews.llvm.org/D94107
The file was modifiedllvm/test/CodeGen/AMDGPU/store-clobbers-load.ll
The file was addedllvm/test/CodeGen/AMDGPU/annotate-noclobber.ll
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUAnnotateUniformValues.cpp
Commit f98535686e3c1fa76986337639df1636282692c9 by lebedev.ri
[SimplifyCFG] simplifyUnreachable(): switch to non-permissive DomTree updates

... which requires not removing a DomTree edge if the switch's default
still points at that destination, because it can't be removed;
... and not processing the same predecessor more than once.
The file was modifiedllvm/lib/Transforms/Utils/SimplifyCFG.cpp
Commit 3460719f583583e6990ec5c1b2a718cc01797bf7 by lebedev.ri
[NFC][SimplifyCFG] Add a test with same-destination condidional branch

Reported by Mikael Holmén as post-commit feedback on
https://reviews.llvm.org/rG2d07414ee5f74a09fb89723b4a9bb0818bdc2e18#968162
The file was modifiedllvm/lib/Transforms/Utils/SimplifyCFG.cpp
The file was addedllvm/test/Transforms/SimplifyCFG/simplifyUnreachable-degenerate-conditional-branch-with-matching-destinations.ll
Commit 29ca7d5a1ad968c371124b8d82edd8d91eee7b4f by lebedev.ri
[SimplifyCFG] simplifyUnreachable(): fix handling of degenerate same-destination conditional branch

One would hope that it would have been already canonicalized into an
unconditional branch, but that isn't really guaranteed to happen
with SimplifyCFG's visitation order.
The file was modifiedllvm/lib/Transforms/Utils/SimplifyCFG.cpp
The file was modifiedllvm/test/Transforms/SimplifyCFG/simplifyUnreachable-degenerate-conditional-branch-with-matching-destinations.ll
Commit fc96cb2dad6b8293124f12d00fb55ff75c2ebe71 by lebedev.ri
[SimplifyCFG] FoldValueComparisonIntoPredecessors(): switch to non-permissive DomTree updates

... which requires not adding a DomTree edge that we just added.
The file was modifiedllvm/lib/Transforms/Utils/SimplifyCFG.cpp
Commit d15d81ce15e086208f30d99ce2257a75401dc12c by lebedev.ri
[SimplifyCFG] FoldValueComparisonIntoPredecessors(): deal with each predecessor only once

If the predecessor is a switch, and BB is not the default destination,
multiple cases could have the same destination. and it doesn't
make sense to re-process the predecessor, because we won't make any changes,
once is enough.

I'm not sure this can be really tested, other than via the assertion
being added here, which fires without the fix.
The file was modifiedllvm/lib/Transforms/Utils/SimplifyCFG.cpp
Commit fa5447aa3fec313bfd8ec31b7c66d390a5589b94 by lebedev.ri
[NFC][SimplifyCFG] SwitchToLookupTable(): pull out SI->getParent() into a variable
The file was modifiedllvm/lib/Transforms/Utils/SimplifyCFG.cpp
Commit 2b437fcd479befb96bd61e71c4de8143bd861a48 by lebedev.ri
[SimplifyCFG] SwitchToLookupTable(): switch to non-permissive DomTree updates

... which requires not deleting a DomTree edge that we just deleted.
The file was modifiedllvm/lib/Transforms/Utils/SimplifyCFG.cpp
Commit 0a87e53fc40ffd644139cdd210e7c382dbe329c8 by lebedev.ri
[NFC][SimplifyCFG] Add a test where SimplifyEqualityComparisonWithOnlyPredecessor() deletes existing edge
The file was addedllvm/test/Transforms/SimplifyCFG/SimplifyEqualityComparisonWithOnlyPredecessor-domtree-preservation-edgecase.ll
Commit a14945c1db614261a6f8d5d199e246d78f51e977 by lebedev.ri
[SimplifyCFG] SimplifyEqualityComparisonWithOnlyPredecessor(): really don't delete DomTree edges multiple times
The file was modifiedllvm/lib/Transforms/Utils/SimplifyCFG.cpp
The file was modifiedllvm/test/Transforms/SimplifyCFG/SimplifyEqualityComparisonWithOnlyPredecessor-domtree-preservation-edgecase.ll