1. [X86] Add scalar/vector test coverage for D93599 (details)
  2. [libc] remove modulo from CircularArrayRef iterator (details)
  3. [libc] Align src buffer instead of dst buffer (details)
  4. [AArch64] Add BRB IALL and BRB INJ instructions (details)
  5. Reapply multiple "[clang][cli]" patches (details)
  6. [Hexagon] Regenerate zext-v4i1.ll tests (details)
  7. [OpenCL][NFC] Improve OpenCL test file naming (details)
  8. [ProfileData] Pass Twine by const reference instead of by value. (details)
  9. [MIPS] MipsAsmParser - Pass Twine by const reference instead of by value. NFCI. (details)
  10. [TableGen] RegisterBankEmitter - Pass Twine by const reference instead of by value. NFCI. (details)
  11. [MLIR][SPIRV] Add `UnsignedOp` trait. (details)
  12. [lldb] Simplify some lldb-server tests (details)
  13. [LoopDeletion] Also consider loops with subloops for deletion. (details)
  14. [Driver][MachineOutliner] Support outlining option with LTO (details)
  15. Fix MaterializeTemporaryExpr's type when its an incomplete array. (details)
  16. [mlir][spirv] Update pass docs (details)
  17. [Hexagon] Wrap functions only used in asserts in ifndef NDEBUG (details)
  18. [X86] Add icmp ne/eq (srl (ctlz x), log2(bw)) test coverage. (details)
  19. Remove some unused <vector> includes. NFCI. (details)
  20. [AArch64] Rearrange mul(dup(sext/zext)) to mul(sext/zext(dup)) (details)
  21. [TargetLowering] Add icmp ne/eq (srl (ctlz x), log2(bw)) vector support. (details)
  22. [flang][driver] Add support for `-D`, `-U` (details)
  23. AMDGPU: Explicitly use SelectionDAG in legacy intrinsic tests (details)
  24. AMDGPU/GlobalISel: Add baseline IR tests for fdiv (details)
Commit dfcb872c3e82c821bb32a2dd53ab73314d38ce38 by llvm-dev
[X86] Add scalar/vector test coverage for D93599

This expands the test coverage beyond just the boolvector/movmsk concat pattern
The file was addedllvm/test/CodeGen/X86/cmp-concat.ll
Commit 223a6f94c59c00733763bacc43f5b9458b4cc6f4 by gchatelet
[libc] remove modulo from CircularArrayRef iterator
The file was modifiedlibc/benchmarks/LibcBenchmark.h
Commit aa9db51ef69f36775e9babd2f4b23142967784ee by gchatelet
[libc] Align src buffer instead of dst buffer

We used to align destination buffer instead of source buffer for the loop of block copy.
This is a mistake.

Differential Revision: https://reviews.llvm.org/D93457
The file was modifiedlibc/test/src/string/memory_utils/memcpy_utils_test.cpp
The file was modifiedlibc/src/string/memory_utils/memcpy_utils.h
Commit 643e3c90761f30194a76671065d221d3cb71a199 by tomas.matheson
[AArch64] Add BRB IALL and BRB INJ instructions

BRB IALL: Invalidate the Branch Record Buffer
BRB INJ: Branch Record Injection into the Branch Record Buffer

Parser changes based on work by Simon Tatham.

These are two-word mnemonics. The assembly parser works by special-casing
the mnemonic in order to parse the second word as a plain identifier token.

Reviewed by: MarkMurrayARM

Differential Revision: https://reviews.llvm.org/D93899
The file was modifiedllvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
The file was modifiedllvm/test/MC/AArch64/brbe.s
The file was modifiedllvm/lib/Target/AArch64/AArch64InstrInfo.td
Commit ce8c59e6af487f0b8786ae921aa926341f0ae04f by Jan Svoboda
Reapply multiple "[clang][cli]" patches

This reverts 7ad666798f12 and 1876a2914fe0 that reverted:

741978d727a4 [clang][cli] Port CodeGen option flags to new option parsing system
383778e2171b [clang][cli] Port LangOpts option flags to new option parsing system
aec2991d083a [clang][cli] Port LangOpts simple string based options to new option parsing system
95d3cc67caac [clang][cli] Port CodeGenOpts simple string flags to new option parsing system
27b7d646886d [clang][cli] Streamline MarshallingInfoFlag description
70410a264949 [clang][cli] Let denormalizer decide how to render the option based on the option class
63a24816f561 [clang][cli] Implement `getAllArgValues` marshalling

Commit 741978d727a4 accidentally changed the `Group` attribute of `g[no_]column_info` options from `g_flags_Group` to `g_Group`, which changed the debug info options passed to cc1 by the driver.

Similar change was also present in 383778e2171b, which accidentally added `Group<f_Group>` to `f[no_]const_strings` and `f[no_]signed_wchar`.

This patch corrects all three accidental changes by replacing `Bool{G,F}Option` with `BoolCC1Option`.
The file was modifiedclang/lib/Frontend/CompilerInvocation.cpp
The file was modifiedclang/include/clang/Basic/DiagnosticFrontendKinds.td
The file was modifiedclang/include/clang/Basic/CodeGenOptions.h
The file was modifiedclang/unittests/Frontend/CompilerInvocationTest.cpp
The file was modifiedclang/include/clang/Basic/DiagnosticDriverKinds.td
The file was modifiedclang/include/clang/Driver/Options.td
The file was modifiedclang/test/Profile/c-generate.c
The file was modifiedllvm/include/llvm/Option/OptParser.td
Commit 37ac4f865fba451d969bd9b4b1e28ce296e093da by llvm-dev
[Hexagon] Regenerate zext-v4i1.ll tests

This will be improved by part of the work for D86578
The file was modifiedllvm/test/CodeGen/Hexagon/vect/zext-v4i1.ll
Commit 29d375f5ff27dc49c2c88c2ec1093cfcd826d449 by sven.vanhaastregt
[OpenCL][NFC] Improve OpenCL test file naming

Change "negative" into "invalid" and put "invalid" at the beginning of
the file name, following the bulk of the invalid tests in the
SemaOpenCL directory.

Use the "invalid-" prefix only for tests that contain only invalid

Drop the "valid" suffix for CodeGen tests, as inputs in this directory
are supposed to be valid anyway.
The file was removedclang/test/SemaOpenCL/vector_conv_invalid.cl
The file was addedclang/test/SemaOpenCL/invalid-vector-literals.cl
The file was addedclang/test/CodeGenOpenCL/vector_literals.cl
The file was removedclang/test/CodeGenOpenCL/vector_literals_valid.cl
The file was removedclang/test/SemaOpenCL/vector_literals_invalid.cl
The file was removedclang/test/CodeGenOpenCL/vector_shufflevector_valid.cl
The file was removedclang/test/SemaOpenCL/pipes-1.2-negative.cl
The file was addedclang/test/SemaOpenCL/vector-conv.cl
The file was addedclang/test/CodeGenOpenCL/vector_shufflevector.cl
The file was removedclang/test/SemaOpenCLCXX/kernel_invalid.cl
The file was addedclang/test/SemaOpenCL/invalid-pipes-cl1.2.cl
The file was addedclang/test/SemaOpenCLCXX/invalid-kernel.cl
Commit 396dd6cd3d8bdcda9dcb606ad4c054560bf0649f by llvm-dev
[ProfileData] Pass Twine by const reference instead of by value.

Its only used by DiagnosticInfoSampleProfile which takes a const reference anyhow.
The file was modifiedllvm/include/llvm/ProfileData/SampleProfReader.h
Commit df5c2caf0fc0d59d4d2e0ce99da4aa58f204791a by llvm-dev
[MIPS] MipsAsmParser - Pass Twine by const reference instead of by value. NFCI.
The file was modifiedllvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
Commit 26c486c2eb1a0f302eb60a4b959456f09adbbacb by llvm-dev
[TableGen] RegisterBankEmitter - Pass Twine by const reference instead of by value. NFCI.
The file was modifiedllvm/utils/TableGen/RegisterBankEmitter.cpp
Commit f60e0a91fbdd8e3409f5ee883a05a6c77f70720c by kareem.ergawy
[MLIR][SPIRV] Add `UnsignedOp` trait.

This commit adds a new trait that can be attached to ops that have
unsigned semantics.

- Check if other places in code can use the new attribute (possibly in this patch).
- Add a similar `SignedOp` attribute (in a new patch).

Reviewed By: antiagainst

Differential Revision: https://reviews.llvm.org/D94068
The file was modifiedmlir/include/mlir/Dialect/SPIRV/IR/SPIRVBitOps.td
The file was modifiedmlir/include/mlir/Dialect/SPIRV/IR/SPIRVLogicalOps.td
The file was addedmlir/include/mlir/Dialect/SPIRV/IR/SPIRVOpTraits.h
The file was modifiedmlir/include/mlir/Dialect/SPIRV/IR/SPIRVCastOps.td
The file was modifiedmlir/include/mlir/Dialect/SPIRV/IR/SPIRVArithmeticOps.td
The file was modifiedmlir/include/mlir/Dialect/SPIRV/IR/SPIRVAtomicOps.td
The file was modifiedmlir/include/mlir/Dialect/SPIRV/IR/SPIRVBase.td
The file was modifiedmlir/include/mlir/Dialect/SPIRV/IR/SPIRVNonUniformOps.td
The file was modifiedmlir/lib/Conversion/StandardToSPIRV/StandardToSPIRV.cpp
The file was modifiedmlir/include/mlir/Dialect/SPIRV/IR/SPIRVOps.h
Commit 4e0e79dd349a208384449fd8dcdc9bf1644ee0f3 by pavel
[lldb] Simplify some lldb-server tests

Remove manual test duplication.
The file was modifiedlldb/test/API/tools/lldb-server/memory-allocation/TestGdbRemoteMemoryAllocation.py
The file was modifiedlldb/test/API/tools/lldb-server/libraries-svr4/TestGdbRemoteLibrariesSvr4Support.py
The file was modifiedlldb/test/API/tools/lldb-server/register-reading/TestGdbRemoteGPacket.py
The file was modifiedlldb/test/API/tools/lldb-server/TestGdbRemoteAuxvSupport.py
The file was modifiedlldb/test/API/tools/lldb-server/thread-name/TestGdbRemoteThreadName.py
Commit 494db3816b0ece5b6722054f75cc2622ae1b840a by flo
[LoopDeletion] Also consider loops with subloops for deletion.

Currently, LoopDeletion does skip loops that have sub-loops, but this
means we currently fail to remove some no-op loops.

One example are inner loops with live-out values. Those cannot be
removed by itself. But the containing loop may itself be a no-op and the
whole loop-nest can be deleted.

The legality checks do not seem to rely on analyzing inner-loops only
for correctness.

With LoopDeletion being a LoopPass, the change means that we now
unfortunately need to do some extra work in parent loops, by checking
some conditions we already checked. But there appears to be no
noticeable compile time impact:

This changes patch leads to ~10 more loops being deleted on
MultiSource, SPEC2000, SPEC2006 with -O3 & LTO

This patch is also required (together with a few others) to eliminate a
no-op loop in omnetpp as discussed on llvm-dev 'LoopDeletion / removal of
empty loops.' (http://lists.llvm.org/pipermail/llvm-dev/2020-December/147462.html)

This change becomes relevant after removing potentially infinite loops
is made possible in 'must-progress' loops (D86844).

Note that I added a function call with side-effects to an outer loop in
`llvm/test/Transforms/LoopDeletion/update-scev.ll` to preserve the
original spirit of the test.

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D93716
The file was modifiedllvm/test/Transforms/LoopDeletion/noop-loops-with-subloops.ll
The file was modifiedllvm/test/Transforms/LoopDeletion/update-scev.ll
The file was modifiedllvm/lib/Transforms/Scalar/LoopDeletion.cpp
The file was modifiedllvm/test/Transforms/LoopDeletion/unreachable-loops.ll
Commit 0c41b1c9f93c09966b87126820d3cf41d8eebbf9 by yvan.roux
[Driver][MachineOutliner] Support outlining option with LTO

This patch propagates the -moutline flag when LTO is enabled and avoids
passing it explicitly to the linker plugin.

Differential Revision: https://reviews.llvm.org/D93385
The file was modifiedclang/lib/Driver/ToolChains/CommonArgs.cpp
The file was modifiedclang/lib/Driver/ToolChains/Clang.cpp
The file was addedclang/test/Driver/arm-machine-outliner.c
The file was modifiedclang/lib/Driver/ToolChains/CommonArgs.h
Commit 3fa6cedb6be809092f8a8b27e63bd4f6dc526a08 by erich.keane
Fix MaterializeTemporaryExpr's type when its an incomplete array.

Like the VarDecl that gets its type updated based on an init-list, this
patch corrects the MaterializeTemporaryExpr's type to make sure it isn't
creating an incomplete type, which leads to a handful of CodeGen crashes
(see PR 47636).

Based on @rsmith 's comments on D88236

Differential Revision: https://reviews.llvm.org/D88298
The file was modifiedclang/test/CodeGenCXX/pr47636.cpp
The file was addedclang/test/AST/pr47636.cpp
The file was modifiedclang/lib/Sema/SemaInit.cpp
Commit 25c78de6d2a50d6f90fd6cd3f0010eb3df157a6c by antiagainst
[mlir][spirv] Update pass docs

Reviewed By: hanchung

Differential Revision: https://reviews.llvm.org/D94174
The file was modifiedmlir/include/mlir/Conversion/Passes.td
Commit 46975b5b29e2ecbf97eb7be2b124d94f0ce4b45e by kparzysz
[Hexagon] Wrap functions only used in asserts in ifndef NDEBUG
The file was modifiedllvm/lib/Target/Hexagon/HexagonVectorCombine.cpp
Commit b69fe6a85db43df27ebb260716d41a3e1b0d7534 by llvm-dev
[X86] Add icmp ne/eq (srl (ctlz x), log2(bw)) test coverage.

Add vector coverage as well (which isn't currently supported).
The file was addedllvm/test/CodeGen/X86/lzcnt-cmp.ll
Commit 500864f928c272e8ebfd6493cb749083124bfd8b by llvm-dev
Remove some unused <vector> includes. NFCI.

<vector> (unlike many other c++ headers) is relatively clean, so if the file doesn't use std::vector then it shouldn't need the header.
The file was modifiedllvm/include/llvm/ExecutionEngine/JITEventListener.h
The file was modifiedllvm/include/llvm/CodeGen/CodeGenPassBuilder.h
The file was modifiedllvm/include/llvm/Analysis/InlineAdvisor.h
Commit 350247a93c07906300b79955ff882004a92ae368 by nicholas.guy
[AArch64] Rearrange mul(dup(sext/zext)) to mul(sext/zext(dup))

Performing this rearrangement allows for existing patterns
to match cases where the vector may be built after an extend,
instead of before.

Differential Revision: https://reviews.llvm.org/D91255
The file was addedllvm/test/CodeGen/AArch64/aarch64-dup-ext-scalable.ll
The file was addedllvm/test/CodeGen/AArch64/aarch64-dup-ext.ll
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.cpp
Commit 1307e3f6c46cc3a6e6ad9cd46fc67efafcac939e by llvm-dev
[TargetLowering] Add icmp ne/eq (srl (ctlz x), log2(bw)) vector support.
The file was modifiedllvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
The file was modifiedllvm/test/CodeGen/X86/lzcnt-cmp.ll
Commit 7809fa20400000fd40b4a4b56696c7fbcd0f0fa9 by andrzej.warzynski
[flang][driver] Add support for `-D`, `-U`

Add support for options -D and -U in the new Flang driver.

Summary of changes:
  - Create PreprocessorOptions, to be used by the driver then translated
    into Fortran::parser::Options
  - Create CompilerInvocation::setFortranOpts to pass preprocessor
    options into the parser options
  - Add a dedicated method, Flang::AddPreprocessingOptions, to extract
    preprocessing options from the driver arguments into the preprocessor
    command arguments

Macros specified like -DName will default to definition 1.

When defining macros, the new driver will drop anything after an
end-of-line character. This is consistent with gfortran and clang, but
different to what currently f18 does. However, flang (which is a bash
wrapper for f18), also drops everything after an end-of-line character.
So gfortran-like behaviour felt like the natural choice. Test is added
to demonstrate this behaviour.

Reviewed By: awarzynski

Differential Revision: https://reviews.llvm.org/D93401
The file was addedflang/test/Flang-Driver/macro_multiline.f90
The file was addedflang/include/flang/Frontend/PreprocessorOptions.h
The file was modifiedflang/lib/Frontend/CompilerInvocation.cpp
The file was modifiedclang/lib/Driver/ToolChains/Flang.cpp
The file was modifiedclang/lib/Driver/ToolChains/Flang.h
The file was modifiedflang/lib/Frontend/CompilerInstance.cpp
The file was modifiedflang/include/flang/Frontend/CompilerInstance.h
The file was modifiedflang/include/flang/Frontend/CompilerInvocation.h
The file was modifiedclang/include/clang/Driver/Options.td
The file was addedflang/test/Flang-Driver/macro_def_undef.f90
The file was modifiedflang/test/Flang-Driver/driver-help.f90
The file was modifiedflang/test/Flang-Driver/driver-help-hidden.f90
Commit 136f49891953ce232be2f4a8bc98e83bb2cd6462 by Matthew.Arsenault
AMDGPU: Explicitly use SelectionDAG in legacy intrinsic tests

GlobalISel will probably not support the legacy buffer intrinsics, so
don't fail when the default is switched.
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.store.format.d16.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.tbuffer.load.dwordx3.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.tbuffer.load.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.store.format.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.tbuffer.store.dwordx3.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.tbuffer.store.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.tbuffer.store.d16.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.tbuffer.load.d16.ll
Commit 0a3cf7f4762e5608750a8f6b3fa4a6efcba66c27 by Matthew.Arsenault
AMDGPU/GlobalISel: Add baseline IR tests for fdiv

The fdiv lowering is currently split between an IR pass and codegen,
so make sure this works end to end. We also currently differ from the
DAG on some edge cases, which this will show in a future change.
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f32.ll
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f64.ll
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f16.ll