SuccessChanges

Summary

  1. Fixed misspelled builder name for e-mail notifications. (details)
  2. More master to main updates (details)
  3. jenkins/jobs: Add timeout to the lnt-ctmark-* jobs (details)
Commit 388283cab6e6578f9e89d1ca122c24a922bbe280 by gkistanova
Fixed misspelled builder name for e-mail notifications.
The file was modifiedbuildbot/osuosl/master/config/status.py (diff)
The file was modifiedzorg/jenkins/jobs/util/make_pipeline.py (diff)
The file was modifiedzorg/jenkins/inspect_log.py (diff)
The file was modifiedtasks/tasktool/tasktool/repos/git.py (diff)
The file was modifiedtasks/tasktool/README.md (diff)
Commit c816513763961852ae753378e0525dd8e508d168 by Azharuddin Mohammed
jenkins/jobs: Add timeout to the lnt-ctmark-* jobs

This is so that these don't end up stuck and running forever in case of
any issues.
The file was modifiedzorg/jenkins/jobs/jobs/lnt-ctmark-aarch64-Oz (diff)
The file was modifiedzorg/jenkins/jobs/jobs/lnt-ctmark-aarch64-Os (diff)
The file was modifiedzorg/jenkins/jobs/jobs/lnt-ctmark-aarch64-O0-g (diff)
The file was modifiedzorg/jenkins/jobs/jobs/lnt-ctmark-aarch64-O3-flto (diff)

Summary

  1. [OpenMP][Tests][NFC] lit might also be known as llvm-lit.py (details)
  2. [OpenMP] Fixed a crash when offloading to x86_64 with target nowait (details)
  3. [OpenMP][Tests][NFC] rename macro to avoid naming clash (details)
  4. [tests] precommit tests for an upcoming AA improvement (details)
  5. [flang] add attribute to trim runtime implementation establish call (details)
  6. [AArch64] Do not fold SP adjustments into pre-increment addr modes if it overflows the redzone. (details)
  7. [MC][ARM] add .w suffixes for BL (T1) and DBG (details)
  8. [libomptarget] Fixed MSVC build fail caused by __attribute__((used)). (details)
  9. Revert rGd65ddca83ff85c7345fe9a0f5a15750f01e38420 - "[ValueTracking] ComputeKnownBits - minimum leading/trailing zero bits in LSHR/SHL (PR44526)" (details)
  10. [mlir] Add constBuilderCall to TypeAttr to simplify builders (details)
  11. [LegalizeIntegerTypes] Further improve ExpandIntRes_SADDSUBO for targets where SADDO/SSUBO aren't supported. (details)
  12. [mlir][spirv] Define spv.GLSL.Ldexp (details)
  13. [lit] Add --ignore-fail (details)
  14. [RISCV] Support fixed vector extract element. Use VL=1 for scalable vector extract element. (details)
  15. [AArch64][GlobalISel] Fix manual selection for v4s16 and v8s8 G_DUP (details)
  16. Remove a workaround for MSVC 2013, now that MSVC 2017 is the minimum. (details)
  17. [llvm-objcopy] If input=output, preserve umask bits, otherwise drop S_ISUID/S_ISGID bits (details)
  18. [lldb] Support debugging utility functions (details)
  19. [mlir][linalg] Support for using output values in TC definitions. (details)
  20. [mlir][linalg] Reuse the symbol if attribute uses are identical. (details)
  21. [mlir][docs] Small fix to local Pass Manager reproduction documentation (details)
  22. AMDGPU: Add even aligned VGPR/AGPR register classes (details)
  23. AMDGPU: Remove special case in shouldCoalesce (details)
  24. [InstCombine] add tests for fdiv+powi; NFC (details)
  25. [libcxx] [test] Quote the path to the python interpreter (details)
  26. [amdgpu] Atomic should be source of divergence. (details)
  27. [tests] precommit tests for D97219 (details)
  28. IR: Rename Metadata::ImplicitCode to SubclassData1, NFC (details)
  29. Transforms: Clone distinct nodes in metadata mapper unless RF_ReuseAndMutateDistinctMDs (details)
  30. [Profile] Include a few asserts in coverage mapping test (details)
  31. [InstCombine] add helper for x/pow(); NFC (details)
  32. [InstCombine] fold fdiv with powi divisor (PR49147) (details)
  33. Revert "[Profile] Include a few asserts in coverage mapping test" (details)
  34. [MC][ARM] make Thumb function also if type attribute is set (details)
  35. [builtins] Define fmax and scalbn inline (details)
  36. Reland "[Driver][Windows] Support per-target runtimes dir layout for profile instr generate" (details)
  37. Revert "[builtins] Define fmax and scalbn inline" (details)
  38. [profile] Fix buffer overrun when parsing %c in filename string (details)
  39. Allow !shape.size type operands in "shape.from_extents" op. (details)
  40. [CUDA][HIP] Support accessing static device variable in host code for -fgpu-rdc (details)
  41. [RISCV] Use a ComplexPattern for zexti32 to match sexti32. (details)
  42. [RISCV] Teach VSETVLI inserter to use VSETIVLI when possible. (details)
  43. Improve attribute documentation for nodebug on typedefs (details)
  44. [llvm] Check availability for os_signpost (details)
  45. update AMDGPU _Float16 support in clang doc (details)
  46. [test] Improve SanitizerCoverage tests on !associated and comdat (details)
  47. [lld-macho] add code signature for native arm64 macOS (details)
  48. [X86] Support amx-bf16 intrinsic. (details)
  49. [ThinLTO][NewPM] Clean up dead code under -O0 (details)
  50. [flang][fir][NFC] Move remaining types to TableGen type definition (details)
  51. [flang][fir][NFC] Remove dead code. (details)
  52. [docs] Add a release note for the removing of -Wreturn-std-move-in-c++11 (details)
  53. [Coroutine] Check indirect uses of alloca when checking lifetime info (details)
  54. [NFC][AIX] Rename aix-csr-vector.ll to aix-csr-vector-extabi.ll (details)
  55. [NARY][NFC] New tests for upcoming changes. (details)
  56. [docs][JITLink] Reintroduce JITLink design/API doc with fixes and improvements. (details)
Commit f3a72509a743726f4acdd3e4d1499a97c33f162a by protze
[OpenMP][Tests][NFC] lit might also be known as llvm-lit.py
The file was modifiedopenmp/cmake/OpenMPTesting.cmake
Commit e5da63d5a9ede1fb6d8aa18cfd44533ead128738 by tianshilei1992
[OpenMP] Fixed a crash when offloading to x86_64 with target nowait

PR#49334 reports a crash when offloading to x86_64 with `target nowait`,
which is caused by referencing a nullptr. The root cause of the issue is, when
pushing a hidden helper task in `__kmp_push_task`, it also maps the gtid to its
shadow gtid, which is wrong.

Reviewed By: jdoerfert

Differential Revision: https://reviews.llvm.org/D97329
The file was addedopenmp/libomptarget/test/offloading/bug49334.cpp
The file was modifiedopenmp/runtime/src/kmp_tasking.cpp
Commit 2fbce374c8fb6f847bf6f4f023fe753989f49aa1 by protze
[OpenMP][Tests][NFC] rename macro to avoid naming clash

Rename a macro use missed in e0f3acc5d34aa
The file was modifiedopenmp/tools/multiplex/tests/custom_data_storage/first-tool.h
Commit c1706f2269ac82cbae2ed538f0857fa6516bcbb4 by listmail
[tests] precommit tests for an upcoming AA improvement
The file was modifiedllvm/test/Analysis/BasicAA/recphi.ll
Commit b146dfe527ba81297d2949fc423e66c869bf926a by jperier
[flang] add attribute to trim runtime implementation establish call

CFI allocatable attribute is needed so that the descriptor for the
result can be allocated/deallocated.

Reviewed By: klausler

Differential Revision: https://reviews.llvm.org/D97395
The file was modifiedflang/runtime/character.cpp
Commit 0146d206317e1d40775621639a4dde7c43e0f433 by Amara Emerson
[AArch64] Do not fold SP adjustments into pre-increment addr modes if it overflows the redzone.

Instead of outright disabling this completely with the noredzone attribute,
we only avoid doing the optimization if there are memory operations between
the adjustment and the load/store that the adjustment would be folded into.
This avoids the case of something like a stack cookie being corrupted if an
exception happens before the pre-increment to the SP occurs.

This also prevents the folding happening if we have a redzone, but the offset
being folded is above the redzone amount (128 bytes in this case).

rdar://73269336

Differential Revision: https://reviews.llvm.org/D95179
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.h
The file was modifiedllvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
The file was modifiedllvm/lib/Target/AArch64/AArch64FrameLowering.cpp
The file was addedllvm/test/CodeGen/AArch64/ldst-nopreidx-sp-redzone.mir
Commit 404843a94dbf2f9d91b9bb1dfc8608a4d7ae58c7 by ndesaulniers
[MC][ARM] add .w suffixes for BL (T1) and DBG

F1.2 Standard assembler syntax fields
describes .w and .n suffixes for wide and narrow encodings.

arch/arm/probes/kprobes/test-thumb.c tests installing kprobes for
certain instructions using inline asm.  There's a few instructions we
fail to assemble due to missing .w t2InstAliases.

Adds .w suffixes for:
* bl  (F5.1.25 BL, BLX (immediate) T1)
* dbg (F5.1.42 DBG T1)

Reviewed By: DavidSpickett

Differential Revision: https://reviews.llvm.org/D97236
The file was modifiedllvm/test/MC/ARM/thumb2-branches.s
The file was modifiedllvm/lib/Target/ARM/ARMInstrThumb2.td
The file was modifiedllvm/test/MC/ARM/basic-thumb2-instructions.s
Commit 6baeeb9efa8ec6d64d66fdceac7240b5b08fb40b by vyacheslav.p.zakharin
[libomptarget] Fixed MSVC build fail caused by __attribute__((used)).

Differential Revision: https://reviews.llvm.org/D97348
The file was modifiedopenmp/libomptarget/include/Debug.h
Commit 96a3dfeb9303f2f2d26628bd08908554286895cf by llvm-dev
Revert rGd65ddca83ff85c7345fe9a0f5a15750f01e38420 - "[ValueTracking] ComputeKnownBits - minimum leading/trailing zero bits in LSHR/SHL (PR44526)"

This is causing sanitizer test failures that I haven't been able to fix yet.
The file was modifiedllvm/lib/Analysis/ValueTracking.cpp
The file was modifiedllvm/lib/Support/KnownBits.cpp
The file was modifiedllvm/test/Transforms/InstSimplify/icmp-constant.ll
Commit 5f8a80882b72695978035a25002d365d0dd84803 by antiagainst
[mlir] Add constBuilderCall to TypeAttr to simplify builders

Reviewed By: rriddle

Differential Revision: https://reviews.llvm.org/D97344
The file was modifiedmlir/include/mlir/IR/OpBase.td
The file was modifiedmlir/lib/Conversion/StandardToSPIRV/StandardToSPIRV.cpp
The file was modifiedmlir/lib/Dialect/StandardOps/Transforms/TensorConstantBufferize.cpp
Commit fe50be12c8b845fffd44c508ad981901d25ac5f8 by craig.topper
[LegalizeIntegerTypes] Further improve ExpandIntRes_SADDSUBO for targets where SADDO/SSUBO aren't supported.

Rather than converting 3 signbits to bools and comparing them,
we can do bitwise logic on the whole vector and convert the
resulting sign bit to a bool at the end.

This is still a different algorithm than what we do in LegalizeDAG
through expandSADDOSSUBO. That algorithm needs to know that the
RHS of SSUBO is > 0, but that's costly when the type is split.

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D97325
The file was modifiedllvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
The file was modifiedllvm/test/CodeGen/AArch64/sadd_sat_vec.ll
The file was modifiedllvm/test/CodeGen/RISCV/ssub_sat_plus.ll
The file was modifiedllvm/test/CodeGen/RISCV/xaluo.ll
The file was modifiedllvm/test/CodeGen/RISCV/sadd_sat_plus.ll
The file was modifiedllvm/test/CodeGen/AArch64/ssub_sat_vec.ll
The file was modifiedllvm/test/CodeGen/Thumb2/mve-saturating-arith.ll
The file was modifiedllvm/test/CodeGen/ARM/sadd_sat.ll
The file was modifiedllvm/test/CodeGen/RISCV/sadd_sat.ll
The file was modifiedllvm/test/CodeGen/ARM/ssub_sat.ll
The file was modifiedllvm/test/CodeGen/RISCV/ssub_sat.ll
The file was modifiedllvm/test/CodeGen/ARM/ssub_sat_plus.ll
The file was modifiedllvm/test/CodeGen/ARM/sadd_sat_plus.ll
Commit ce2ad938ff1fd4bad6ee91809f970984b1614e35 by antiagainst
[mlir][spirv] Define spv.GLSL.Ldexp

co-authored-by: Alan Liu <alanliu.yf@gmail.com>

Reviewed By: antiagainst

Differential Revision: https://reviews.llvm.org/D97228
The file was modifiedmlir/lib/Dialect/SPIRV/IR/SPIRVOps.cpp
The file was modifiedmlir/test/Dialect/SPIRV/IR/glsl-ops.mlir
The file was modifiedmlir/include/mlir/Dialect/SPIRV/IR/SPIRVGLSLOps.td
The file was modifiedmlir/test/Target/SPIRV/glsl-ops.mlir
Commit 2a5aa81739d31959600978c0f11332823010a754 by jdenny.ornl
[lit] Add --ignore-fail

For some build configurations, `check-all` calls lit multiple times to
run multiple lit test suites.  Most recently, I've found this to be
true when configuring openmp as part of `LLVM_ENABLE_RUNTIMES`, but
this is not the first time.

If one test suite fails, none of the remaining test suites run, so you
cannot determine if your patch has broken them.  It can then be
frustrating to try to determine which `check-` targets will run the
remaining tests without getting stuck on the failing tests.

When such cases arise, it is probably best to adjust the cmake
configuration for `check-all` to run all test suites as part of one
lit invocation.  Because that fix will likely not be implemented and
land immediately, this patch introduces `--ignore-fail` to serve as a
workaround for developers trying to see test results until it does
land:

```
$ LIT_OPTS=--ignore-fail ninja check-all
```

One problem with `--ignore-fail` is that it makes it challenging to
detect test failures in a script, perhaps in CI.  This problem should
serve as motivation to actually fix the cmake configuration instead of
continuing to use `--ignore-fail` indefinitely.

Reviewed By: jhenderson, thopre

Differential Revision: https://reviews.llvm.org/D96371
The file was modifiedllvm/utils/lit/lit/main.py
The file was addedllvm/utils/lit/tests/Inputs/ignore-fail/xpass.txt
The file was addedllvm/utils/lit/tests/ignore-fail.py
The file was addedllvm/utils/lit/tests/Inputs/ignore-fail/fail.txt
The file was addedllvm/utils/lit/tests/Inputs/ignore-fail/lit.cfg
The file was addedllvm/utils/lit/tests/Inputs/ignore-fail/unresolved.txt
The file was modifiedllvm/docs/CommandGuide/lit.rst
The file was modifiedllvm/utils/lit/lit/cl_arguments.py
The file was addedllvm/utils/lit/tests/Inputs/ignore-fail/xfail.txt
Commit 086670d367869e62a3c5dffe3cd9bed04a5898c2 by craig.topper
[RISCV] Support fixed vector extract element. Use VL=1 for scalable vector extract element.

I've changed to use VL=1 for slidedown and shifts to avoid extra
element processing that we don't need.

The i64 fixed vector handling on i32 isn't great if the vector type
isn't legal due to an ordering issue in type legalization. If the
vector type isn't legal, we fall back to default legalization
which will bitcast the vector to vXi32 and use two independent extracts.
Doing better will require handling several different cases by
manually inserting insert_subvector/extract_subvector to adjust the type
to a legal vector before emitting custom nodes.

Reviewed By: frasercrmck

Differential Revision: https://reviews.llvm.org/D97319
The file was modifiedllvm/test/CodeGen/RISCV/rvv/extractelt-fp-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vreductions-int-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/extractelt-int-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/extractelt-int-rv64.ll
The file was modifiedllvm/lib/Target/RISCV/RISCVISelLowering.cpp
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/extractelt-fp-rv64.ll
Commit e339bba637b941c8e78057319b7654c4babf18cb by Jessica Paquette
[AArch64][GlobalISel] Fix manual selection for v4s16 and v8s8 G_DUP

The manual G_DUP selection code would produce DUPv16i8 for v8s8s and DUPv8i16
for v4s16.

This adds the missing cases to the manual selection code, and makes it return
false when there is an unexpected size.

Update select-dup.mir to reflect the change.

Differential Revision: https://reviews.llvm.org/D97240
The file was modifiedllvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/select-dup.mir
Commit c2487bf7dfdda59b775b3d5a06684af243790125 by jyknight
Remove a workaround for MSVC 2013, now that MSVC 2017 is the minimum.

In MSVC 2013, 'alignas(integer-template-arg)' didn't compile; verified
on godbolt that this now works properly.
The file was modifiedllvm/include/llvm/Support/TrailingObjects.h
Commit 17b4e695ce0ef89eac4a37df2df49d4c0e700766 by i
[llvm-objcopy] If input=output, preserve umask bits, otherwise drop S_ISUID/S_ISGID bits

This makes the behavior similar to cp

```
chmod u+s,g+s,o+x a
sudo llvm-strip a -o b
// With this patch, b drops set-user-ID and set-group-ID bits.
// sudo cp a b => b does not have set-user-ID or set-group-ID bits.
```

This also changes the behavior for the following case:

```
chmod u+s,g+s,o+x a
llvm-strip a
// a preserves set-user-ID and set-group-ID bits.
// This matches binutils<2.36 and probably >=2.37.  2.36 and 2.36.1 have some compatibility issues.
```

Differential Revision: https://reviews.llvm.org/D97253
The file was modifiedllvm/tools/llvm-objcopy/llvm-objcopy.cpp
The file was modifiedllvm/test/tools/llvm-objcopy/ELF/mirror-permissions-unix.test
Commit 38dfb235db19caa1aaa58c1c8153a7464b932087 by Jonas Devlieghere
[lldb] Support debugging utility functions

LLDB uses utility functions to run code in the inferior for its own
internal purposes, such as reading classes from the Objective-C runtime
for example. Because these expressions should be transparent to the
user, we ignore breakpoints and unwind the stack on errors, which
makes them hard to debug.

This patch adds a new setting target.debug-utility-expression that, when
enabled, changes these options to facilitate debugging. It enables
breakpoints, disables unwinding and writes out the utility function
source code to disk so it shows up in the source view.

Differential revision: https://reviews.llvm.org/D97249
The file was modifiedlldb/include/lldb/Expression/UtilityFunction.h
The file was modifiedlldb/source/Expression/FunctionCaller.cpp
The file was modifiedlldb/source/Expression/UtilityFunction.cpp
The file was modifiedlldb/source/Plugins/ExpressionParser/Clang/ClangUtilityFunction.h
The file was modifiedlldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp
The file was modifiedlldb/source/Plugins/ExpressionParser/Clang/ClangExpressionSourceCode.cpp
The file was modifiedlldb/include/lldb/Target/Target.h
The file was modifiedlldb/source/Target/TargetProperties.td
The file was modifiedlldb/source/Target/Target.cpp
The file was modifiedlldb/source/Plugins/ExpressionParser/Clang/ClangExpressionSourceCode.h
The file was modifiedlldb/source/Plugins/ExpressionParser/Clang/ClangUtilityFunction.cpp
Commit 705068cb8c4d86c798c4134f0a332f4a45c7df04 by hanchung
[mlir][linalg] Support for using output values in TC definitions.

This will allow us to define select(pred, in, out) for TC ops, which is useful
for pooling ops.

Reviewed By: antiagainst

Differential Revision: https://reviews.llvm.org/D97312
The file was modifiedmlir/include/mlir/Dialect/Linalg/IR/LinalgNamedStructuredOpsSpec.tc
The file was modifiedmlir/test/mlir-linalg-ods-gen/test-linalg-ods-gen.tc
The file was modifiedmlir/tools/mlir-linalg-ods-gen/mlir-linalg-ods-gen.cpp
Commit 21895a2beff7fcd92441c884de7c04f324996c79 by hanchung
[mlir][linalg] Reuse the symbol if attribute uses are identical.

Depends On D97312

Reviewed By: antiagainst

Differential Revision: https://reviews.llvm.org/D97383
The file was modifiedmlir/tools/mlir-linalg-ods-gen/mlir-linalg-ods-gen.cpp
The file was modifiedmlir/test/mlir-linalg-ods-gen/test-linalg-ods-gen.tc
Commit e79cd47e1620045562960ddfe17ab0c4f6e6628f by riddleriver
[mlir][docs] Small fix to local Pass Manager reproduction documentation
The file was modifiedmlir/docs/PassManagement.md
Commit 78b6d73a93fc6085d2a2fc84bdce1bbde740cf16 by Matthew.Arsenault
AMDGPU: Add even aligned VGPR/AGPR register classes

gfx90a operations require even aligned registers, but this was
previously achieved by reserving registers inside the full class.

Ideally this would be captured in the static instruction definitions
for the operands, and we would have different instructions per
subtarget. The hackiest part of this is we need to manually reassign
AGPR register classes after instruction selection (we get away without
this for VGPRs since those types are actually registered for legal
types).
The file was modifiedllvm/lib/Target/AMDGPU/SIInstrInfo.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/reserved-reg-in-clause.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.atomic.fadd.ll
The file was modifiedllvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/inline-asm.i128.ll
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/dpp64_combine.mir
The file was modifiedllvm/lib/Target/AMDGPU/SIISelLowering.cpp
The file was addedllvm/test/CodeGen/AMDGPU/alloc-aligned-tuples-gfx908.mir
The file was modifiedllvm/lib/Target/AMDGPU/SIRegisterInfo.h
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.atomic.fadd.ll
The file was addedllvm/test/CodeGen/AMDGPU/verify-gfx90a-aligned-vgprs.mir
The file was modifiedllvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/merge-load-store-agpr.mir
The file was modifiedllvm/lib/Target/AMDGPU/SIRegisterInfo.td
The file was modifiedllvm/lib/Target/AMDGPU/GCNSubtarget.h
The file was modifiedllvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
The file was removedllvm/test/CodeGen/AMDGPU/reserved-vgpr-tuples.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/twoaddr-fma-f64.mir
The file was addedllvm/test/CodeGen/AMDGPU/alloc-aligned-tuples-gfx90a.mir
The file was modifiedllvm/lib/Target/AMDGPU/SIInstructions.td
Commit 589223e044dbea0554d2e8b54bf49e9cc278b643 by Matthew.Arsenault
AMDGPU: Remove special case in shouldCoalesce

Unaligned registers are now constrained with classes, rather than
specially reserving a subset of the whole class.
The file was modifiedllvm/test/CodeGen/AMDGPU/fp64-atomics-gfx90a.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.dim.gfx90a.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/coalesce-vgpr-alignment.ll
The file was modifiedllvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/global-atomics-fp.ll
Commit 3475159122b656ff098e2f44af32dc56f3beb610 by spatel
[InstCombine] add tests for fdiv+powi; NFC
The file was modifiedllvm/test/Transforms/InstCombine/fdiv.ll
Commit c218c80c730a14a1cbcebd588b18220a879702c6 by martin
[libcxx] [test] Quote the path to the python interpreter

This should allow running tests with the interpreter in some of the
default paths where Python for Windows might be installed.

Differential Revision: https://reviews.llvm.org/D97369
The file was modifiedlibcxx/test/CMakeLists.txt
Commit 0d4e12e3c110e5d73302a369f5e17d1fa67710e1 by michael.hliao
[amdgpu] Atomic should be source of divergence.

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D97392
The file was modifiedllvm/lib/Target/AMDGPU/SIISelLowering.cpp
The file was addedllvm/test/CodeGen/AMDGPU/dag-divergence-atomic.ll
Commit 52745e4d907867bbb28fb8b0e8456915611a47a3 by listmail
[tests] precommit tests for D97219
The file was modifiedllvm/test/Transforms/LoopStrengthReduce/post-increment-insertion.ll
Commit 1e1b92f76de79b934ead3be075aff101bd880392 by Duncan P. N. Exon Smith
IR: Rename Metadata::ImplicitCode to SubclassData1, NFC

Metadata::ImplicitCode is a bit shaved off of Metadata::Storage,
currently only in use by the subclass DILocation. However, the bit isn't
reserved for that purpose. Rename it `SubclassData1` to make it clear
that it has nothing to do with Metadata itself (and other subclasses are
free to use it).

As a drive-by, remove an old TODO about exposing bits to subclasses
(looks like that has mostly been done).

No functionality change here.

Differential Revision: https://reviews.llvm.org/D96740
The file was modifiedllvm/include/llvm/IR/Metadata.h
The file was modifiedllvm/include/llvm/IR/DebugInfoMetadata.h
Commit 01701646d5555409a6fad920f0e4801d79c154ea by Duncan P. N. Exon Smith
Transforms: Clone distinct nodes in metadata mapper unless RF_ReuseAndMutateDistinctMDs

This is a follow up to 22a52dfddcefad4f275eb8ad1cc0e200074c2d8a and a
revert of df763188c9a1ecb1e7e5c4d4ea53a99fbb755903.

With this change, we only skip cloning distinct nodes in
MDNodeMapper::mapDistinct if RF_ReuseAndMutateDistinctMDs, dropping the
no-longer-needed local helper `cloneOrBuildODR()`.  Skipping cloning in
other cases is unsound and breaks CloneModule, which is why the textual
IR for PR48841 didn't pass previously. This commit adds the test as:
Transforms/ThinLTOBitcodeWriter/cfi-debug-info-cloned-type-references-global-value.ll

Cloning less often exposed a hole in subprogram cloning in
CloneFunctionInto thanks to df763188c9a1ecb1e7e5c4d4ea53a99fbb755903's
test ThinLTO/X86/Inputs/dicompositetype-unique-alias.ll. If a function
has a subprogram attachment whose scope is a DICompositeType that
shouldn't be cloned, but it has no internal debug info pointing at that
type, that composite type was being cloned. This commit plugs that hole,
calling DebugInfoFinder::processSubprogram from CloneFunctionInto.

As hinted at in 22a52dfddcefad4f275eb8ad1cc0e200074c2d8a's commit
message, I think we need to formalize ownership of metadata a bit more
so that ValueMapper/CloneFunctionInto (and similar functions) can deal
with cloning (or not) metadata in a more generic, less fragile way.

This fixes PR48841.

Differential Revision: https://reviews.llvm.org/D96734
The file was modifiedllvm/lib/Transforms/Utils/ValueMapper.cpp
The file was modifiedllvm/include/llvm/IR/DebugInfo.h
The file was addedllvm/test/Transforms/ThinLTOBitcodeWriter/cfi-debug-info-cloned-type-references-global-value.ll
The file was modifiedllvm/lib/Transforms/Utils/CloneFunction.cpp
Commit 80f329bcd0281c11062879025761d0657167fe8b by phosek
[Profile] Include a few asserts in coverage mapping test

These should catch any accidental use of the compilation directory.

Differential Revision: https://reviews.llvm.org/D97402
The file was modifiedllvm/unittests/ProfileData/CoverageMappingTest.cpp
Commit 868d43fbd6571d11f91564969676bb0f1b19b455 by spatel
[InstCombine] add helper for x/pow(); NFC

We at least want to add powi to this list, so
split it off into a switch to reduce code duplication.
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp
Commit a7cee55762c6564de9dfc90985fe5c14cad7f9ee by spatel
[InstCombine] fold fdiv with powi divisor (PR49147)

This extends b40fde062c for the especially non-standard
powi pattern. We want to avoid being completely wrong
on the negation-of-int-min corner case, so I'm adding
an extra FMF check for 'ninf' assuming that gives us
the flexibility to handle that possibility.
https://llvm.org/PR49147
The file was modifiedllvm/test/Transforms/InstCombine/fdiv.ll
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp
Commit ae7528a34e2771ba4f0741e4941f78810854103d by phosek
Revert "[Profile] Include a few asserts in coverage mapping test"

This reverts commit 80f329bcd0281c11062879025761d0657167fe8b.
The file was modifiedllvm/unittests/ProfileData/CoverageMappingTest.cpp
Commit a921aaf789912d981cbb2036bdc91ad7289e1523 by ndesaulniers
[MC][ARM] make Thumb function also if type attribute is set

Make sure to set the bottom bit of the symbol even when the type
attribute of a label is set after the label.

GNU as sets the thumb state according to the thumb state of the label.
If a .type directive is placed after the label, set the symbol's thumb
state according to the thumb state of the .type directive. This matches
GNU as in most cases.

From: Stefan Agner <stefan@agner.ch>

This fixes:
https://bugs.llvm.org/show_bug.cgi?id=44860
https://github.com/ClangBuiltLinux/linux/issues/866

Reviewed By: MaskRay

Differential Revision: https://reviews.llvm.org/D74927
The file was modifiedllvm/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp
The file was addedllvm/test/MC/ARM/thumb-function-address.s
Commit 341889ee9e03e73b313263c516b3d1fd33d4c4ba by rprichard
[builtins] Define fmax and scalbn inline

Define inline versions of __compiler_rt_fmax* and __compiler_rt_scalbn*
rather than depend on the versions in libm. As with
__compiler_rt_logbn*, these functions are only defined for single,
double, and quad precision (binary128).

Fixes PR32279 for targets using only these FP formats (e.g. Android
on arm/arm64/x86/x86_64).

For single and double precision, on AArch64, use __builtin_fmax[f]
instead of the new inline function, because the builtin expands to the
AArch64 fmaxnm instruction.

Reviewed By: MaskRay

Differential Revision: https://reviews.llvm.org/D91841
The file was modifiedcompiler-rt/lib/builtins/fp_lib.h
The file was addedcompiler-rt/test/builtins/Unit/compiler_rt_scalbnf_test.c
The file was modifiedcompiler-rt/lib/builtins/divdc3.c
The file was addedcompiler-rt/test/builtins/Unit/compiler_rt_fmaxf_test.c
The file was modifiedcompiler-rt/lib/builtins/int_math.h
The file was addedcompiler-rt/test/builtins/Unit/compiler_rt_fmaxl_test.c
The file was addedcompiler-rt/test/builtins/Unit/compiler_rt_fmax_test.c
The file was modifiedcompiler-rt/lib/builtins/divtc3.c
The file was addedcompiler-rt/test/builtins/Unit/compiler_rt_scalbnl_test.c
The file was modifiedcompiler-rt/lib/builtins/divsc3.c
The file was addedcompiler-rt/test/builtins/Unit/compiler_rt_scalbn_test.c
The file was modifiedcompiler-rt/lib/builtins/int_lib.h
The file was modifiedcompiler-rt/lib/builtins/ppc/divtc3.c
Commit 9f1b832331e350426f7f2f8cc30ab8ba991f5884 by markus.boeck02
Reland "[Driver][Windows] Support per-target runtimes dir layout for profile instr generate"

This relands commit rG7f9d5d6e444c which was reverted in rGab5b00ada9e7

Differential Revision: https://reviews.llvm.org/D96638
The file was modifiedclang/lib/Driver/ToolChains/BareMetal.h
The file was modifiedclang/test/Driver/cl-options.c
The file was modifiedclang/test/Driver/fsanitize.c
The file was modifiedclang/lib/Driver/ToolChains/BareMetal.cpp
The file was modifiedclang/test/Driver/instrprof-ld.c
The file was modifiedclang/include/clang/Driver/ToolChain.h
The file was modifiedclang/test/Driver/sanitizer-ld.c
The file was modifiedclang/lib/Driver/ToolChain.cpp
Commit 680f836c2fa72166badd594a52b3f41b2ad074d2 by rprichard
Revert "[builtins] Define fmax and scalbn inline"

This reverts commit 341889ee9e03e73b313263c516b3d1fd33d4c4ba.

The new unit tests fail on sanitizer-windows.
The file was modifiedcompiler-rt/lib/builtins/divsc3.c
The file was modifiedcompiler-rt/lib/builtins/divdc3.c
The file was modifiedcompiler-rt/lib/builtins/int_lib.h
The file was modifiedcompiler-rt/lib/builtins/fp_lib.h
The file was removedcompiler-rt/test/builtins/Unit/compiler_rt_scalbnl_test.c
The file was removedcompiler-rt/test/builtins/Unit/compiler_rt_scalbn_test.c
The file was removedcompiler-rt/test/builtins/Unit/compiler_rt_fmax_test.c
The file was modifiedcompiler-rt/lib/builtins/ppc/divtc3.c
The file was modifiedcompiler-rt/lib/builtins/int_math.h
The file was removedcompiler-rt/test/builtins/Unit/compiler_rt_fmaxl_test.c
The file was removedcompiler-rt/test/builtins/Unit/compiler_rt_scalbnf_test.c
The file was removedcompiler-rt/test/builtins/Unit/compiler_rt_fmaxf_test.c
The file was modifiedcompiler-rt/lib/builtins/divtc3.c
Commit a7d4826101aba8594bf5308c6a3e40c44608bca5 by Vedant Kumar
[profile] Fix buffer overrun when parsing %c in filename string

Fix a buffer overrun that can occur when parsing '%c' at the end of a
filename pattern string.

rdar://74571261

Reviewed By: kastiglione

Differential Revision: https://reviews.llvm.org/D97239
The file was addedcompiler-rt/test/profile/ContinuousSyncMode/get-filename.c
The file was modifiedcompiler-rt/lib/profile/InstrProfilingFile.c
Commit c519460745ece21238b0ee6c0f9b921366701308 by silvasean
Allow !shape.size type operands in "shape.from_extents" op.

This expands the op to support error propagation and also makes it symmetric with  "shape.get_extent" op.

Reviewed By: silvas

Differential Revision: https://reviews.llvm.org/D97261
The file was modifiedmlir/test/Dialect/Shape/canonicalize.mlir
The file was modifiedmlir/include/mlir/Dialect/Shape/IR/ShapeOps.td
Commit 47acdec1dd5d6d4c279727a97313c586c20e9c6f by Yaxun.Liu
[CUDA][HIP] Support accessing static device variable in host code for -fgpu-rdc

For -fgpu-rdc mode, static device vars in different TU's may have the same name.
To support accessing file-scope static device variables in host code, we need to give them
a distinct name and external linkage. This can be done by postfixing each static device variable with
a distinct CUID (Compilation Unit ID) hash.

Since the static device variables have different name across compilation units, now we let
them have external linkage so that they can be looked up by the runtime.

Reviewed by: Artem Belevich, and Jon Chesterfield

Differential Revision: https://reviews.llvm.org/D85223
The file was modifiedclang/lib/CodeGen/CGCUDANV.cpp
The file was modifiedclang/test/CodeGenCUDA/device-var-linkage.cu
The file was addedclang/test/SemaCUDA/static-device-var.cu
The file was modifiedclang/lib/CodeGen/CodeGenModule.h
The file was addedclang/test/CodeGenCUDA/static-device-var-rdc.cu
The file was modifiedclang/include/clang/AST/ASTContext.h
The file was modifiedclang/lib/CodeGen/CodeGenModule.cpp
The file was modifiedclang/test/CodeGenCUDA/managed-var.cu
The file was modifiedclang/lib/AST/ASTContext.cpp
Commit 9bde29629dfec420dbfbfe550073415452ae81f9 by craig.topper
[RISCV] Use a ComplexPattern for zexti32 to match sexti32.

We just started using a ComplexPattern for sexti32. This updates
zexti32 to match.

Reviewed By: luismarques

Differential Revision: https://reviews.llvm.org/D97231
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
The file was modifiedllvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfo.td
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfoF.td
The file was modifiedllvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfoD.td
Commit efcdd598b766e764a7efb48b49e9ec8b0a590510 by craig.topper
[RISCV] Teach VSETVLI inserter to use VSETIVLI when possible.

We always create the VL operand using a register, but if we can
determine that it came from an ADDI X0, imm with a sufficiently
small immediate, we can use VSETIVLI.

Reviewed By: frasercrmck

Differential Revision: https://reviews.llvm.org/D97332
The file was modifiedllvm/test/CodeGen/RISCV/rvv/extractelt-int-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-vrgather.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/extractelt-int-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-splat-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-splat.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vreductions-int-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-splat-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-splat.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-setcc.ll
The file was modifiedllvm/lib/Target/RISCV/RISCVISelLowering.cpp
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-load-store.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-setcc.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-logic.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/extractelt-fp-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-vrgather.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/extractelt-fp-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/zvlsseg-zero-vl.ll
Commit 7c926fee930012f9ec19cdaab23b7e154a3845ba by dblaikie
Improve attribute documentation for nodebug on typedefs

(followup to 8472fa6c54c9d044adcd147f6826bccebd730f30 )
The file was modifiedclang/include/clang/Basic/AttrDocs.td
Commit b03bb054e19c550ba895ec406e7b04cd1531407e by Jonas Devlieghere
[llvm] Check availability for os_signpost

Add availability checks to the os_signpost code so this can be used with
an older deployment target.

Differential revision: https://reviews.llvm.org/D97410
The file was modifiedllvm/lib/Support/Signposts.cpp
Commit 392fd3f1bf9f925942b385d8b99fb662d5739a83 by Yaxun.Liu
update AMDGPU _Float16 support in clang doc

Reviewed by: Matt Arsenault

Differential Revision: https://reviews.llvm.org/D97386
The file was modifiedclang/docs/LanguageExtensions.rst
Commit e9445765a5708a9097c253a5f783349ace2956ee by i
[test] Improve SanitizerCoverage tests on !associated and comdat
The file was modifiedllvm/test/Instrumentation/SanitizerCoverage/interposable-symbol-nocomdat.ll
The file was modifiedllvm/test/Instrumentation/SanitizerCoverage/trace-pc-guard-comdat.ll
The file was modifiedllvm/test/Instrumentation/SanitizerCoverage/inline-bool-flag.ll
The file was modifiedllvm/test/Instrumentation/SanitizerCoverage/trace-pc-guard-nocomdat.ll
Commit 151990dd94e5087c94527553e9a91b64ae864a71 by gkm
[lld-macho] add code signature for native arm64 macOS

Differential Revision: https://reviews.llvm.org/D96164
The file was modifiedlld/MachO/SyntheticSections.h
The file was modifiedlld/MachO/OutputSegment.h
The file was modifiedlld/MachO/Writer.cpp
The file was modifiedllvm/include/llvm/BinaryFormat/MachO.h
The file was modifiedlld/MachO/SyntheticSections.cpp
Commit 4bc7c8631ad62487a290dd4b7791848b67635787 by chen3.liu
[X86] Support amx-bf16 intrinsic.

Adding support for intrinsics of AMX-BF16.
This patch alse fix a bug that AMX-INT8 instructions will be selected with wrong
predicate.

Differential Revision: https://reviews.llvm.org/D97358
The file was modifiedllvm/lib/Target/X86/X86PreTileConfig.cpp
The file was modifiedclang/test/CodeGen/X86/amx_api.c
The file was modifiedllvm/lib/Target/X86/X86ExpandPseudo.cpp
The file was modifiedllvm/lib/Target/X86/X86RegisterInfo.cpp
The file was modifiedclang/lib/Headers/amxintrin.h
The file was modifiedllvm/lib/Target/X86/X86ISelDAGToDAG.cpp
The file was modifiedllvm/test/CodeGen/X86/AMX/amx-tile-basic.ll
The file was modifiedclang/include/clang/Basic/BuiltinsX86_64.def
The file was modifiedllvm/lib/Target/X86/X86InstrAMX.td
The file was modifiedllvm/lib/Target/X86/X86LowerAMXType.cpp
The file was modifiedllvm/include/llvm/IR/IntrinsicsX86.td
Commit a9b33ffb8f84f0f5b1c2253973ed04bc776bd710 by aeubanks
[ThinLTO][NewPM] Clean up dead code under -O0

We're running into undefined references using ThinLTO with -O0 on
Windows/Chrome. This fixes that.

This matches the legacy PM.

Reviewed By: tejohnson

Differential Revision: https://reviews.llvm.org/D97414
The file was modifiedllvm/test/Other/new-pm-O0-defaults.ll
The file was modifiedllvm/lib/Passes/PassBuilder.cpp
Commit 841f6995cd33b8891655b2aeb78deca548362c23 by clementval
[flang][fir][NFC] Move remaining types to TableGen type definition

Move the remaing of FIR types to TableGen type definition. This follow suggestion in D96422.

Reviewed By: schweitz, jeanPerier, rriddle

Differential Revision: https://reviews.llvm.org/D96987
The file was modifiedflang/lib/Optimizer/Dialect/FIRType.cpp
The file was modifiedflang/include/flang/Optimizer/Dialect/FIRType.h
The file was modifiedflang/include/flang/Optimizer/Dialect/FIRTypes.td
The file was modifiedflang/include/flang/Optimizer/Dialect/FIROps.td
Commit 082ec3ab07760d1a6e47886246090c6f58708dbf by eschweitz
[flang][fir][NFC] Remove dead code.

This patch removes OpaqueAttr as it is no longer used.

Differential Revision: https://reviews.llvm.org/D97424
The file was modifiedflang/test/Fir/fir-ops.fir
The file was modifiedflang/lib/Optimizer/Dialect/FIRAttr.cpp
The file was modifiedflang/include/flang/Optimizer/Dialect/FIRAttr.h
The file was modifiedflang/lib/Optimizer/Dialect/FIRDialect.cpp
Commit b950de5c13ef2171c0457a413c3b06aa31047938 by nullptr.cpp
[docs] Add a release note for the removing of -Wreturn-std-move-in-c++11

`-Wreturn-std-move-in-c++11` has been removed in fbee4a0c79cc4ee87c34e51342742a5bc6fcf872.

Reviewed By: aaronpuchert, amccarth

Differential Revision: https://reviews.llvm.org/D97364
The file was modifiedclang/docs/ReleaseNotes.rst
Commit c38000a9fb2cd64ad6e72939643e2c0fa4972690 by lxfind
[Coroutine] Check indirect uses of alloca when checking lifetime info

In the existing logic, we look at the lifetime.start marker of each alloca, and check all uses of the alloca, to see if any pair of the lifetime marker and an use of alloca crosses suspension point.
This approach is unfortunately incorrect. An use of alloca does not need to be a direct use, but can be an indirect use through alias.
Only checking direct uses can miss cases where indirect uses are crossing suspension point.
This can be demonstrated in the newly added test case 007.
In the test case, both x and y are only directly used prior to suspend, but they are captured into an alias, merged through a PHINode (so they couldn't be materialized), and used after CoroSuspend.
If we only check whether the lifetime starts cross suspension points with direct uses, we will put the allocas to the stack, and then capture their addresses in the frame.

Instead of fixing it in D96441 and D96566, this patch takes a different approach which I think is better.
We still checks the lifetime info in the same way as before, but with two differences:
1. The collection of liftime.start is moved into AllocaUseVisitor to make the logic more concentrated.
2. When looking at lifetime.start and use pairs, we not only checks the direct uses as before, but in this patch we check all uses collected by AllocaUseVisitor, which would include all indirect uses through alias. This will make the analysis more accurate without throwing away the lifetime optimization.

Differential Revision: https://reviews.llvm.org/D96922
The file was addedllvm/test/Transforms/Coroutines/coro-alloca-07.ll
The file was modifiedllvm/lib/Transforms/Coroutines/CoroFrame.cpp
The file was addedllvm/test/Transforms/Coroutines/coro-alloca-08.ll
Commit 1c051b7b704257ed9a7c02844ee8c1ea9327dfee by zarko
[NFC][AIX] Rename aix-csr-vector.ll to aix-csr-vector-extabi.ll
The file was removedllvm/test/CodeGen/PowerPC/aix-csr-vector.ll
The file was addedllvm/test/CodeGen/PowerPC/aix-csr-vector-extabi.ll
Commit 6d31ee1cea7554fec9f3be6c4a40fc10e1595879 by ybrevnov
[NARY][NFC] New tests for upcoming changes.
The file was addedllvm/test/Transforms/NaryReassociate/nary-umin.ll
The file was addedllvm/test/Transforms/NaryReassociate/nary-smax.ll
The file was addedllvm/test/Transforms/NaryReassociate/nary-umax.ll
The file was addedllvm/test/Transforms/NaryReassociate/nary-smin.ll
Commit 93c8246952d08fc4640946a8cb4151d399ec1684 by Lang Hames
[docs][JITLink] Reintroduce JITLink design/API doc with fixes and improvements.

This document was originally introduced in ab4648504b2, and was reverted in
912bc4980e9 while I investigated a number of shpinx bot errors. This commit
reintroduces the document with fixes for those errors, as well as some
improvements to the wording and formatting.
The file was modifiedllvm/docs/ORCv2.rst
The file was addedllvm/docs/JITLink.rst
The file was modifiedllvm/docs/UserGuides.rst

Summary

  1. Fixed misspelled builder name for e-mail notifications. (details)
  2. More master to main updates (details)
  3. jenkins/jobs: Add timeout to the lnt-ctmark-* jobs (details)
Commit 388283cab6e6578f9e89d1ca122c24a922bbe280 by gkistanova
Fixed misspelled builder name for e-mail notifications.
The file was modifiedbuildbot/osuosl/master/config/status.py
Commit b8d41c307ba74e913a5b20446b51e349bbbe5045 by Azharuddin Mohammed
More master to main updates
The file was modifiedtasks/tasktool/README.md
The file was modifiedtasks/tasktool/tasktool/repos/git.py
The file was modifiedzorg/jenkins/inspect_log.py
The file was modifiedzorg/jenkins/jobs/util/make_pipeline.py
Commit c816513763961852ae753378e0525dd8e508d168 by Azharuddin Mohammed
jenkins/jobs: Add timeout to the lnt-ctmark-* jobs

This is so that these don't end up stuck and running forever in case of
any issues.
The file was modifiedzorg/jenkins/jobs/jobs/lnt-ctmark-aarch64-Os
The file was modifiedzorg/jenkins/jobs/jobs/lnt-ctmark-aarch64-O0-g
The file was modifiedzorg/jenkins/jobs/jobs/lnt-ctmark-aarch64-O3-flto
The file was modifiedzorg/jenkins/jobs/jobs/lnt-ctmark-aarch64-Oz