SuccessChanges

Summary

  1. [BreakFalseDeps] fix typos/grammar in documentation comment; NFC (details)
  2. [InstCombine] Precommit tests for D67351. (details)
  3. [InstCombine] Use SimplifyFMulInst to simplify multiply in fma. (details)
  4. [NFC][InstCombine] PR43251 - valid for other predicates too (details)
  5. [utils] Implement the llvm-locstats tool (details)
  6. [CMake] Don't pass all LLVM_COMPILE_FLAGS to the C compiler (details)
  7. [clang][codegen][NFC] Make test patterns more permissive. (details)
  8. [VectorUtils] Remove unused include. [NFC] (details)
  9. [ARM] auto-generate complete test checks; NFC (details)
  10. [X86] Add AVX partial dependency tests as noted on D67363 (details)
  11. [ARM] add test for BreakFalseDeps with minsize attribute; NFC (details)
  12. Revert "[utils] Implement the llvm-locstats tool" (details)
  13. [x86] add a test for BreakFalseDeps; NFC (details)
  14. Don't emit .gnu_pubnames when tuning for LLDB. (details)
  15. [RISCV] Add Option for Printing Architectural Register Names (details)
  16. Implement DW_OP_convert (details)
  17. AMDGPU/GlobalISel: First pass at attempting to legalize load/stores (details)
  18. [RISCV] Support llvm-objdump -M no-aliases and -M numeric (details)
  19. AMDGPU/GlobalISel: Legalize constant 32-bit loads (details)
  20. AMDGPU/GlobalISel: RegBankSelect for G_ZEXTLOAD/G_SEXTLOAD (details)
  21. [NFC][InstCombine][InstSimplify] PR43251 - and some patterns with offset (details)
  22. AMDGPU/GlobalISel: Select llvm.amdgcn.sffbh (details)
  23. AMDGPU/GlobalISel: Select cvt pk intrinsics (details)
  24. AMDGPU/GlobalISel: Select G_FABS/G_FNEG (details)
  25. [BPI] Adjust the probability for floating point unordered comparison (details)
  26. GlobalISel/TableGen: Handle REG_SEQUENCE patterns (details)
  27. [Function] Factor out GetCallEdgeForReturnAddress, NFC (details)
  28. [lldbtest] Add an "expected_cmd_failure" option to the filecheck helper (details)
  29. [NFC][InstSimplify] rewrite test added in r371537 to use non-null (details)
  30. [X86] Updated target specific selection dag code to conservatively check (details)
  31. Fix for PR43175: compiler crash when trying to emit noncapturable (details)
Commit df6a958dcb56daf59cbaeb7870d80f7a73854cda by spatel
[BreakFalseDeps] fix typos/grammar in documentation comment; NFC
llvm-svn: 371516
The file was modifiedllvm/lib/CodeGen/BreakFalseDeps.cpp
Commit 8886d0134eac27d9f4116bc39c7c4696321b9007 by flo
[InstCombine] Precommit tests for D67351.
llvm-svn: 371517
The file was modifiedllvm/test/Transforms/InstCombine/fma.ll
Commit 18a1f0818b659cee13865b4fad2648d85984a4ed by flo
[InstCombine] Use SimplifyFMulInst to simplify multiply in fma.
This allows us to fold fma's that multiply with 0.0. Also, the multiply
by 1.0 case is handled there as well. The fneg/fabs cases are not
handled by SimplifyFMulInst, so we need to keep them.
Reviewers: spatel, anemet, lebedev.ri
Reviewed By: spatel
Differential Revision: https://reviews.llvm.org/D67351
llvm-svn: 371518
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
The file was modifiedllvm/test/Transforms/InstCombine/fma.ll
Commit 7dfd0fb7f1cda3525d9c2fbdf680391b73479031 by lebedev.ri
[NFC][InstCombine] PR43251 - valid for other predicates too
llvm-svn: 371519
The file was modifiedllvm/test/Transforms/InstCombine/result-of-usub-is-non-zero-and-no-overflow.ll
Commit 54008972d17bf82ae36ccda7a2b20985c8a2821e by djordje.todorovic
[utils] Implement the llvm-locstats tool
The tool reports verbose output for the DWARF debug location coverage.
The llvm-locstats for each variable or formal parameter DIE computes
what percentage from the code section bytes, where it is in scope, it
has location description. The line 0 shows the number (and the
percentage) of DIEs with no location information, but the line 100 shows
the number (and the percentage) of DIEs where there is location
information in all code section bytes (where the variable or parameter
is in the scope). The line 50..59 shows the number (and the percentage)
of DIEs where the location information is in between 50 and 59
percentage of its scope covered.
The tool will be very useful for tracking improvements regarding the
"debugging optimized code" support with LLVM ecosystem.
Differential Revision: https://reviews.llvm.org/D66526
llvm-svn: 371520
The file was modifiedllvm/docs/CommandGuide/index.rst
The file was modifiedllvm/test/tools/llvm-dwarfdump/X86/locstats.ll
The file was addedllvm/utils/llvm-locstats/CMakeLists.txt
The file was addedllvm/utils/llvm-locstats/llvm-locstats.py
The file was addedllvm/docs/CommandGuide/llvm-locstats.rst
The file was modifiedllvm/CMakeLists.txt
Commit fef1cb1c971e3d38386462fe9640b9ba35bb448f by dave
[CMake] Don't pass all LLVM_COMPILE_FLAGS to the C compiler
GCC (unlike clang!) warns about C++ flags when compiling C.
https://reviews.llvm.org/D67171
llvm-svn: 371521
The file was modifiedllvm/cmake/modules/AddLLVM.cmake
Commit 30b5331df8803aa9a634f84f94b0b411e94854fc by courbet
[clang][codegen][NFC] Make test patterns more permissive.
See the discussion in:
http://lists.llvm.org/pipermail/llvm-commits/Week-of-Mon-20190909/692736.html
llvm-svn: 371522
The file was modifiedclang/test/CodeGenCXX/auto-var-init.cpp
Commit 1c3434543a0507b7e2078c931b2078a18d006d45 by flo
[VectorUtils] Remove unused include. [NFC]
Patch by Francesco Petrogalli <francesco.petrogalli@arm.com>
Reviewers: fhahn
Reviewed By: fhahn
Differential Revision: https://reviews.llvm.org/D67365
llvm-svn: 371523
The file was modifiedllvm/include/llvm/Analysis/VectorUtils.h
Commit 3b0b3def86e5d53bfe23e52888ddebfda5ede1a6 by spatel
[ARM] auto-generate complete test checks; NFC
llvm-svn: 371524
The file was modifiedllvm/test/CodeGen/ARM/a15-partial-update.ll
Commit 937ca68157437df375838053ff0e58b0294df94e by llvm-dev
[X86] Add AVX partial dependency tests as noted on D67363
llvm-svn: 371525
The file was modifiedllvm/test/CodeGen/X86/sqrt-partial.ll
Commit d2434e65fa9638f945874b7a473296330e2648bc by spatel
[ARM] add test for BreakFalseDeps with minsize attribute; NFC
llvm-svn: 371526
The file was modifiedllvm/test/CodeGen/ARM/a15-partial-update.ll
Commit b21cc626c9a7207f23f5f005453c58182721cabd by djordje.todorovic
Revert "[utils] Implement the llvm-locstats tool"
This reverts commit rL371520.
llvm-svn: 371527
The file was removedllvm/docs/CommandGuide/llvm-locstats.rst
The file was modifiedllvm/CMakeLists.txt
The file was removedllvm/utils/llvm-locstats/CMakeLists.txt
The file was removedllvm/utils/llvm-locstats/llvm-locstats.py
The file was modifiedllvm/test/tools/llvm-dwarfdump/X86/locstats.ll
The file was modifiedllvm/docs/CommandGuide/index.rst
Commit 8812157b11eac4f8ed578bc9cad19cdd826b3339 by spatel
[x86] add a test for BreakFalseDeps; NFC
As discussed in D67363
llvm-svn: 371528
The file was modifiedllvm/test/CodeGen/X86/sqrt-partial.ll
Commit f987f561fadc35fb597ce821b2deeb005f40bd77 by Adrian Prantl
Don't emit .gnu_pubnames when tuning for LLDB.
LLDB reads the various .apple* accelerator tables (and in the near
future: the DWARF 5 accelerator tables) which should make
.gnu_pubnames redundant. This changes the Clang driver to no longer pass
-ggnu-pubnames when tuning for LLDB.
Thanks to David Blaikie for pointing this out!
http://lists.llvm.org/pipermail/llvm-commits/Week-of-Mon-20190422/thread.html#646062
rdar://problem/50142073
Differential Revision: https://reviews.llvm.org/D67373
llvm-svn: 371530
The file was modifiedclang/test/Driver/debug-options.c
The file was modifiedclang/lib/Driver/ToolChains/Clang.cpp
Commit 6b877f6aac3d8e569e74953f0310323c2882619c by selliott
[RISCV] Add Option for Printing Architectural Register Names
Summary: This is an option primarily to use during testing. Instead of
always printing registers using their ABI names, this allows a user to
request they are printed with their architectural name.
This is then used in the register constraint tests to ensure the mapping
between architectural and abi names is correct.
Reviewers: asb, luismarques
Reviewed By: asb
Subscribers: pzheng, hiraditya, rbar, johnrusso, simoncook, apazos,
sabuasal, niosHD, kito-cheng, shiva0217, jrtc27, MaskRay, zzheng,
edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX,
jocewei, psnobl, benna, Jim, s.egerton, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D65950
llvm-svn: 371531
The file was modifiedllvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.h
The file was addedllvm/test/MC/RISCV/numeric-reg-names-f.s
The file was modifiedllvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
The file was addedllvm/test/MC/RISCV/numeric-reg-names.s
The file was addedllvm/test/MC/RISCV/numeric-reg-names-d.s
Commit 9b23df63ecd9f23bb8877783d30d1a49e895cf7c by Adrian Prantl
Implement DW_OP_convert
This patch adds basic support for DW_OP_convert[1] for integer types.
Recent versions of LLVM's optimizer may insert this opcode into DWARF
expressions. DW_OP_convert is effectively a type cast operation that
takes a reference to a base type DIE (or zero) and then casts the value
at the top of the DWARF stack to that type. Internally this works by
changing the bit size of the APInt that is used as backing storage for
LLDB's DWARF stack.
I managed to write a unit test for this by implementing a mock YAML
object file / module that takes debug info sections in yaml2obj format.
[1] Typed DWARF stack.
http://www.dwarfstd.org/ShowIssue.php?issue=140425.1
<rdar://problem/48167864>
Differential Revision: https://reviews.llvm.org/D67369
llvm-svn: 371532
The file was modifiedlldb/include/lldb/Utility/Scalar.h
The file was modifiedlldb/source/Expression/DWARFExpression.cpp
The file was modifiedlldb/unittests/Expression/DWARFExpressionTest.cpp
The file was modifiedlldb/include/lldb/Core/Section.h
The file was modifiedlldb/source/Core/Section.cpp
The file was modifiedlldb/source/Utility/Scalar.cpp
The file was modifiedlldb/unittests/Utility/ScalarTest.cpp
Commit c0ceca5883060bfaf501007d76640821d825828b by Matthew.Arsenault
AMDGPU/GlobalISel: First pass at attempting to legalize load/stores
There's still a lot more to do, but this handles decomposing due to
alignment. I've gotten it to the point where nothing crashes or infinite
loops the legalizer.
llvm-svn: 371533
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-local.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-private.mir
The file was modifiedllvm/lib/Target/AMDGPU/SIISelLowering.h
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir
The file was modifiedllvm/lib/Target/AMDGPU/SIISelLowering.cpp
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-global.mir
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-local-128.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store.mir
The file was removedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-local.mir
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-constant.mir
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-flat.mir
Commit d57de491be0ba4fea88566bc0803773c53dc8414 by selliott
[RISCV] Support llvm-objdump -M no-aliases and -M numeric
Summary: Now that llvm-objdump allows target-specific options, we match
the
`no-aliases` and `numeric` options for RISC-V, as supported by GNU
objdump.
This is done by overriding the variables used for the command-line
options, so that the command-line options are still supported.
This patch updates all tests using `llvm-objdump -riscv-no-aliases` to
use
`llvm-objdump -M no-aliases`.
Reviewers: luismarques, asb
Reviewed By: luismarques, asb
Subscribers: pzheng, hiraditya, rbar, johnrusso, simoncook, apazos,
sabuasal, niosHD, kito-cheng, shiva0217, jrtc27, MaskRay, zzheng,
edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX,
jocewei, psnobl, benna, Jim, s.egerton, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D66139
llvm-svn: 371534
The file was modifiedllvm/test/MC/RISCV/rv32d-valid.s
The file was modifiedllvm/test/MC/RISCV/rv32c-valid.s
The file was modifiedllvm/test/MC/RISCV/rv32i-valid.s
The file was modifiedllvm/test/MC/RISCV/compress-cjal.s
The file was modifiedllvm/test/MC/RISCV/rva-aliases-valid.s
The file was modifiedllvm/test/MC/RISCV/cnop.s
The file was modifiedllvm/test/MC/RISCV/rv32i-aliases-valid.s
The file was modifiedllvm/test/MC/RISCV/rv64c-hints-valid.s
The file was modifiedllvm/test/MC/RISCV/rv64f-aliases-valid.s
The file was modifiedllvm/test/MC/RISCV/rv64a-valid.s
The file was modifiedllvm/test/MC/RISCV/rv32m-valid.s
The file was modifiedllvm/test/MC/RISCV/rv64d-valid.s
The file was modifiedllvm/test/MC/RISCV/rv32f-valid.s
The file was modifiedllvm/test/MC/RISCV/option-mix.s
The file was modifiedllvm/test/MC/RISCV/rv32dc-valid.s
The file was modifiedllvm/test/MC/RISCV/rv32e-invalid.s
The file was modifiedllvm/test/MC/RISCV/rv32-relaxation.s
The file was modifiedllvm/test/CodeGen/RISCV/compress-inline-asm.ll
The file was modifiedllvm/test/MC/RISCV/compress-rv32d.s
The file was modifiedllvm/test/MC/RISCV/csr-aliases.s
The file was modifiedllvm/test/MC/RISCV/rv32a-valid.s
The file was modifiedllvm/test/MC/RISCV/priv-valid.s
The file was modifiedllvm/test/MC/RISCV/rv64dc-valid.s
The file was modifiedllvm/test/MC/RISCV/rv64m-valid.s
The file was modifiedllvm/test/MC/RISCV/numeric-reg-names-d.s
The file was modifiedllvm/test/MC/RISCV/rvi-aliases-valid.s
The file was modifiedllvm/test/MC/RISCV/rv32fc-aliases-valid.s
The file was modifiedllvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
The file was modifiedllvm/test/MC/RISCV/rv64i-valid.s
The file was modifiedllvm/test/MC/RISCV/rvc-hints-valid.s
The file was modifiedllvm/test/MC/RISCV/rvf-aliases-valid.s
The file was modifiedllvm/test/MC/RISCV/numeric-reg-names.s
The file was modifiedllvm/test/MC/RISCV/fixups.s
The file was modifiedllvm/test/MC/RISCV/rvd-aliases-valid.s
The file was modifiedllvm/test/MC/RISCV/rv32e-valid.s
The file was modifiedllvm/test/MC/RISCV/compress-rv32f.s
The file was modifiedllvm/test/MC/RISCV/rv32c-aliases-valid.s
The file was modifiedllvm/test/MC/RISCV/rv64a-aliases-valid.s
The file was modifiedllvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.h
The file was modifiedllvm/test/MC/RISCV/align.s
The file was modifiedllvm/test/MC/RISCV/rv32fc-valid.s
The file was modifiedllvm/test/MC/RISCV/rvdc-aliases-valid.s
The file was modifiedllvm/test/MC/RISCV/option-rvc.s
The file was modifiedllvm/test/MC/RISCV/rv64-relaxation.s
The file was modifiedllvm/test/MC/RISCV/rv64c-aliases-valid.s
The file was modifiedllvm/test/MC/RISCV/rv64i-aliases-valid.s
The file was modifiedllvm/test/MC/RISCV/compress-rv32i.s
The file was modifiedllvm/test/MC/RISCV/rv64f-valid.s
The file was modifiedllvm/test/CodeGen/RISCV/compress.ll
The file was modifiedllvm/test/CodeGen/RISCV/option-rvc.ll
The file was modifiedllvm/test/MC/RISCV/rv64d-aliases-valid.s
The file was modifiedllvm/test/MC/RISCV/rvc-aliases-valid.s
The file was modifiedllvm/test/MC/RISCV/rv32c-only-valid.s
The file was modifiedllvm/test/MC/RISCV/fixups-compressed.s
The file was modifiedllvm/test/CodeGen/RISCV/option-norvc.ll
The file was modifiedllvm/test/MC/RISCV/compress-rv64i.s
The file was modifiedllvm/test/MC/RISCV/rv64c-valid.s
The file was modifiedllvm/test/MC/RISCV/numeric-reg-names-f.s
Commit ad6a8b83cdc35019cc0431286f3fbacf7d184781 by Matthew.Arsenault
AMDGPU/GlobalISel: Legalize constant 32-bit loads
Legalize by casting to a 64-bit constant address. This isn't how the DAG
implements it, but it should.
llvm-svn: 371535
The file was modifiedllvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-constant-32bit.mir
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h
Commit da027275c666183efb9434ece31ef0d92fcf9f2b by Matthew.Arsenault
AMDGPU/GlobalISel: RegBankSelect for G_ZEXTLOAD/G_SEXTLOAD
llvm-svn: 371536
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sextload.mir
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-zextload.mir
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
Commit 880657c97c394eebd35c17db878c09f1180030fe by lebedev.ri
[NFC][InstCombine][InstSimplify] PR43251 - and some patterns with offset
!= 0
https://rise4fun.com/Alive/21b
llvm-svn: 371537
The file was addedllvm/test/Transforms/InstSimplify/result-of-usub-by-nonzero-is-non-zero-and-no-overflow.ll
The file was modifiedllvm/test/Transforms/InstCombine/result-of-usub-is-non-zero-and-no-overflow.ll
Commit 37d1bda4f6b59c38c35334a86fc8430343db7925 by Matthew.Arsenault
AMDGPU/GlobalISel: Select llvm.amdgcn.sffbh
llvm-svn: 371538
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstrInfo.td
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.sffbh.mir
The file was modifiedllvm/lib/Target/AMDGPU/VOP1Instructions.td
Commit 7df5b3fd26243a80d97382fdc09ce0374ab98d87 by Matthew.Arsenault
AMDGPU/GlobalISel: Select cvt pk intrinsics
llvm-svn: 371539
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cvt.pknorm.u16.mir
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cvt.pk.u16.mir
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cvt.pk.i16.mir
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUGISel.td
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstrInfo.td
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cvt.pknorm.i16.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cvt.pkrtz.mir
Commit e1895aba3da01df442253bf048e38371377db15e by Matthew.Arsenault
AMDGPU/GlobalISel: Select G_FABS/G_FNEG
f64 doesn't work yet because tablegen currently doesn't handlde
REG_SEQUENCE.
This does regress some multi use VALU fneg cases since now the immediate
remains in an SGPR, and more moves are used for legalizing the xor. This
is a SIFixSGPRCopies deficiency.
llvm-svn: 371540
The file was modifiedllvm/lib/Target/AMDGPU/SIInstructions.td
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fcanonicalize.mir
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fabs.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fsub.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/fneg-combines.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fabs.mir
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fneg.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fneg.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/fneg.ll
Commit b329e0728b3eda7a1c754931e5c174b2b7ae51b3 by carrot
[BPI] Adjust the probability for floating point unordered comparison
Since NaN is very rare in normal programs, so the probability for
floating point unordered comparison should be extremely small. Current
probability is 3/8, it is too large, this patch changes it to a tiny
number.
Differential Revision: https://reviews.llvm.org/D65303
llvm-svn: 371541
The file was modifiedllvm/lib/Analysis/BranchProbabilityInfo.cpp
The file was modifiedllvm/test/CodeGen/SystemZ/call-05.ll
The file was addedllvm/test/Analysis/BranchProbabilityInfo/fcmp.ll
Commit 4a23ae5e78798662c07c94cc708fd70fd5ae88f9 by Matthew.Arsenault
GlobalISel/TableGen: Handle REG_SEQUENCE patterns
The scalar f64 patterns don't work yet because they fail on multiple
results from the unused implicit def of scc in the result bit operation.
llvm-svn: 371542
The file was addedllvm/test/TableGen/GlobalISelEmitterRegSequence.td
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fabs.mir
The file was modifiedllvm/utils/TableGen/GlobalISelEmitter.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fneg.mir
The file was modifiedllvm/lib/Target/AMDGPU/SIInstructions.td
Commit ff02109ad47af387839f3163168382273fcec05b by Vedant Kumar
[Function] Factor out GetCallEdgeForReturnAddress, NFC
Finding the call edge in a function which corresponds to a particular
return address is a generic/useful operation.
llvm-svn: 371543
The file was modifiedlldb/include/lldb/Symbol/Function.h
The file was modifiedlldb/source/Symbol/Function.cpp
The file was modifiedlldb/source/Target/StackFrameList.cpp
Commit 3ef7dbd6650d53af79dedbfcd3c85a96b29c96bb by Vedant Kumar
[lldbtest] Add an "expected_cmd_failure" option to the filecheck helper
llvm-svn: 371544
The file was modifiedlldb/packages/Python/lldbsuite/test/lldbtest.py
Commit 870ffe3cee6398f5c576e230765424f6f89d2143 by lebedev.ri
[NFC][InstSimplify] rewrite test added in r371537 to use non-null
pointer instead
I only want to ensure that %offset is non-zero there, it doesn't matter
how that info is conveyed. As filed in PR43267, the assumption way does
not work.
llvm-svn: 371546
The file was modifiedllvm/test/Transforms/InstSimplify/result-of-usub-by-nonzero-is-non-zero-and-no-overflow.ll
Commit a9beacbac8d22f2b796130766ff7f8c93af131f2 by listmail
[X86] Updated target specific selection dag code to conservatively check
for isAtomic in addition to isVolatile
See D66309 for context.
This is the first sweep of x86 target specific code to add isAtomic
bailouts where appropriate. The intention here is to have the switch
from AtomicSDNode to LoadSDNode/StoreSDNode be close to NFC; that is,
I'm not looking to allow additional optimizations at this time.
Sorry for the lack of tests.  As discussed in the review, most of these
are vector tests (for which atomicity is not well defined) and I
couldn't figure out to exercise the anyextend cases which aren't vector
specific.
Differential Revision: https://reviews.llvm.org/D66322
llvm-svn: 371547
The file was modifiedllvm/lib/Target/X86/X86InstrInfo.td
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
The file was modifiedllvm/lib/Target/X86/X86ISelDAGToDAG.cpp
Commit b5890a329a08715f1974f5f46f1205f2ca1de41e by a.bataev
Fix for PR43175: compiler crash when trying to emit noncapturable
constant.
If the constexpr variable is partially initialized, the initializer can
be emitted as the structure, not as an array, because of some early
optimizations. The llvm variable gets the type from this constant and,
thus, gets the type which is pointer to struct rather than pointer to an
array. We need to convert this type to be truely array, otherwise it may
lead to the compiler crash when trying to emit array subscript
expression.
llvm-svn: 371548
The file was modifiedclang/lib/CodeGen/CGExpr.cpp
The file was addedclang/test/OpenMP/constexpr_partial_array.cpp