1. [AMDGPU] Limit runs of fixLdsBranchVmemWARHazard (details)
  2. [mlir][Linalg] Make printer/parser have the same behavior. (details)
  3. Adding some of the documents for C11. (details)
  4. [TLI] SimplifyDemandedVectorElts(): handle SCALAR_TO_VECTOR(EXTRACT_VECTOR_ELT(?, 0)) (details)
  5. [dfsan] Add stack-trace printing functions to dfsan interface (details)
  6. Allow signposts to take advantage of deferred string substitution (details)
  7. [HWASan] Enable globals support for LAM. (details)
  8. [libc] Add hardware implementations of x86_64 sqrt functions. (details)
  9. [Hexagon] Add HVX and control register names to Hexagon target (details)
Commit e0c382a9d5a0e2689b97186736ebc82e17c5f822 by Piotr Sobczak
[AMDGPU] Limit runs of fixLdsBranchVmemWARHazard

The code in fixLdsBranchVmemWARHazard looks for patterns of a vmem/lds
access followed by a branch, followed by an lds/vmem access.

The handling of the hazard requires an arbitrary number of instructions
to process. In the worst case where a function has a vmem access, but no lds
accesses, all instructions are examined only to conclude that the hazard
cannot occur.

Add the pre-processing stage which detects if there is both lds and vmem
present in the function and only then does the more costly search.

This patch significantly improves compilation time in the cases the hazard
cannot happen. In one pathological case I looked at IsHazardInst is needlesly
called 88.6 milions times.

The numbers could also be improved by introducing a map around the
inner calls to ::getWaitStatesSince in fixLdsBranchVmemWARHazard, but
nothing will beat not running fixLdsBranchVmemWARHazard at all in the cases
detected by shouldRunLdsBranchVmemWARHazardFixup().

Differential Revision:
The file was modifiedllvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
The file was modifiedllvm/lib/Target/AMDGPU/GCNHazardRecognizer.h
Commit e3bc4dbe8e75faf13798028fcb7710675d8c05ed by hanchung
[mlir][Linalg] Make printer/parser have the same behavior.

The parser of generic op did not recognize the output from mlir-opt when there
are multiple outputs. One would wrap the result types with braces, and one would
not. The patch makes the behavior the same.

Reviewed By: mravishankar

Differential Revision:
The file was modifiedmlir/test/Dialect/Linalg/vectorization.mlir
The file was modifiedmlir/test/Dialect/Linalg/roundtrip.mlir
The file was modifiedmlir/test/Dialect/Linalg/bufferize.mlir
The file was modifiedmlir/lib/Dialect/Linalg/IR/LinalgOps.cpp
The file was modifiedmlir/test/Dialect/Linalg/invalid.mlir
The file was modifiedmlir/test/Dialect/Linalg/canonicalize.mlir
Commit 00dbf8c83218829633b9f2ec1ee94a1f3b8dd29c by aaron
Adding some of the documents for C11.

This is not the complete set of language-related documents for C11, but
is about 75% complete.
The file was modifiedclang/www/c_status.html
Commit 585e65d3307f5f081b32b21421f2a0b84eccd1b5 by lebedev.ri
[TLI] SimplifyDemandedVectorElts(): handle SCALAR_TO_VECTOR(EXTRACT_VECTOR_ELT(?, 0))

Iff we have `SCALAR_TO_VECTOR` (and we demand it's only defined 0'th element),
and said scalar was produced by `EXTRACT_VECTOR_ELT` from the 0'th element
of some vector, then we can just continue traversal into said source vector.

This comes up in X86 vector uniform shift lowering.

Reviewed By: RKSimon

Differential Revision:
The file was modifiedllvm/test/CodeGen/X86/vector-fshr-rot-512.ll
The file was modifiedllvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
The file was modifiedllvm/test/CodeGen/X86/vector-fshr-rot-256.ll
The file was modifiedllvm/test/CodeGen/X86/vector-fshl-rot-256.ll
The file was modifiedllvm/test/CodeGen/X86/vector-fshl-rot-512.ll
The file was modifiedllvm/test/CodeGen/X86/vector-rotate-256.ll
The file was modifiedllvm/test/CodeGen/X86/vector-fshl-256.ll
The file was modifiedllvm/test/CodeGen/X86/vector-fshl-512.ll
The file was modifiedllvm/test/CodeGen/X86/vector-fshr-256.ll
The file was modifiedllvm/test/CodeGen/X86/vector-fshr-512.ll
Commit 98504959a6f114866cbf523e44d2f45e755626d5 by gbalats
[dfsan] Add stack-trace printing functions to dfsan interface

Reviewed By: stephan.yichao.zhao

Differential Revision:
The file was modifiedcompiler-rt/lib/dfsan/dfsan.cpp
The file was modifiedcompiler-rt/include/sanitizer/dfsan_interface.h
The file was modifiedcompiler-rt/lib/dfsan/done_abilist.txt
The file was addedcompiler-rt/test/dfsan/stack_trace.c
Commit 03841edde7eee21d1d450041ab9a113a7e1be869 by Adrian Prantl
Allow signposts to take advantage of deferred string substitution

One nice feature of the os_signpost API is that format string
substitutions happen in the consumer, not the logging
application. LLVM's current Signpost class doesn't take advantage of
this though and instead always uses a static "Begin/End %s" format

This patch uses variadic macros to allow the API to be used as
intended. Unfortunately, the primary use-case I had in mind (the
LLDB_SCOPED_TIMER() macro) does not get much better from this, because
__PRETTY_FUNCTION__ is *not* a macro, but a static string, so
signposts created by LLDB_SCOPED_TIMER() still use a static "%s"
format string. At least LLDB_SCOPED_TIMERF() works as intended.

This reapplies the previsously reverted patch with additional MachO.h
macro #undefs.

Differential Revision:
The file was modifiedllvm/lib/Support/Signposts.cpp
The file was modifiedllvm/lib/Support/Timer.cpp
The file was modifiedllvm/include/llvm/Support/Signposts.h
The file was modifiedlldb/source/Utility/Timer.cpp
The file was modifiedlldb/include/lldb/Utility/Timer.h
The file was modifiedlldb/source/Plugins/ObjectFile/Mach-O/ObjectFileMachO.cpp
Commit b87894a1d28f3819e38c11ce1fdf05113ac5ca34 by mascasa
[HWASan] Enable globals support for LAM.

Reviewed By: vitalybuka

Differential Revision:
The file was modifiedllvm/lib/Transforms/Instrumentation/HWAddressSanitizer.cpp
The file was addedllvm/test/Instrumentation/HWAddressSanitizer/X86/globals.ll
The file was modifiedcompiler-rt/test/hwasan/TestCases/global.c
Commit a58b2827feceaa27193318a12e3a06893eabdcb6 by sivachandra
[libc] Add hardware implementations of x86_64 sqrt functions.
The file was addedlibc/src/math/x86_64/sqrtl.cpp
The file was addedlibc/src/math/x86_64/sqrt.cpp
The file was modifiedlibc/src/math/x86_64/CMakeLists.txt
The file was addedlibc/src/math/x86_64/sqrtf.cpp
Commit 0577f4b1789eff410f5b28434a4f7854a50dc639 by kparzysz
[Hexagon] Add HVX and control register names to Hexagon target
The file was modifiedclang/lib/Basic/Targets/Hexagon.cpp
The file was addedclang/test/CodeGen/hexagon-inline-asm-reg-names.c