Changes

Summary

  1. [SimplifyCFG] Improve store speculation check (details)
  2. AArch64: support i128 (& larger) returns in GlobalISel (details)
  3. [ARM] Ensure correct regclass in distributing postinc (details)
  4. [AMDGPU] Fix MMO for raw/struct buffer access with non-constant offset (details)
  5. [AMDGPU] Pre-commit global-isel test case for D106451 (details)
  6. [AMDGPU][GISel] Fix MMO for raw/struct buffer access with non-constant offset (details)
  7. [llvm-readobj] Display multiple function names for stack size entries (details)
  8. [OpenCL] Change default standard version to CL1.2 (details)
  9. [SLP]Fix costs calculations. (details)
  10. [LV] Add test to store a first-order rec via interleave group. (details)
  11. [InstrRef][AArch64][1/4] Accept constant physreg variable locations (details)
  12. [Analyzer][solver][NFC] print constraints deterministically (ordered by their string representation) (details)
  13. Simplify away some SmallVector copies. NFCI. (details)
  14. [IR] Consider non-willreturn as side effect (PR50511) (details)
  15. [libc++][ci] Detect not committed generated files. (details)
  16. Recommit "[VPlan] Add recipe for first-order rec phis, make splicing explicit." (details)
  17. [SystemZ] Add support for new cpu architecture - arch14 (details)
  18. [Clang][OpenMP] Remove the mandatory flush for capture for OpenMP 5.1 (details)
  19. [AArch64][SVE] Break false dependencies for inactive lanes of unary operations (details)
  20. [LV] Don't assume isScalarAfterVectorization if one of the uses needs widening. (details)
  21. [MergeICmps] Separate out BCECmp and use Optional (NFC) (details)
  22. [SimplifyLibCalls] reduce code duplication; NFC (details)
  23. [SimplifyLibCalls] avoid crash on pointer math (details)
  24. [libc++][NFC] Change a few instances of > > to >> in C++20 code (details)
  25. [SVE] Use reg+reg addressing mode for immediate offsets. (details)
  26. [AsmParser] Remove MDRef (NFC) (details)
  27. [MergeICmps] Try to fix MSVC build failure (details)
  28. [yaml2obj][MachO] Rename PayloadString to Content (details)
  29. [llvm-objcopy] Drop GRP_COMDAT if the group signature is localized (details)
  30. [MergeICmps] Collect block instructions once (NFC) (details)
  31. [clang][pp] adds '#pragma include_instead' (details)
  32. [LV] Remove assert that VF cannot be scalable in setCostBasedWideningDecision. (details)
  33. [Analysis] Fix getOrderedReductionCost to call target's getArithmeticInstrCost implementation (details)
  34. [libc++] Add range_size_t (details)
  35. [PowerPC] Change altivec indexed load/store builtins argument type (details)
  36. [DebugInfo] Correctly update debug users of SSA values in tail duplication (details)
  37. [LAA] Remove RuntimeCheckingPtrGroup::RtCheck member (NFC). (details)
Commit ffb3277b0036909a8e622d5758a1e2850eabfd19 by nikita.ppv
[SimplifyCFG] Improve store speculation check

isSafeToSpeculateStore() looks for a preceding store to the same
location to make sure that introducing a new store of the same
value is safe. It currently bails on intervening mayHaveSideEffect()
instructions. However, I believe just checking mayWriteToMemory()
is sufficient there -- we just need to make sure that we know which
value was stored, we don't care if we can unwind in the meantime.

While looking into this, I started having some doubts about the
correctness of the transform with regard to thread safety. While
we don't try to hoist non-simple stores, I believe we also need
to make sure that the preceding store is simple as well. Otherwise
we could introduce a spurious non-atomic write after an atomic write
-- under our memory model this would result in a subsequent undef
atomic read, even if the second write stores the same value as the
first.

Example: https://alive2.llvm.org/ce/z/q_3YAL

Differential Revision: https://reviews.llvm.org/D106742
The file was modifiedllvm/lib/Transforms/Utils/SimplifyCFG.cpp
The file was modifiedllvm/test/Transforms/SimplifyCFG/speculate-store.ll
Commit a487a49acc5a172909d706ffc43240ced1ac0693 by Tim Northover
AArch64: support i128 (& larger) returns in GlobalISel
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll
The file was addedllvm/test/CodeGen/AArch64/GlobalISel/translate-ret.ll
The file was modifiedllvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp
The file was modifiedllvm/test/CodeGen/AArch64/arm64-subvector-extend.ll
Commit 010f8e305705acb5128f409256e7f22ff3adc780 by david.green
[ARM] Ensure correct regclass in distributing postinc

The register class required for some MVE loads/stores is more
constrained than the register we use when creating postinc. Make sure we
constrain the register class to keep the code correct.
The file was modifiedllvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
The file was modifiedllvm/test/CodeGen/Thumb2/mve-postinc-distribute.mir
Commit 9ac10658aeda44d8a90ae372c1478610d143c8bb by jay.foad
[AMDGPU] Fix MMO for raw/struct buffer access with non-constant offset

Codegen for the raw/struct buffer access intrinsics would update the
offset in the MMO to reflect the combined offset, if it was known to be
constant. If the combined offset was not known to be constant, or if
there was an index, it would set the offset in the MMO to 0. This is
unsafe because it makes it look like the access does not alias with
another access with a fixed non-zero offset.

Fix these cases by setting the pointer in the MMO to null, to reflect
the fact that we do not have any known IR value pointer + constant
offset for the access.

Differential Revision: https://reviews.llvm.org/D106284
The file was modifiedllvm/lib/Target/AMDGPU/SIISelLowering.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/buffer-intrinsics-mmo-offsets.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/buffer-schedule.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/extract_subvector_vec4_vec3.ll
Commit 683b9ed0d593f249e992bed63768986b37b49dbb by jay.foad
[AMDGPU] Pre-commit global-isel test case for D106451

This test case shows the scheduler wrongly reordering two buffer
accesses that might alias.
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/buffer-schedule.ll
Commit 59f6865231ff7d233e3728b21de2e5aa35189eb3 by jay.foad
[AMDGPU][GISel] Fix MMO for raw/struct buffer access with non-constant offset

Codegen for the raw/struct buffer access intrinsics would update the
offset in the MMO to reflect the combined offset, if it was known to be
constant. If the combined offset was not known to be constant, or if
there was an index, it would set the offset in the MMO to 0. This is
unsafe because it makes it look like the access does not alias with
another access with a fixed non-zero offset.

Fix these cases by setting the pointer in the MMO to null, to reflect
the fact that we do not have any known IR value pointer + constant
offset for the access.

D106284 did this for SelectionDAG. This is the corresponding fix for
GlobalISel.

Differential Revision: https://reviews.llvm.org/D106451
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.store.i8.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.buffer.load.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.atomic.cmpswap.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.load.f16.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.atomic.fadd.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.store.format.f32.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.store.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.tbuffer.load.f16.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.format.f32.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.atomic.add.ll
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.atomic.fadd.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.format.f16.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.buffer.store.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.tbuffer.load.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.store.f16.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.raw.buffer.load.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.format.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.atomic.add.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.load.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.format.f16.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.format.f16.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.atomic.cmpswap.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.format.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/buffer-schedule.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.store.format.f16.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.store.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.ll
Commit 87ed73fe6e01591998eed0dd769353f88919d056 by gbreynoo
[llvm-readobj] Display multiple function names for stack size entries

The current implementation of displaying .stack_size information
presumes that each entry represents a single function but this is not
always the case. For example with the use of ICF multiple functions can
be represented with the same code, meaning that the address found in a
.stack_size entry corresponds to multiple function symbols.
This change allows multiple function names to be displayed when
appropriate.

Differential Revision: https://reviews.llvm.org/D105884
The file was modifiedllvm/test/Object/BPF/yaml2obj-elf-bpf-rel.yaml
The file was modifiedllvm/tools/llvm-readobj/ELFDumper.cpp
The file was modifiedllvm/test/tools/llvm-readobj/ELF/stack-sizes.test
Commit 81600160b3f926746d02c52003d81180941fe9d0 by anastasia.stulova
[OpenCL] Change default standard version to CL1.2

Set default version for OpenCL C to 1.2. This means that the
absence of any standard flag will be equivalent to passing
'-cl-std=CL1.2'.

Note that this patch also fixes incorrect version check for
the pointer to pointer kernel arguments diagnostic and
atomic test.

Differential Revision: https://reviews.llvm.org/D106504
The file was modifiedclang/test/Parser/opencl-cl20.cl
The file was modifiedclang/test/SemaOpenCL/fp64-fp16-options.cl
The file was modifiedclang/test/Preprocessor/predefined-macros.c
The file was modifiedclang/lib/Frontend/CompilerInvocation.cpp
The file was modifiedclang/test/CodeGenOpenCL/spir_version.cl
The file was modifiedclang/test/Parser/opencl-storage-class.cl
The file was modifiedclang/test/SemaOpenCL/func.cl
The file was modifiedclang/test/Parser/opencl-atomics-cl20.cl
The file was modifiedclang/lib/Sema/SemaDecl.cpp
Commit 6ca48efcf6e16adfcf33688d86de7bd2bb75a49a by a.bataev
[SLP]Fix costs calculations.

Need to fix several cost-related problems. The final type may be defined
incorrectly because of to early definition (we may end up with the wider
type), the CommonCost should not be redefined in ExtractElements
cost related calculations and the shuffle of the final insertelements
vectors should be calculated as a cost of single vector permutations
+ costs of two vector permutations for other n-1 incoming vectors.

Differential Revision: https://reviews.llvm.org/D106578
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/vec_list_bias.ll
The file was modifiedllvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/vec_list_bias-inseltpoison.ll
Commit 93664503be6b3f47269cf617f8c46b6ce95f8076 by flo
[LV] Add test to store a first-order rec via interleave group.

This is a reduced version of the reproducer from
https://bugs.chromium.org/p/chromium/issues/detail?id=1232798#c2
The file was addedllvm/test/Transforms/LoopVectorize/AArch64/interleaved-store-of-first-order-recurrence.ll
Commit f86694cb808f22253e00742ccd279760ef0c688d by jeremy.morse
[InstrRef][AArch64][1/4] Accept constant physreg variable locations

Late in SelectionDAG we join up instruction numbers with their defining
instructions, if it couldn't be done during the main part of SelectionDAG.
One exception is function arguments, where we have to point a DBG_PHI
instruction at the incoming live register, as they don't have a defining
instruction. This patch adds another exception, for constant physregs, like
aarch64 has.

It may seem wasteful to use two instructions where we could use a single
DBG_VALUE, however the whole point of instruction referencing is to
decouple the identification of values from the specification of where
variable location ranges start.

(Part of my aarch64 work to ease adoption of  instruction referencing, as
in the meta comment on D104520)

Differential Revision: https://reviews.llvm.org/D104520
The file was addedllvm/test/DebugInfo/AArch64/instr-ref-const-physreg.ll
The file was modifiedllvm/lib/CodeGen/MachineFunction.cpp
Commit 4761321d49db01dce1e308f900add033cc26fb47 by gabor.marton
[Analyzer][solver][NFC] print constraints deterministically (ordered by their string representation)

This change is an extension to D103967 where I added dump methods for
(dis)equality classes of the State. There, the (dis)equality classes and their
contents are dumped in an ordered fashion, they are ordered based on their
string representation. This is very useful once we start to use FileCheck to
test the State dump in certain tests.

Differential Revision: https://reviews.llvm.org/D106642
The file was modifiedclang/lib/StaticAnalyzer/Core/RangeConstraintManager.cpp
Commit 404f0d4f7cc7b7497c9725c6c6f20b21df8611bb by benny.kra
Simplify away some SmallVector copies. NFCI.

The lifetime of the initializer list is the full expression, so we can
skip storing it in a temporary vector.
The file was modifiedllvm/include/llvm/IR/DerivedTypes.h
The file was modifiedllvm/include/llvm/IR/Constants.h
Commit 33146857e9840a92840d48bbc3483e34ea545fc7 by nikita.ppv
[IR] Consider non-willreturn as side effect (PR50511)

This adjusts mayHaveSideEffect() to return true for !willReturn()
instructions. Just like other side-effects, non-willreturn calls
(aka "divergence") cannot be removed and cannot be reordered relative
to other side effects. This fixes a number of bugs where
non-willreturn calls are either incorrectly dropped or moved. In
particular, it also fixes the last open problem in
https://bugs.llvm.org/show_bug.cgi?id=50511.

I performed a cursory review of all current mayHaveSideEffect()
uses, which convinced me that these are indeed the desired default
semantics. Places that do not want to consider non-willreturn as a
sideeffect generally do not want mayHaveSideEffect() semantics at
all. I identified two such cases, which are addressed by D106591
and D106742. Finally, there is a use in SCEV for which we don't
really have an appropriate API right now -- what it wants is
basically "would this be considered forward progress". I've just
spelled out the previous semantics there.

Differential Revision: https://reviews.llvm.org/D106749
The file was modifiedllvm/include/llvm/IR/Instruction.h
The file was modifiedllvm/lib/IR/Instruction.cpp
The file was modifiedllvm/test/Transforms/SCCP/calltest.ll
The file was modifiedllvm/test/Transforms/LoopDeletion/noop-loops-with-subloops.ll
The file was modifiedllvm/test/Transforms/LICM/sinking.ll
The file was modifiedllvm/lib/Transforms/Scalar/ADCE.cpp
The file was modifiedllvm/lib/Analysis/DemandedBits.cpp
The file was modifiedllvm/lib/Analysis/ScalarEvolution.cpp
Commit 1139fd4270c7462a4bce8e1e91e6be174dcae88f by koraq
[libc++][ci] Detect not committed generated files.

The Generated output CI job only tests for modified files. This job
should also fail the generated output contains new files.

It would be possible to test modified and untracked files in one
execution of `git ls-files`. However the diff is stored as an artifact
so the execution of `git diff` would still be required.

Discussion: Would it be better to do `git ls-files -om` and remove the
excution of
`! grep -q '^--- a' ${BUILD_DIR}/generated_output.patch || false` ?
(Obviously then the name `generated_output.untracked` should change to
something like `generated_output.status`)

Reviewed By: #libc, ldionne

Differential Revision: https://reviews.llvm.org/D106534
The file was modifiedlibcxx/utils/ci/run-buildbot
The file was modifiedlibcxx/utils/ci/buildkite-pipeline.yml
Commit 7a1e73f0b9fcfec0e90aff735f0ac4cfb6b9ec41 by flo
Recommit "[VPlan] Add recipe for first-order rec phis, make splicing explicit."

This reverts the revert commit b1777b04dc4b1a9fee0e7effa7e177892ab32ef0.

The patch originally got reverted due to a crash:
https://bugs.chromium.org/p/chromium/issues/detail?id=1232798#c2

The underlying issue was that we were not using the stored values from
the modified memory recipes, but the out-of-date values directly from
the IR (accessed via the VPlan). This should be fixed in d995d6376. A
reduced version of the reproducer has been added in 93664503be6b.
The file was modifiedllvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
The file was modifiedllvm/test/Transforms/LoopVectorize/induction.ll
The file was modifiedllvm/test/Transforms/LoopVectorize/vplan-sink-scalars-and-merge.ll
The file was modifiedllvm/test/Transforms/LoopVectorize/first-order-recurrence-sink-replicate-region.ll
The file was modifiedllvm/lib/Transforms/Vectorize/VPlan.h
The file was modifiedllvm/lib/Transforms/Vectorize/LoopVectorize.cpp
The file was modifiedllvm/test/Transforms/LoopVectorize/scalable-first-order-recurrence.ll
The file was modifiedllvm/test/Transforms/LoopVectorize/first-order-recurrence-complex.ll
The file was modifiedllvm/test/Transforms/LoopVectorize/first-order-recurrence.ll
The file was modifiedllvm/lib/Transforms/Vectorize/VPlanValue.h
The file was modifiedllvm/lib/Transforms/Vectorize/VPlan.cpp
The file was modifiedllvm/test/Transforms/LoopVectorize/interleaved-accesses.ll
Commit 8cd8120a7b5d4c6f7674679b53477b51fd054a27 by ulrich.weigand
[SystemZ] Add support for new cpu architecture - arch14

This patch adds support for the next-generation arch14
CPU architecture to the SystemZ backend.

This includes:
- Basic support for the new processor and its features.
- Detection of arch14 as host processor.
- Assembler/disassembler support for new instructions.
- New LLVM intrinsics for certain new instructions.
- Support for low-level builtins mapped to new LLVM intrinsics.
- New high-level intrinsics in vecintrin.h.
- Indicate support by defining  __VEC__ == 10304.

Note: No currently available Z system supports the arch14
architecture.  Once new systems become available, the
official system name will be added as supported -march name.
The file was modifiedclang/test/Driver/systemz-march.c
The file was modifiedclang/test/Misc/target-invalid-cpu-note.c
The file was addedllvm/test/CodeGen/SystemZ/vec-intrinsics-04.ll
The file was addedclang/test/CodeGen/SystemZ/builtins-systemz-zvector4-error.c
The file was modifiedclang/lib/Basic/Targets/SystemZ.h
The file was addedclang/test/CodeGen/SystemZ/builtins-systemz-vector4-error.c
The file was modifiedllvm/include/llvm/IR/IntrinsicsSystemZ.td
The file was modifiedclang/lib/Basic/Targets/SystemZ.cpp
The file was modifiedllvm/lib/Target/SystemZ/SystemZInstrInfo.td
The file was modifiedclang/include/clang/Basic/BuiltinsSystemZ.def
The file was addedllvm/test/MC/SystemZ/insn-bad-arch14.s
The file was modifiedllvm/lib/Target/SystemZ/SystemZInstrVector.td
The file was modifiedclang/test/Preprocessor/predefined-arch-macros.c
The file was modifiedllvm/unittests/Support/Host.cpp
The file was modifiedllvm/lib/Support/Host.cpp
The file was addedllvm/test/MC/SystemZ/insn-good-arch14.s
The file was modifiedllvm/lib/Target/SystemZ/SystemZSubtarget.h
The file was modifiedclang/test/CodeGen/target-data.c
The file was modifiedllvm/lib/Target/SystemZ/SystemZInstrFormats.td
The file was modifiedllvm/lib/Target/SystemZ/SystemZProcessors.td
The file was addedclang/test/CodeGen/SystemZ/builtins-systemz-zvector4.c
The file was modifiedllvm/test/MC/SystemZ/insn-bad-z15.s
The file was modifiedllvm/lib/Target/SystemZ/SystemZInstrSystem.td
The file was modifiedclang/test/CodeGen/SystemZ/systemz-abi-vector.c
The file was modifiedllvm/lib/Target/SystemZ/SystemZFeatures.td
The file was addedclang/test/CodeGen/SystemZ/builtins-systemz-vector4.c
The file was addedllvm/test/MC/Disassembler/SystemZ/insns-arch14.txt
The file was modifiedllvm/lib/Target/SystemZ/SystemZSubtarget.cpp
The file was modifiedclang/lib/Sema/SemaChecking.cpp
The file was modifiedclang/lib/Headers/vecintrin.h
The file was modifiedclang/test/CodeGen/SystemZ/systemz-abi.c
Commit 3274cdc83ecdf2af569ad4f564d55d0e43b1072e by tianshilei1992
[Clang][OpenMP] Remove the mandatory flush for capture for OpenMP 5.1

In OpenMP 5.1:
> If the `write` or `update` clause is specifieded, the atomic operation is not an atomic conditional update for which the comparison fails, and the effective memory ordering is `release`, `acq_rel`, or `seq_cst`, the strong flush on entry to the atomic operation is also a release flush. If the `read` or `update` clause is specified and the effective memory ordering is `acquire`, `acq_rel`, or `seq_cst` then the strong flush on exit from the atomic operation is also an acquire flush.

In OpenMP 5.0:
> If the `write`, `update`, or **`capture`** clause is specified and the `release`, `acq_rel`, or `seq_cst` clause is specified then the strong flush on entry to the atomic operation is also a release flush. If the `read` or `capture` clause is specified and the `acquire`, `acq_rel`, or `seq_cst` clause is specified then the strong flush on exit from the atomic operation is also an acquire flush.

From my understanding, in OpenMP 5.1, `capture` is removed from the requirement for flush, therefore we don't have to enforce it.

Reviewed By: ABataev

Differential Revision: https://reviews.llvm.org/D100768
The file was modifiedclang/test/OpenMP/atomic_capture_codegen.cpp
The file was modifiedclang/lib/CodeGen/CGStmtOpenMP.cpp
Commit 81eafb8a37c9f0eecd3b73642d94eee3bae490bf by bradley.smith
[AArch64][SVE] Break false dependencies for inactive lanes of unary operations

Differential Revision: https://reviews.llvm.org/D105889
The file was modifiedllvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
The file was modifiedllvm/test/CodeGen/AArch64/sve-forward-st-to-ld.ll
The file was modifiedllvm/test/CodeGen/AArch64/sve-gather-scatter-dag-combine.ll
The file was addedllvm/test/CodeGen/AArch64/sve-unary-movprfx.ll
The file was addedllvm/test/CodeGen/AArch64/sve2-unary-movprfx.ll
The file was modifiedllvm/lib/Target/AArch64/AArch64InstrInfo.h
The file was modifiedllvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
The file was modifiedllvm/lib/Target/AArch64/SVEInstrFormats.td
The file was modifiedllvm/test/CodeGen/AArch64/sve-masked-gather-legalize.ll
The file was modifiedllvm/lib/Target/AArch64/AArch64InstrFormats.td
Commit 981e9dce548277eaf3f6725bf5ffe84e03f658b1 by sander.desmalen
[LV] Don't assume isScalarAfterVectorization if one of the uses needs widening.

This fixes an issue that was found in D105199, where a GEP instruction
is used both as the address of a store, as well as the value of a store.
For the former, the value is scalar after vectorization, but the latter
(as value) requires widening.

Other code in that function seems to prevent similar cases from happening,
but it seems this case was missed.

Reviewed By: david-arm

Differential Revision: https://reviews.llvm.org/D106164
The file was modifiedllvm/lib/Transforms/Vectorize/LoopVectorize.cpp
The file was addedllvm/test/Transforms/LoopVectorize/AArch64/sve-widen-gep.ll
The file was modifiedllvm/test/Transforms/LoopVectorize/AArch64/predication_costs.ll
The file was modifiedllvm/test/Transforms/LoopVectorize/pointer-induction.ll
Commit 0d3807b365e5aeee34a3c3887813996907eb7ddb by nikita.ppv
[MergeICmps] Separate out BCECmp and use Optional (NFC)

Separate out the BCECmp part from BCECmpBlock, which just stores
the comparison atoms without the branch instruction. At the same
time switch the code to return Optional<> rather than objects in
invalid state and partially constructed objects.
The file was modifiedllvm/lib/Transforms/Scalar/MergeICmps.cpp
Commit d8260269c32c1c1140c8061ba469e28a75ccc159 by spatel
[SimplifyLibCalls] reduce code duplication; NFC
The file was modifiedllvm/lib/Transforms/Utils/SimplifyLibCalls.cpp
Commit 87d604ffe494fcf66e469e2758c289f18b0e7ce9 by spatel
[SimplifyLibCalls] avoid crash on pointer math

We could try harder to screen out libcalls by
function signature (and that would be a much larger
change than for sprintf alone), but that might make
the transition to type-less pointers more difficult.

https://llvm.org/PR51200
The file was modifiedllvm/test/Transforms/InstCombine/stpcpy-1.ll
The file was modifiedllvm/lib/Transforms/Utils/SimplifyLibCalls.cpp
Commit 3ca6dea05dec44680f29a40de7481aede09cae8a by Louis Dionne
[libc++][NFC] Change a few instances of > > to >> in C++20 code
The file was modifiedlibcxx/include/__ranges/concepts.h
The file was modifiedlibcxx/include/__iterator/concepts.h
Commit 3b77e2737c8545aa628e1d2cff5799db033f7081 by paul.walker
[SVE] Use reg+reg addressing mode for immediate offsets.

For reg+imm SVE addressing mode imm is implictly scaled by VL,
making them impractical for truely immediate offsets.  However, if
the offset can be unscaled based on the storage element type we
can use the reg+reg SVE addressing mode and thus either reduce the
number of generate add instructions or replace them with a mov
instruction that can be hoisted from the hot code path.

Differential Revision: https://reviews.llvm.org/D106744
The file was modifiedllvm/test/CodeGen/AArch64/sve-fixed-length-masked-scatter.ll
The file was modifiedllvm/test/CodeGen/AArch64/sve-fixed-length-fp-arith.ll
The file was modifiedllvm/test/CodeGen/AArch64/sve-fixed-length-fp-extend-trunc.ll
The file was modifiedllvm/test/CodeGen/AArch64/sve-fixed-length-int-to-fp.ll
The file was modifiedllvm/test/CodeGen/AArch64/sve-fixed-length-trunc-stores.ll
The file was modifiedllvm/test/CodeGen/AArch64/sve-fixed-length-bit-counting.ll
The file was modifiedllvm/test/CodeGen/AArch64/sve-fixed-length-fp-reduce.ll
The file was modifiedllvm/test/CodeGen/AArch64/sve-fixed-length-int-compares.ll
The file was modifiedllvm/test/CodeGen/AArch64/sve-fixed-length-log-reduce.ll
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
The file was modifiedllvm/test/CodeGen/AArch64/sve-fixed-length-vector-shuffle.ll
The file was modifiedllvm/test/CodeGen/AArch64/sve-fixed-length-int-shifts.ll
The file was modifiedllvm/test/CodeGen/AArch64/sve-fixed-length-splat-vector.ll
The file was modifiedllvm/test/CodeGen/AArch64/sve-fixed-length-rev.ll
The file was modifiedllvm/test/CodeGen/AArch64/sve-fixed-length-fp-to-int.ll
The file was modifiedllvm/test/CodeGen/AArch64/named-vector-shuffles-sve.ll
The file was modifiedllvm/test/CodeGen/AArch64/sve-fixed-length-int-extends.ll
The file was modifiedllvm/test/CodeGen/AArch64/sve-fixed-length-int-minmax.ll
The file was modifiedllvm/test/CodeGen/AArch64/sve-fixed-length-float-compares.ll
The file was modifiedllvm/test/CodeGen/AArch64/sve-fixed-length-loads.ll
The file was modifiedllvm/test/CodeGen/AArch64/sve-fixed-length-int-reduce.ll
The file was modifiedllvm/test/CodeGen/AArch64/sve-fixed-length-masked-gather.ll
The file was modifiedllvm/test/CodeGen/AArch64/sve-vscale-attr.ll
The file was modifiedllvm/test/CodeGen/AArch64/sve-fixed-length-fp-minmax.ll
The file was modifiedllvm/test/CodeGen/AArch64/sve-fixed-length-fp-rounding.ll
The file was modifiedllvm/test/CodeGen/AArch64/sve-fixed-length-stores.ll
The file was modifiedllvm/test/CodeGen/AArch64/sve-intrinsics-ld1ro-addressing-mode-reg-imm.ll
Commit 0c9978473e53833211669920370e2909303f0b49 by kazu
[AsmParser] Remove MDRef (NFC)

The last use was removed on Jan 12, 2015 in commit
ab617d597708fcf3c4b829bf595e9d990ca66c07.
The file was modifiedllvm/include/llvm/AsmParser/LLParser.h
Commit c691651c53485a07db5b529e5a465eee397b7987 by nikita.ppv
[MergeICmps] Try to fix MSVC build failure

Apparently this fails to line up the types -- try to sidestep the
issue entirely by writing the code in a more reasonable way: Walk
over the operands and perform a set lookup, rather than walking
over the set and performing an operand scan.
The file was modifiedllvm/lib/Transforms/Scalar/MergeICmps.cpp
Commit c0da287c30c9f511ccb07fdd42c997be2caea9ec by i
[yaml2obj][MachO] Rename PayloadString to Content

The new name is conciser and matches yaml2obj ELF & DWARF.

Reviewed By: #lld-macho, thakis

Differential Revision: https://reviews.llvm.org/D106759
The file was modifiedllvm/test/ObjectYAML/MachO/dylib_dylinker_command.yaml
The file was modifiedllvm/lib/ObjectYAML/MachOEmitter.cpp
The file was modifiedllvm/test/tools/llvm-objcopy/MachO/install-name-tool-delete-rpath.test
The file was modifiedllvm/test/ObjectYAML/MachO/out_of_order_linkedit.yaml
The file was modifiedlld/test/MachO/dylib-stub.yaml
The file was modifiedllvm/lib/ObjectYAML/MachOYAML.cpp
The file was modifiedllvm/test/tools/llvm-lipo/Inputs/CPU10-slice.yaml
The file was modifiedllvm/test/ObjectYAML/MachO/null_string_entries.yaml
The file was modifiedllvm/test/tools/llvm-objcopy/MachO/Inputs/strip-all.yaml
The file was modifiedllvm/test/tools/llvm-objcopy/MachO/basic-executable-copy.test
The file was modifiedllvm/test/ObjectYAML/MachO/symtab.yaml
The file was modifiedllvm/test/tools/llvm-dwarfdump/uuid32.yaml
The file was modifiedllvm/test/ObjectYAML/MachO/export_trie.yaml
The file was modifiedllvm/test/tools/llvm-objcopy/MachO/segment-size-alignment.test
The file was modifiedllvm/include/llvm/ObjectYAML/MachOYAML.h
The file was modifiedllvm/test/tools/llvm-objcopy/MachO/install-name-tool-id.test
The file was modifiedllvm/test/tools/llvm-tapi-diff/Inputs/macho.yaml
The file was modifiedllvm/test/tools/llvm-objcopy/MachO/install-name-tool-change.test
The file was modifiedllvm/test/tools/llvm-objcopy/MachO/lc-load-weak-dylib.test
The file was modifiedllvm/test/tools/llvm-objcopy/MachO/segments-vmsize.test
The file was modifiedllvm/test/tools/llvm-readobj/MachO/needed-libs.test
The file was modifiedllvm/test/tools/llvm-lipo/Inputs/armv7-slice-big.yaml
The file was modifiedllvm/test/tools/llvm-objcopy/MachO/remove-lc-index-update.test
The file was modifiedllvm/test/tools/llvm-objcopy/MachO/install-name-tool-rpath.test
The file was modifiedlld/test/MachO/zippered.yaml
The file was modifiedllvm/test/tools/llvm-dwarfdump/uuid.yaml
The file was modifiedllvm/tools/obj2yaml/macho2yaml.cpp
Commit 792c206e2b63c16075d759d3abc3eb5399ed74fe by i
[llvm-objcopy] Drop GRP_COMDAT if the group signature is localized

See [GRP_COMDAT group with STB_LOCAL signature](https://groups.google.com/g/generic-abi/c/2X6mR-s2zoc)
objcopy PR: https://sourceware.org/bugzilla/show_bug.cgi?id=27931

GRP_COMDAT deduplication is purely based on the signature symbol name in
ld.lld/GNU ld/gold. The local/global status is not part of the equation.

If the signature symbol is localized by --localize-hidden or
--keep-global-symbol, the intention is likely to make the group fully
localized. Drop GRP_COMDAT to suppress deduplication.

Reviewed By: jhenderson

Differential Revision: https://reviews.llvm.org/D106782
The file was modifiedllvm/test/tools/llvm-objcopy/ELF/strip-dwo-groups.test
The file was modifiedllvm/tools/llvm-objcopy/ELF/Object.cpp
The file was modifiedllvm/test/tools/llvm-objcopy/ELF/remove-section-in-group.test
The file was modifiedllvm/test/tools/llvm-objcopy/ELF/group.test
The file was modifiedllvm/test/tools/llvm-objcopy/ELF/group-reorder.test
Commit f921bf6049df6cb8b8a030fedd15351d003f91a9 by nikita.ppv
[MergeICmps] Collect block instructions once (NFC)

Collect the relevant instructions for a given BCECmpBlock once
on construction, rather than repeating this logic in multiple
places.
The file was modifiedllvm/lib/Transforms/Scalar/MergeICmps.cpp
Commit e8a64e5491260714c79dab65d1aa73245931d314 by cjdb
[clang][pp] adds '#pragma include_instead'

`#pragma clang include_instead(<header>)` is a pragma that can be used
by system headers (and only system headers) to indicate to a tool that
the file containing said pragma is an implementation-detail header and
should not be directly included by user code.

The library alternative is very messy code that can be seen in the first
diff of D106124, and we'd rather avoid that with something more
universal.

This patch takes the first step by warning a user when they include a
detail header in their code, and suggests alternative headers that the
user should include instead. Future work will involve adding a fixit to
automate the process, as well as cleaning up modules diagnostics to not
suggest said detail headers. Other tools, such as clangd can also take
advantage of this pragma to add the correct user headers.

Differential Revision: https://reviews.llvm.org/D106394
The file was modifiedclang/include/clang/Lex/PreprocessorLexer.h
The file was addedclang/test/Preprocessor/Inputs/include_instead/private-x.h
The file was addedclang/test/Preprocessor/Inputs/include_instead/public-before.h
The file was addedclang/test/Preprocessor/Inputs/include_instead/private3.h
The file was addedclang/test/Preprocessor/Inputs/include_instead/bad-syntax.h
The file was addedclang/test/Preprocessor/Inputs/include_instead/public-empty.h
The file was modifiedclang/include/clang/Lex/HeaderSearch.h
The file was addedclang/test/Preprocessor/include_instead_file_not_found.cpp
The file was modifiedclang/lib/Lex/Pragma.cpp
The file was addedclang/test/Preprocessor/include_instead.cpp
The file was addedclang/test/Preprocessor/Inputs/include_instead/public-after.h
The file was addedclang/test/Preprocessor/Inputs/include_instead/non-system-header.h
The file was modifiedclang/lib/Lex/PPDirectives.cpp
The file was modifiedclang/lib/Lex/PPLexerChange.cpp
The file was modifiedclang/lib/Lex/Lexer.cpp
The file was modifiedclang/include/clang/Basic/DiagnosticLexKinds.td
The file was modifiedclang/include/clang/Lex/Preprocessor.h
The file was addedclang/test/Preprocessor/Inputs/include_instead/file-not-found.h
The file was addedclang/test/Preprocessor/Inputs/include_instead/private1.h
The file was addedclang/test/Preprocessor/Inputs/include_instead/private2.h
Commit b9051ba84836f6c2a3b008638de14b588e58fa9f by sander.desmalen
[LV] Remove assert that VF cannot be scalable in setCostBasedWideningDecision.

Scalarization for scalable vectors is not (yet) supported, so the
LV discards a VF when scalarization is chosen as the widening
decision. It should therefore not assert that the VF is not scalable
when it computes the decision to scalarize.

The code can get here when both the interleave-cost, gather/scatter cost
and scalarization-cost are all illegal. This may e.g. happen for SVE
when the VF=1, to avoid generating `<vscale x 1 x eltty>` types that
the code-generator cannot yet handle.

Reviewed By: david-arm

Differential Revision: https://reviews.llvm.org/D106656
The file was modifiedllvm/lib/Transforms/Vectorize/LoopVectorize.cpp
The file was modifiedllvm/test/Transforms/LoopVectorize/AArch64/sve-gather-scatter.ll
Commit 77c5e6ba900a167909873d2364d55b6a19df8994 by llvm-dev
[Analysis] Fix getOrderedReductionCost to call target's getArithmeticInstrCost implementation

The getOrderedReductionCost implementation introduced in D105432 calls the CRTP base version getArithmeticInstrCost instead of the redirecting to the target version.

Differential Revision: https://reviews.llvm.org/D106795
The file was modifiedllvm/test/Analysis/CostModel/X86/reduce-fmul.ll
The file was modifiedllvm/include/llvm/CodeGen/BasicTTIImpl.h
The file was modifiedllvm/test/Analysis/CostModel/X86/reduce-fadd.ll
Commit fbaf7f0bc768bb236db49a2fea79169f91c10720 by Louis Dionne
[libc++] Add range_size_t

Differential Revision: https://reviews.llvm.org/D106708
The file was addedlibcxx/test/std/ranges/range.req/range.range/range_size_t.compile.pass.cpp
The file was modifiedlibcxx/docs/Status/RangesPaper.csv
The file was modifiedlibcxx/include/__ranges/concepts.h
The file was modifiedlibcxx/include/ranges
Commit 240dde948252ab9ef0428c46ca578c06127d3799 by qiucofan
[PowerPC] Change altivec indexed load/store builtins argument type

This patch changes the index argument of lvxl?/lve[bhw]x and
stvxl?/stve[bhw]x builtins from int to long. Because on 64-bit
subtargets, an extra extsw will always been generated, which is
incorrect.

Reviewed By: nemanjai

Differential Revision: https://reviews.llvm.org/D106530
The file was modifiedclang/lib/Headers/altivec.h
The file was modifiedclang/test/CodeGen/ppc-xmmintrin.c
The file was modifiedclang/test/CodeGen/ppc-emmintrin.c
The file was modifiedclang/include/clang/Basic/BuiltinsPPC.def
Commit 31e75512174e1bdaa242ee5c7f30fe56e68c3748 by stephen.tozer
[DebugInfo] Correctly update debug users of SSA values in tail duplication

During tail duplication, SSA values may be updated and have their uses
replaced with a virtual register, and any debug instructions that use
that value are deleted. This patch fixes the implementation of the debug
instruction deletion to work correctly for debug instructions that use
the SSA value multiple times, by batching deletions so that we don't
attempt to delete the same instruction twice.

Differential Revision: https://reviews.llvm.org/D106557
The file was addedllvm/test/CodeGen/X86/tail-dup-debugvalue.mir
The file was modifiedllvm/lib/CodeGen/TailDuplicator.cpp
Commit 6d753b0751b1f4b6fb6851b69627244722c57a64 by flo
[LAA] Remove RuntimeCheckingPtrGroup::RtCheck member (NFC).

This patch removes RtCheck from RuntimeCheckingPtrGroup to make it
possible to construct RuntimeCheckingPtrGroup objects without a
RuntimePointerChecking object. This should make it easier to
re-use the code to generate runtime checks, e.g. in D102834.

RtCheck was only used to access the pointer info for a given index.
Instead, the start and end expressions can be passed directly.

For code-gen, we also need to know the address space to use. This can
also be explicitly passed at construction.

Reviewed By: efriedma

Differential Revision: https://reviews.llvm.org/D105481
The file was modifiedllvm/lib/Analysis/LoopAccessAnalysis.cpp
The file was modifiedllvm/lib/Transforms/Utils/LoopUtils.cpp
The file was modifiedllvm/include/llvm/Analysis/LoopAccessAnalysis.h