Changes

Summary

  1. [tosa][mlir] Refactor tosa.reshape lowering to linalg for dynamic cases. (details)
  2. [mlir][sparse] first version of "truly" dynamic sparse tensors as outputs of kernels (details)
  3. [RISCV][test] Add more tests of immediate materialisation (details)
  4. [RISCV] Optimize immediate materialisation with SH*ADD (details)
  5. [InstSimplify] Fold A|B | (A^B) --> A|B (details)
  6. [Bazel] Enable layering_check for MLIR build (details)
  7. [LLDB][NativePDB] Fix local-variables.cpp failure on windows bots (details)
  8. add tsan shared lib (details)
  9. [DAGCombiner] Prevent unfoldMaskedMerge from creating an AND with two inverted inputs. (details)
  10. DebugInfo: Make DWARFExpression::iterator::operator++ return itself (details)
  11. DebugInfo: const-qualify accessors of DWARFExpression::Operation (details)
  12. DebugInfo: Make DWARFExpression::iterator::skipBytes() const, NFC (details)
  13. [clang] NFC: rename internal `IsPossiblyOpaquelyQualifiedType` overload (details)
  14. [mlir][linalg][bufferize][NFC] Clean up tensor op bufferization (details)
  15. AMDGPU: Regenerate test checks (details)
  16. AMDGPU: Mark prolog/epilog SCC defs as dead (details)
  17. [X86] Fix crash with inline asm using wrong register name (details)
  18. [RISCV] Add test cases to prepare for overring TargetLowering::hasAndNot. NFC (details)
  19. [RISCV] Override TargetLowering::hasAndNot for Zbb. (details)
  20. Add the stop count to "statistics dump" in each target's dictionary. (details)
  21. [llvm-profgen] Add switch to allow use of first loadable segment for calculating offset (details)
Commit 381677dfbfea0aeba6ee70eeb4d1441356fb916f by rob.suderman
[tosa][mlir] Refactor tosa.reshape lowering to linalg for dynamic cases.

Split tosa.reshape into three individual lowerings: collapse, expand and a
combination of both. Add simple dynamic shape support.

Reviewed By: rsuderman

Differential Revision: https://reviews.llvm.org/D113936
The file was modifiedmlir/lib/Conversion/TosaToLinalg/TosaToLinalg.cpp
The file was modifiedmlir/test/Conversion/TosaToLinalg/tosa-to-linalg.mlir
Commit f66e5769d41b436176f87a08279feec5163c32f3 by ajcbik
[mlir][sparse] first version of "truly" dynamic sparse tensors as outputs of kernels

This revision contains all "sparsification" ops and rewriting necessary to support sparse output tensors when the kernel has no reduction (viz. insertions occur in lexicographic order and are "injective"). This will be later generalized to allow reductions too. Also, this first revision only supports sparse 1-d tensors (viz. vectors) as output in the runtime support library. This will be generalized to n-d tensors shortly. But this way, the revision is kept to a manageable size.

Reviewed By: bixia

Differential Revision: https://reviews.llvm.org/D113705
The file was modifiedmlir/lib/Dialect/SparseTensor/IR/SparseTensorDialect.cpp
The file was modifiedmlir/lib/Dialect/SparseTensor/Transforms/Sparsification.cpp
The file was modifiedmlir/test/Dialect/SparseTensor/sparse_out.mlir
The file was modifiedmlir/test/Dialect/SparseTensor/dense.mlir
The file was modifiedmlir/test/Dialect/SparseTensor/roundtrip.mlir
The file was modifiedmlir/test/Dialect/SparseTensor/invalid.mlir
The file was modifiedmlir/test/Dialect/SparseTensor/fold.mlir
The file was modifiedmlir/include/mlir/Dialect/SparseTensor/IR/SparseTensorOps.td
The file was modifiedmlir/lib/ExecutionEngine/SparseTensorUtils.cpp
The file was modifiedmlir/test/Dialect/SparseTensor/conversion.mlir
The file was modifiedmlir/lib/Dialect/SparseTensor/Transforms/SparseTensorConversion.cpp
The file was addedmlir/test/Integration/Dialect/SparseTensor/CPU/sparse_vector_ops.mlir
Commit 39256ed58ce96daac0e4153af7b73122505c1626 by powerman1st
[RISCV][test] Add more tests of immediate materialisation

Reviewed By: craig.topper, luismarques

Differential Revision: https://reviews.llvm.org/D113567
The file was modifiedllvm/test/CodeGen/RISCV/imm.ll
The file was modifiedllvm/test/MC/RISCV/rv64zba-aliases-valid.s
Commit 4c3d916c4bd2a392101c74dd270bd1e6a4fec15b by powerman1st
[RISCV] Optimize immediate materialisation with SH*ADD

Use LUI+SH*ADD+ADDI to compose specific immediates.

Reviewed By: craig.topper, luismarques

Differential Revision: https://reviews.llvm.org/D113568
The file was modifiedllvm/test/MC/RISCV/rv64zba-aliases-valid.s
The file was modifiedllvm/test/CodeGen/RISCV/imm.ll
The file was modifiedllvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp
Commit 62c51a72f9e7540fb58bba7e116a4b411ab18bef by muhammad.asif.manzoor1
[InstSimplify] Fold A|B | (A^B) --> A|B

This patch adds the following fold opportunity:
A|B | (A^B) --> A|B

that is reported here : https://bugs.llvm.org/show_bug.cgi?id=52479

https://alive2.llvm.org/ce/z/33-My-

Test cases with base results are added in D113860

Reviewed By: rampitec

Differential Revision: https://reviews.llvm.org/D113861
The file was modifiedllvm/test/Transforms/InstSimplify/or.ll
The file was modifiedllvm/lib/Analysis/InstructionSimplify.cpp
Commit d4238fbf6a691188e1ccda21f88a90bd41d919b6 by gcmn
[Bazel] Enable layering_check for MLIR build

This feature checks that headers included by a file are provided by a
header exported by one of the direct dependencies of the build rule in
which it is contained. It ensures that appropriate layering (a goal of
the LLVM project) is preserved. So far, I'm only adding this to MLIR
because we've had it turned on internally since the beginning, so MLIR
is already layering clean. It would be nice to also enable it for LLVM,
but that requires some additional cleanup.

Reviewed By: jpienaar

Differential Revision: https://reviews.llvm.org/D113952
The file was modifiedutils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Commit b6d35352304601925bc1c055106949d2e27b3975 by zequanwu
[LLDB][NativePDB] Fix local-variables.cpp failure on windows bots
The file was modifiedlldb/test/Shell/SymbolFile/NativePDB/local-variables.cpp
Commit d2b43605c96ff5669653455fdfc06ec26876f436 by zijunzhao
add tsan shared lib

Change-Id: Ic83ff1ec86d6a7d61b07fa3df7e0cb2790b5ebc7
The file was modifiedcompiler-rt/cmake/config-ix.cmake
The file was modifiedcompiler-rt/test/tsan/CMakeLists.txt
The file was modifiedcompiler-rt/lib/tsan/CMakeLists.txt
Commit 233def40f7adfc92db4492e7d612e6ff1d85931f by craig.topper
[DAGCombiner] Prevent unfoldMaskedMerge from creating an AND with two inverted inputs.

It's possible that the mask is already a NOT. At least if InstCombine
hasn't canonicalized the input. In that case we will form an ANDN with
X instead of with Y. So we don't need to worry about Y being a constant.

We might need to check that X isn't a constant instead, but we don't
have a test case for that yet.

This fixes a size regression found when trying to enable this combine
for RISCV in D113937.

Differential Revision: https://reviews.llvm.org/D113948
The file was modifiedllvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
The file was modifiedllvm/test/CodeGen/X86/unfold-masked-merge-scalar-variablemask.ll
Commit b23ba295bd129315eac09a52cf58346081e6fdc8 by Duncan P. N. Exon Smith
DebugInfo: Make DWARFExpression::iterator::operator++ return itself

Looks like an accident that `operator++` was returning `Operator&`
instead of `iterator&`. Update to match standard iterator behaviour.
The file was modifiedllvm/include/llvm/DebugInfo/DWARF/DWARFExpression.h
Commit 79df41011ba6b899c50f870bad4b28dbbb0d28cb by Duncan P. N. Exon Smith
DebugInfo: const-qualify accessors of DWARFExpression::Operation

Add `const` to DWARFExpression::Operation's accessors and make
Operation::extract() private, since it's only used by the friend class
DWARFExpression::iterator.
The file was modifiedllvm/include/llvm/DebugInfo/DWARF/DWARFExpression.h
The file was modifiedllvm/lib/DebugInfo/DWARF/DWARFExpression.cpp
Commit d7a81359d781e1aad83f422d18e00c7e97ebb7c6 by Duncan P. N. Exon Smith
DebugInfo: Make DWARFExpression::iterator::skipBytes() const, NFC

Given that DWARFExpression::iterator::skipBytes() doesn't change any
state (it returns a new `iterator`), it might as well be
`const`-qualified.
The file was modifiedllvm/include/llvm/DebugInfo/DWARF/DWARFExpression.h
Commit 21ed00bc1bfd2b0b81d288f7f096a31079c24c4a by mizvekov
[clang] NFC: rename internal `IsPossiblyOpaquelyQualifiedType` overload

Rename `IsPossiblyOpaquelyQualifiedType` overload taking a Type*
as `IsPossiblyOpaquelyQualifiedTypeInternal` instead.

Signed-off-by: Matheus Izvekov <mizvekov@gmail.com>

Differential Revision: https://reviews.llvm.org/D113954
The file was modifiedclang/lib/Sema/SemaTemplateDeduction.cpp
Commit 17194ca96ab5a46ee90c656f7654d3f15f5d46c6 by springerm
[mlir][linalg][bufferize][NFC] Clean up tensor op bufferization

Differential Revision: https://reviews.llvm.org/D113730
The file was modifiedmlir/lib/Dialect/Linalg/ComprehensiveBufferize/ComprehensiveBufferize.cpp
Commit e6bfbd7e0dc41d394d4eee69f727660090eaf828 by Matthew.Arsenault
AMDGPU: Regenerate test checks
The file was modifiedllvm/test/CodeGen/AMDGPU/spill-reg-tuple-super-reg-use.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/spill-special-sgpr.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/pei-reg-scavenger-position.mir
Commit 659887b4056236d376c0ac1218ca3f7a0dd75604 by Matthew.Arsenault
AMDGPU: Mark prolog/epilog SCC defs as dead

A future change will add SCC liveness checks. Since we are still
relying on forward register scavenging, add dead flags to avoid
spuriously detecting SCC as live.
The file was modifiedllvm/test/CodeGen/AMDGPU/spill-special-sgpr.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/pei-scavenge-sgpr-gfx9.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/spill-reg-tuple-super-reg-use.mir
The file was modifiedllvm/lib/Target/AMDGPU/SIFrameLowering.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/lds-atomic-fmin-fmax.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/gfx-callable-return-types.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/non-entry-alloca.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/sgpr-spill.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/pei-scavenge-vgpr-spill.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/pei-reg-scavenger-position.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/pei-scavenge-sgpr.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/non-entry-alloca.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/dynamic-alloca-uniform.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/pei-scavenge-sgpr-carry-out.mir
Commit b484fa8289299a4a55708d8e4104aacfea8d7fd5 by pengfei.wang
[X86] Fix crash with inline asm using wrong register name

Fixes PR#48678. `X86TargetLowering::getRegForInlineAsmConstraint()` can adjust the register class to match the type, e.g. change `VR128X` to `VR256X` if the type needs 256 bits. However, the function currently returns the unadjusted register and the adjusted register class, e.g. `xmm15` and `VR256X`, which then causes an assertion failure later because the register class does not contain that register. This patch fixes this behavior.

Reviewed By: pengfei

Differential Revision: https://reviews.llvm.org/D113834
The file was modifiedllvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
The file was addedllvm/test/CodeGen/X86/asm-reject-reg-type-mismatch-avx.ll
Commit d90eeab0ed1d73d1db62edf9b49527f3b3e4140c by craig.topper
[RISCV] Add test cases to prepare for overring TargetLowering::hasAndNot. NFC

These test files are copied directly from AArch64. Some of the cases
may benefit from ANDN with the Zbb extension. Somes cases already
improve use ANDN.

selectcc-to-shiftand.ll also contains tests that test select->and
conversion even when a ANDN isn't needed. I think this improves our
coverage of these optimizations.

Differential Revision: https://reviews.llvm.org/D113935
The file was addedllvm/test/CodeGen/RISCV/selectcc-to-shiftand.ll
The file was addedllvm/test/CodeGen/RISCV/unfold-masked-merge-scalar-variablemask.ll
Commit 391b0ba603ab4e2b5fcdfe29a2907a67831293df by craig.topper
[RISCV] Override TargetLowering::hasAndNot for Zbb.

Differential Revision: https://reviews.llvm.org/D113937
The file was modifiedllvm/test/CodeGen/RISCV/unfold-masked-merge-scalar-variablemask.ll
The file was modifiedllvm/lib/Target/RISCV/RISCVISelLowering.h
The file was modifiedllvm/lib/Target/RISCV/RISCVISelLowering.cpp
The file was modifiedllvm/test/CodeGen/RISCV/selectcc-to-shiftand.ll
Commit dbd36e1e9f16059f1be1d15f8549a6e538906679 by gclayton
Add the stop count to "statistics dump" in each target's dictionary.

It is great to know how many times the target has stopped over its lifetime as each time the target stops, and possibly resumes without the user seeing it for things like shared library loading and signals that are not notified and auto continued, to help explain why a debug session might be slow. This is now included as "stopCount" inside each target JSON.

Differential Revision: https://reviews.llvm.org/D113810
The file was modifiedlldb/test/API/commands/statistics/basic/TestStats.py
The file was modifiedlldb/source/Target/Statistics.cpp
Commit f7976edc1ec48ae9f96bcc7524ae02373d126869 by aktoon
[llvm-profgen] Add switch to allow use of first loadable segment for calculating offset

Adding `-use-loadable-segment-as-base` to allow use of first loadable segment for calculating offset. By default first executable segment is used for calculating offset. The switch helps compatibility with unsymbolized profile generated from older tools.

Differential Revision: https://reviews.llvm.org/D113727
The file was modifiedllvm/tools/llvm-profgen/PerfReader.cpp
The file was modifiedllvm/test/tools/llvm-profgen/inline-cs-pseudoprobe.test
The file was modifiedllvm/tools/llvm-profgen/ProfiledBinary.h
The file was modifiedllvm/tools/llvm-profgen/ProfiledBinary.cpp