Changes

Summary

  1. [libc++] Implement P1272R4 (std::byteswap) (details)
  2. [gn build] Port 1dc62f2653f8 (details)
  3. [libc++][NFC] Sort includes in __ranges/concepts.h (details)
  4. NFC: clang-format lib/Transforms/Instrumentation/InstrProfiling.cpp (details)
  5. [llvm] Use range-based for loops (NFC) (details)
  6. [llvm] Use make_early_inc_range (NFC) (details)
  7. [RISCV] Generate pseudo instruction li (details)
Commit 1dc62f2653f837745251bd905940c11962469b45 by nikolasklauser
[libc++] Implement P1272R4 (std::byteswap)

Implement P1274R4

Reviewed By: Quuxplusone, Mordante, #libc

Spies: jloser, lebedev.ri, mgorny, libcxx-commits, arichardson

Differential Revision: https://reviews.llvm.org/D114074
The file was modifiedlibcxx/include/module.modulemap
The file was addedlibcxx/include/__bit/byteswap.h
The file was modifiedlibcxx/include/CMakeLists.txt
The file was modifiedlibcxx/test/std/language.support/support.limits/support.limits.general/bit.version.pass.cpp
The file was modifiedlibcxx/test/std/language.support/support.limits/support.limits.general/version.version.pass.cpp
The file was modifiedlibcxx/docs/FeatureTestMacroTable.rst
The file was modifiedlibcxx/include/version
The file was addedlibcxx/test/libcxx/diagnostics/detail.headers/bit/byteswap.module.verify.cpp
The file was addedlibcxx/test/std/numerics/bit/byteswap.pass.cpp
The file was modifiedlibcxx/docs/Status/Cxx2bPapers.csv
The file was modifiedlibcxx/utils/generate_feature_test_macro_components.py
The file was modifiedlibcxx/include/bit
Commit 0a413506a29e9d9ab0af1156d5474fe78072d554 by llvmgnsyncbot
[gn build] Port 1dc62f2653f8
The file was modifiedllvm/utils/gn/secondary/libcxx/include/BUILD.gn
Commit a60b63940a656b01b44d1db749bd4130e3739b27 by joeloser93
[libc++][NFC] Sort includes in __ranges/concepts.h

Differential Revision: https://reviews.llvm.org/D114328
The file was modifiedlibcxx/include/__ranges/concepts.h
Commit b72b56016a6b586a22a49f145c924c03e4239b1d by mcgrathr
NFC: clang-format lib/Transforms/Instrumentation/InstrProfiling.cpp

Differential Revision: https://reviews.llvm.org/D114343
The file was modifiedllvm/lib/Transforms/Instrumentation/InstrProfiling.cpp
Commit ea5421bd0db3e6782f60c53a7055eb11abed09c3 by kazu
[llvm] Use range-based for loops (NFC)
The file was modifiedllvm/lib/Target/XCore/XCoreFrameLowering.cpp
The file was modifiedllvm/lib/Target/X86/X86FrameLowering.cpp
The file was modifiedllvm/lib/Target/PowerPC/PPCFrameLowering.cpp
The file was modifiedllvm/lib/Target/SystemZ/SystemZFrameLowering.cpp
Commit 49e3838145dff1ec91c2e67a2cb562775c8d2a08 by kazu
[llvm] Use make_early_inc_range (NFC)
The file was modifiedllvm/lib/Target/Lanai/LanaiFrameLowering.cpp
The file was modifiedllvm/lib/Target/Hexagon/HexagonPeephole.cpp
The file was modifiedllvm/lib/Target/AMDGPU/R600Packetizer.cpp
Commit af0ecfccae82ade32581959d61fe86f573d08def by pc.wang
[RISCV] Generate pseudo instruction li

Add an alias of `addi [x], zero, imm` to generate pseudo
instruction li, which makes assembly mush more readable.
For existed tests, users can update them by running script
`llvm/utils/update_llc_test_checks.py`.

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D112692
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vadd-vp.ll
The file was modifiedllvm/test/CodeGen/RISCV/rv32zbp.ll
The file was modifiedllvm/test/CodeGen/RISCV/half-arith.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-vrgather.ll
The file was modifiedllvm/test/CodeGen/RISCV/i32-icmp.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-load-store.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmulu.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/bswap-sdnode.ll
The file was modifiedllvm/test/CodeGen/RISCV/rv64zba.ll
The file was modifiedllvm/test/CodeGen/RISCV/lsr-legaladdimm.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/memory-args.ll
The file was modifiedllvm/test/CodeGen/RISCV/half-br-fcmp.ll
The file was modifiedllvm/test/CodeGen/RISCV/ssub_sat.ll
The file was modifiedllvm/test/CodeGen/RISCV/analyze-branch.ll
The file was modifiedllvm/test/CodeGen/RISCV/calling-conv-ilp32f-ilp32d-common.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmaccu.ll
The file was modifiedllvm/test/CodeGen/RISCV/split-offsets.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vminu-sdnode.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vsra-sdnode.ll
The file was modifiedllvm/test/CodeGen/RISCV/rv32zbs.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll
The file was modifiedllvm/test/CodeGen/RISCV/sext-zext-trunc.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-logic.ll
The file was modifiedllvm/test/CodeGen/RISCV/atomic-rmw.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vremu-sdnode.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast-large-vector.ll
The file was modifiedllvm/test/CodeGen/RISCV/shift-masked-shamt.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/calling-conv-fastcc.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/setcc-integer-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/cttz-sdnode.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vdivu-sdnode.ll
The file was modifiedllvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll
The file was modifiedllvm/test/CodeGen/RISCV/calling-conv-ilp32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vsra-vp.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vor-sdnode.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll
The file was modifiedllvm/test/CodeGen/RISCV/atomic-load-store.ll
The file was modifiedllvm/test/CodeGen/RISCV/shifts.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmul.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/extractelt-int-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int.ll
The file was modifiedllvm/test/CodeGen/RISCV/calling-conv-lp64.ll
The file was modifiedllvm/test/CodeGen/RISCV/jumptable.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vector-strided-load-store.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract.ll
The file was modifiedllvm/test/CodeGen/RISCV/indirectbr.ll
The file was modifiedllvm/test/CodeGen/RISCV/imm.ll
The file was modifiedllvm/test/CodeGen/RISCV/mul.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/urem-seteq-vec.ll
The file was modifiedllvm/test/CodeGen/RISCV/unfold-masked-merge-scalar-variablemask.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vshl-vp.ll
The file was modifiedllvm/test/CodeGen/RISCV/rv64zbs.ll
The file was modifiedllvm/test/CodeGen/RISCV/double-br-fcmp.ll
The file was modifiedllvm/test/MC/RISCV/rv64zba-aliases-valid.s
The file was modifiedllvm/test/CodeGen/RISCV/rv64m-w-insts-legalization.ll
The file was modifiedllvm/test/CodeGen/RISCV/shrinkwrap.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vsub-sdnode.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmacc.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-subvector.ll
The file was modifiedllvm/test/CodeGen/RISCV/srem-vector-lkk.ll
The file was modifiedllvm/test/CodeGen/RISCV/calling-conv-rv32f-ilp32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect.ll
The file was modifiedllvm/test/CodeGen/RISCV/float-bit-preserving-dagcombines.ll
The file was modifiedllvm/test/CodeGen/RISCV/select-constant-xor.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-shuffles.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-splat.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/combine-sats.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv-fastcc.ll
The file was modifiedllvm/test/CodeGen/RISCV/sink-icmp.ll
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfo.td
The file was modifiedllvm/test/CodeGen/RISCV/double-fcmp.ll
The file was modifiedllvm/test/CodeGen/RISCV/srem-lkk.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/allocate-lmul-2-4-8.ll
The file was modifiedllvm/test/CodeGen/RISCV/uadd_sat.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-i1.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vreductions-int-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-vremu-vp.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmv.x.s-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsra-vp.ll
The file was modifiedllvm/test/CodeGen/RISCV/rv32zba.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmulhu-sdnode.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/rv64-spill-zvlsseg.ll
The file was modifiedllvm/test/CodeGen/RISCV/calling-conv-lp64-lp64f-common.ll
The file was modifiedllvm/test/CodeGen/RISCV/float-convert.ll
The file was modifiedllvm/test/CodeGen/RISCV/rv64zbb.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap.ll
The file was modifiedllvm/test/CodeGen/RISCV/vararg.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsrl-vp.ll
The file was modifiedllvm/test/CodeGen/RISCV/atomic-signext.ll
The file was modifiedllvm/test/CodeGen/RISCV/branch-relaxation.ll
The file was modifiedllvm/test/CodeGen/RISCV/vec3-setcc-crash.ll
The file was modifiedllvm/test/CodeGen/RISCV/remat.ll
The file was modifiedllvm/test/MC/RISCV/rv64zbs-aliases-valid.s
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vsrl-sdnode.ll
The file was modifiedllvm/test/MC/RISCV/rv32i-aliases-valid.s
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-setcc.ll
The file was modifiedllvm/test/CodeGen/RISCV/atomic-cmpxchg.ll
The file was modifiedllvm/test/CodeGen/RISCV/frame.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int-vp.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-splat.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/interleave-crash.ll
The file was modifiedllvm/test/MC/RISCV/compress-rv32i.s
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-exttrunc.ll
The file was modifiedllvm/test/MC/RISCV/numeric-reg-names.s
The file was modifiedllvm/test/CodeGen/RISCV/rvv/setcc-integer-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/pr51206.ll
The file was modifiedllvm/test/CodeGen/RISCV/half-convert.ll
The file was modifiedllvm/test/CodeGen/RISCV/div.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll
The file was modifiedllvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/riscv_function_name.ll.expected
The file was modifiedllvm/test/CodeGen/RISCV/sadd_sat_plus.ll
The file was modifiedllvm/test/CodeGen/RISCV/half-fcmp.ll
The file was modifiedllvm/test/CodeGen/RISCV/xaluo.ll
The file was modifiedllvm/test/CodeGen/RISCV/fp-imm.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/stepvector.ll
The file was modifiedllvm/test/CodeGen/RISCV/select-const.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/combine-splats.ll
The file was modifiedllvm/test/CodeGen/RISCV/double-calling-conv.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-vdivu-vp.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-vreductions-mask.ll
The file was modifiedllvm/test/CodeGen/RISCV/double-convert.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssubu.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-load-int.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-vrgather.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/rv32-spill-zvlsseg.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-buildvec.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vdivu-vp.ll
The file was modifiedllvm/test/CodeGen/RISCV/alloca.ll
The file was modifiedllvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-common.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/extract-subvector.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vdiv-sdnode.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/insertelt-int-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/calling-conv-half.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssub.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vremu-vp.ll
The file was modifiedllvm/test/CodeGen/RISCV/rem.ll
The file was modifiedllvm/test/CodeGen/RISCV/urem-lkk.ll
The file was modifiedllvm/test/CodeGen/RISCV/hoist-global-addr-base.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-store-int.ll
The file was modifiedllvm/test/CodeGen/RISCV/double-arith.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vsrl-vp.ll
The file was modifiedllvm/test/CodeGen/RISCV/double-intrinsics.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vreductions-int-vp.ll
The file was modifiedllvm/test/CodeGen/RISCV/usub_sat.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vrem-sdnode.ll
The file was modifiedllvm/test/CodeGen/RISCV/rotl-rotr.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/rvv-vscale.i64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rv64zbb-zbp.ll
The file was modifiedllvm/test/CodeGen/RISCV/alu64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vreductions-int-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/bitreverse-sdnode.ll
The file was modifiedllvm/test/CodeGen/RISCV/rv64i-w-insts-legalization.ll
The file was modifiedllvm/test/CodeGen/RISCV/calling-conv-ilp32d.ll
The file was modifiedllvm/test/CodeGen/RISCV/select-optimize-multiple.ll
The file was modifiedllvm/test/CodeGen/RISCV/flt-rounds.ll
The file was modifiedllvm/test/CodeGen/RISCV/double-previous-failure.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/ctlz-sdnode.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-store-fp.ll
The file was modifiedllvm/test/CodeGen/RISCV/float-br-fcmp.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vsplats-i64.ll
The file was modifiedllvm/test/CodeGen/RISCV/double-bitmanip-dagcombines.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmax-sdnode.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vssubu-sdnode.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vxor-sdnode.ll
The file was modifiedllvm/test/CodeGen/RISCV/ssub_sat_plus.ll
The file was modifiedllvm/test/CodeGen/RISCV/sadd_sat.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-bitcast.ll
The file was modifiedllvm/test/CodeGen/RISCV/stack-slot-size.ll
The file was modifiedllvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll
The file was modifiedllvm/test/CodeGen/RISCV/bswap-ctlz-cttz-ctpop.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/smulo-sdnode.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmaxu-sdnode.ll
The file was modifiedllvm/test/CodeGen/RISCV/float-fcmp.ll
The file was modifiedllvm/test/CodeGen/RISCV/urem-vector-lkk.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll
The file was modifiedllvm/test/CodeGen/RISCV/usub_sat_plus.ll
The file was modifiedllvm/test/CodeGen/RISCV/legalize-fneg.ll
The file was modifiedllvm/test/CodeGen/RISCV/copysign-casts.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vand-sdnode.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmulh-sdnode.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/ctpop-sdnode.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/rvv-vscale.i32.ll
The file was modifiedllvm/test/MC/RISCV/rv64i-aliases-valid.s
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vshl-sdnode.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-i1.ll
The file was modifiedllvm/test/CodeGen/RISCV/rv32zbb.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmul-sdnode.ll
The file was modifiedllvm/test/CodeGen/RISCV/calling-conv-lp64-lp64f-lp64d-common.ll
The file was modifiedllvm/test/CodeGen/RISCV/addimm-mulimm.ll
The file was modifiedllvm/test/CodeGen/RISCV/alu32.ll
The file was modifiedllvm/test/CodeGen/RISCV/zext-with-load-is-free.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll
The file was modifiedllvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-ilp32d-common.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-vand-vp.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/rvv-out-arguments.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-abs.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-load-fp.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll
The file was modifiedllvm/test/CodeGen/RISCV/selectcc-to-shiftand.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctpop.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmin-sdnode.ll
The file was modifiedllvm/test/CodeGen/RISCV/split-sp-adjust.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll
The file was modifiedllvm/test/CodeGen/RISCV/select-cc.ll
The file was modifiedllvm/test/CodeGen/RISCV/uadd_sat_plus.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-setcc.ll
The file was modifiedllvm/test/CodeGen/RISCV/float-arith.ll
The file was modifiedllvm/test/MC/RISCV/rvi-aliases-valid.s
The file was modifiedllvm/test/CodeGen/RISCV/rv64zbp.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vssub-sdnode.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-vadd-vp.ll
The file was modifiedllvm/test/CodeGen/RISCV/codemodel-lowering.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-vshl-vp.ll