1. Support custom expedited register set in gdb-remote (details)
  2. Send SVE vg register in custom expedited registerset (details)
  3. [gn build] Manually sync 8da7efb and cac5be4 (details)
  4. [llvm-objdump] Document --mattr=help in --help output (details)
  5. [VE] Specify vector alignments (details)
  6. [VPlan] Use VPUser to manage VPPredInstPHIRecipe operand (NFC). (details)
  7. [VE] Change the behaviour of truncate (details)
  8. Try to fix bots after 112b3cb by removing cortex-a57-misched-mla.s (details)
  9. [VE] Optimize prologue/epilogue instructions (details)
  10. [mac/lld] Add support for response files (details)
  11. Try harder to get rid off cortex-a57-misched-mla.s (details)
Commit b69c09bf43527e79a770efd9886b79e611f8fd59 by omair.javaid
Support custom expedited register set in gdb-remote

This patch adds capability to introduce a custom expedited register set
in gdb remote. Currently we send register set 0 as expedited register set
but for the case of AArch64 SVE we intend to send additional information
about SVE registers size/offset configuration which can be calculated
from vg register. Therefore we will expedited Vg register in case of
AArch64 is in SVE mode to speedup register configuration calculations.

Reviewed By: labath

Differential Revision: https://reviews.llvm.org/D82853
The file was modifiedlldb/source/Host/common/NativeRegisterContext.cpp
The file was modifiedlldb/include/lldb/Host/common/NativeRegisterContext.h
The file was modifiedlldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationServerLLGS.cpp
Commit 4e8aeb97ca41eb202c9c90a9c640a630903c769b by omair.javaid
Send SVE vg register in custom expedited registerset

This patch ovverides GetExpeditedRegisterSet for
NativeRegisterContextLinux_arm64 to send vector granule register in
expedited register set if SVE mode is selected.

Reviewed By: labath

Differential Revision: https://reviews.llvm.org/D82855
The file was modifiedlldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.h
The file was modifiedlldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.h
The file was modifiedlldb/test/API/tools/lldb-server/TestGdbRemoteExpeditedRegisters.py
The file was modifiedlldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.cpp
The file was modifiedlldb/packages/Python/lldbsuite/test/tools/lldb-server/gdbremote_testcase.py
The file was modifiedlldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp
Commit 13c42f4ca7fbe36257d192da02ec46a2c880d938 by hans
[gn build] Manually sync 8da7efb and cac5be4

This adds the clang-tidy concurrency module to the gn build.
The file was addedllvm/utils/gn/secondary/clang-tools-extra/clang-tidy/concurrency/BUILD.gn
The file was modifiedllvm/utils/gn/secondary/clang-tools-extra/clang-tidy/BUILD.gn
Commit c2ead57ccf74900901fdda1cd0fbe9a7a0d1297a by david.spickett
[llvm-objdump] Document --mattr=help in --help output

This does the same as `--mcpu=help` but was only
documented in the user guide.

* Added a test for both options.
* Corrected the single dash in `-mcpu=help` text.

Reviewed By: jhenderson

Differential Revision: https://reviews.llvm.org/D92305
The file was modifiedllvm/tools/llvm-objdump/llvm-objdump.cpp
The file was modifiedllvm/docs/CommandGuide/llvm-objdump.rst
The file was addedllvm/test/tools/llvm-objdump/mattr-mcpu-help.test
Commit 33eac0f2830ee3f362ec0207a3d0e5f0861de8f1 by marukawa
[VE] Specify vector alignments

Specify alignments for all vector types.  Update a regression test also.

Reviewed By: simoll

Differential Revision: https://reviews.llvm.org/D92256
The file was modifiedclang/lib/Basic/Targets/VE.h
The file was modifiedclang/test/CodeGen/target-data.c
The file was modifiedllvm/lib/Target/VE/VETargetMachine.cpp
Commit fe83adb05a8a35835ccc5645fe41c4c82a439cba by flo
[VPlan] Use VPUser to manage VPPredInstPHIRecipe operand (NFC).

VPPredInstPHIRecipe is one of the recipes that was missed during the
initial conversion. This patch adjusts the recipe to also manage its
operand using VPUser.
The file was modifiedllvm/lib/Transforms/Vectorize/VPlanValue.h
The file was modifiedllvm/lib/Transforms/Vectorize/VPlan.h
The file was modifiedllvm/lib/Transforms/Vectorize/VPlan.cpp
The file was modifiedllvm/lib/Transforms/Vectorize/LoopVectorize.cpp
The file was modifiedllvm/test/Transforms/LoopVectorize/vplan-printing.ll
Commit 44a679eaa40cf234c79c241012607ed5f7bada77 by marukawa
[VE] Change the behaviour of truncate

Change the way to truncate i64 to i32 in I64 registers.  VE assumed
sext values previously.  Change it to zext values this time to make
it match to the LLVM behaviour.

Reviewed By: simoll

Differential Revision: https://reviews.llvm.org/D92226
The file was modifiedllvm/test/CodeGen/VE/Scalar/select.ll
The file was modifiedllvm/lib/Target/VE/VEInstrInfo.td
The file was modifiedllvm/test/CodeGen/VE/VELIntrinsics/vbrd.ll
The file was modifiedllvm/test/CodeGen/VE/Scalar/br_jt.ll
The file was modifiedllvm/test/CodeGen/VE/Scalar/select_cc.ll
The file was modifiedllvm/test/CodeGen/VE/VELIntrinsics/lsv.ll
The file was modifiedllvm/test/CodeGen/VE/VELIntrinsics/lvlgen.ll
The file was modifiedllvm/test/CodeGen/VE/Vector/vec_add.ll
The file was modifiedllvm/test/CodeGen/VE/Vector/vec_broadcast.ll
Commit 273641fedc528c3d7ea96020c104a4131e179c62 by hans
Try to fix bots after 112b3cb by removing cortex-a57-misched-mla.s
The file was modifiedllvm/test/CodeGen/ARM/cortex-a57-misched-mla.mir
Commit 686988a50f5009df5a7f184b7debfe012b29bbf8 by marukawa
[VE] Optimize prologue/epilogue instructions

Optimize eliminate FP mechanism.  This time optimize a function which has
no call but fixed stack objects.  LLVM eliminates FP on such functions now.
Also, optimize GOT/PLT registers save/restore instructions if a given
function doesn't uses them.  In addition, remove generating mechanism of
`.cfi` instructions since those are taken from other architectures and not
inspected yet.  Update regression tests, also.

Reviewed By: simoll

Differential Revision: https://reviews.llvm.org/D92251
The file was modifiedllvm/test/CodeGen/VE/Scalar/function_prologue_epilogue.ll
The file was modifiedllvm/test/CodeGen/VE/Scalar/store-align2.ll
The file was modifiedllvm/test/CodeGen/VE/Scalar/load-align2.ll
The file was modifiedllvm/test/CodeGen/VE/Scalar/load-align4.ll
The file was modifiedllvm/test/CodeGen/VE/Scalar/load-align1.ll
The file was modifiedllvm/test/CodeGen/VE/Scalar/fabs.ll
The file was modifiedllvm/test/CodeGen/VE/Scalar/load.ll
The file was modifiedllvm/test/CodeGen/VE/Scalar/stackframe_nocall.ll
The file was modifiedllvm/test/CodeGen/VE/Scalar/stackframe_size.ll
The file was modifiedllvm/test/CodeGen/VE/Scalar/store-align8.ll
The file was modifiedllvm/lib/Target/VE/VEFrameLowering.cpp
The file was modifiedllvm/test/CodeGen/VE/Scalar/store-align4.ll
The file was modifiedllvm/test/CodeGen/VE/Scalar/store.ll
The file was modifiedllvm/test/CodeGen/VE/Scalar/loadrri.ll
The file was modifiedllvm/test/CodeGen/VE/Scalar/sext_zext_load.ll
The file was modifiedllvm/test/CodeGen/VE/Vector/fastcc_callee.ll
The file was modifiedllvm/test/CodeGen/VE/Scalar/callee.ll
The file was modifiedllvm/test/CodeGen/VE/Scalar/fp_fneg.ll
The file was modifiedllvm/test/CodeGen/VE/Scalar/load-align8.ll
The file was modifiedllvm/test/CodeGen/VE/Scalar/stackframe_align.ll
The file was modifiedllvm/lib/Target/VE/VEFrameLowering.h
The file was modifiedllvm/test/CodeGen/VE/Scalar/fcopysign.ll
The file was modifiedllvm/test/CodeGen/VE/Scalar/stackframe_call.ll
The file was modifiedllvm/test/CodeGen/VE/Scalar/store-align1.ll
Commit d20abb1ec3b6ff90cc4221e6a5865ae22fa2f5e9 by thakis
[mac/lld] Add support for response files

ld64 learned about them in Xcode 12, so we should too.

Differential Revision: https://reviews.llvm.org/D92149
The file was modifiedlld/MachO/DriverUtils.cpp
The file was addedlld/test/MachO/responsefile.test
Commit 25d54abca59bcfb6f11e895d744240f09a344018 by hans
Try harder to get rid off cortex-a57-misched-mla.s
The file was modifiedllvm/test/CodeGen/ARM/cortex-a57-misched-mla.mir