Changes

Summary

  1. [AArch64][GlobalISel] Add missing default statement to a switch in the (details)
  2. Driver: Don't look for libc++ headers in the install directory on (details)
  3. export.sh: Fetch sources from GitHub instead of SVN (details)
  4. [PowerPC] Fix MI peephole optimization for splats (details)
Commit 7ac966240184e604c03a7caf62f070ebb2977498 by Amara Emerson
[AArch64][GlobalISel] Add missing default statement to a switch in the
selector.
The file was modifiedllvm/lib/Target/AArch64/AArch64InstructionSelector.cpp
Commit 198fbcb817492ff45946e3f7517de15e8cdf0607 by peter
Driver: Don't look for libc++ headers in the install directory on
Android.
The NDK uses a separate set of libc++ headers in the sysroot. Any
headers in the installation directory are not going to work on Android,
not least because they use a different name for the inline namespace
(std::__1 instead of std::__ndk1).
This effectively makes it impossible to produce a single toolchain that
is capable of targeting both Android and another platform that expects
libc++ headers to be installed in the installation directory, such as
Mac.
In order to allow this scenario to work, stop looking for headers in the
install directory on Android.
Differential Revision: https://reviews.llvm.org/D71154
The file was modifiedclang/lib/Driver/ToolChains/Linux.cpp
The file was modifiedclang/test/Driver/stdlibxx-isystem.cpp
The file was addedclang/test/Driver/android-no-installed-libcxx.cpp
Commit edf6717d8d30034da932b95350898e03c90a5082 by tstellar
export.sh: Fetch sources from GitHub instead of SVN
Reviewers: hansw, jdoerfert
Subscribers: sylvestre.ledru, mgorny, hans, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D70460
The file was modifiedllvm/utils/release/export.sh
Commit 884351547da27e76e14bef5fe20c3e3cb0e89acd by lkail
[PowerPC] Fix MI peephole optimization for splats
Summary: This patch fixes an issue where the PPC MI peephole
optimization pass incorrectly remove a vector swap.
Specifically, the pass can combine a splat/swap to a splat/copy. It uses
`TargetRegisterInfo::lookThruCopyLike` to determine that the operands to
the splat are the same. However, the current logic only compares the
operands based on register numbers. In the case where the splat operands
are ultimately feed from the same physical register, the pass can
incorrectly remove a swap if the feed register for one of the operands
has been clobbered.
This patch adds a check to ensure that the registers feeding are both
virtual registers or the operands to the splat or swap are both the same
register.
Here is an example in pseudo-MIR of what happens in the test cased added
in this patch:
Before PPC MI peephole optimization:
```
%arg = XVADDDP %0, %1
$f1 = COPY %arg.sub_64 call double rint(double)
%res.first = COPY $f1
%vec.res.first = SUBREG_TO_REG 1, %res.first, %subreg.sub_64
%arg.swapped = XXPERMDI %arg, %arg, 2
$f1 = COPY %arg.swapped.sub_64 call double rint(double)
%res.second = COPY $f1
%vec.res.second = SUBREG_TO_REG 1, %res.second, %subreg.sub_64
%vec.res.splat = XXPERMDI %vec.res.first, %vec.res.second, 0
%vec.res = XXPERMDI %vec.res.splat, %vec.res.splat, 2
; %vec.res == [ %vec.res.second[0], %vec.res.first[0] ]
```
After optimization:
```
; ...
%vec.res.splat = XXPERMDI %vec.res.first, %vec.res.second, 0
; lookThruCopyLike(%vec.res.first) == lookThruCopyLike(%vec.res.second)
== $f1
; so the pass replaces the swap with a copy:
%vec.res = COPY %vec.res.splat
; %vec.res == [ %vec.res.first[0], %vec.res.second[0] ]
```
As best as I can tell, this has occurred since r288152, which added
support for lowering certain vector operations to direct moves in the
form of a splat.
Committed for vddvss (Colin Samples). Thanks Colin for the patch!
Differential Revision: https://reviews.llvm.org/D69497
The file was addedllvm/test/CodeGen/PowerPC/mi-peephole-splat.ll
The file was modifiedllvm/lib/Target/PowerPC/PPCMIPeephole.cpp
The file was modifiedllvm/test/CodeGen/PowerPC/vector-constrained-fp-intrinsics.ll