Started 2 mo 13 days ago
Took 47 min

Build #34164 (Aug 2, 2021 2:36:31 PM)

Changes
  1. [SLP][X86] Add fmuladd test coverage (details)
  2. [NFC][InstCombine] Add tests for umin reduction w/ i1 element type (PR51259) (details)
  3. [InstCombine] `vector_reduce_umin(?ext(<n x i1>))` --> `?ext(vector_reduce_and(<n x i1>))` (PR51259) (details)
  4. [NFC][InstCombine] Add tests for umax reduction w/ i1 element type (PR51259) (details)
  5. [InstCombine] `vector_reduce_umax(?ext(<n x i1>))` --> `?ext(vector_reduce_or(<n x i1>))` (PR51259) (details)
  6. [AArch64] Regenerate fp16 tests. (details)
  7. [ValueTracking] Fix computeConstantRange to use "may" instead of "always" semantics for llvm.assume (details)
  8. Revert "[unroll] Move multiple exit costing into consumer pass [NFC]" (details)
  9. [sanitizer] Fix __sanitizer_syscall_post_epoll_wait (details)
  10. [sanitizer] Add callbacks for epoll_pwait2 (details)
  11. [NFC][InstCombine] Add tests for smin reduction w/ i1 element type (PR51259) (details)
  12. [InstCombine] `vector_reduce_smin(?ext(<n x i1>))` --> `?ext(vector_reduce_{or,and}(<n x i1>))` (PR51259) (details)
  13. [NFC][InstCombine] Add tests for smax reduction w/ i1 element type (PR51259) (details)
  14. [InstCombine] `vector_reduce_smax(?ext(<n x i1>))` --> `?ext(vector_reduce_{and,or}(<n x i1>))` (PR51259) (details)

Started by timer (11 times)

This run spent:

  • 1 hr 41 min waiting;
  • 47 min build duration;
  • 2 hr 29 min total from scheduled to completion.
Revision: 2ba285961959af1928e9d9535c869f3334a2030e
Repository: https://github.com/llvm/llvm-zorg.git
  • refs/remotes/origin/main
Revision: 554fc9ad0a24f6689c61d080c9451edd2ddc90b1
Repository: http://labmaster3.local/git/llvm-project.git
  • refs/remotes/origin/main
Revision: 2ba285961959af1928e9d9535c869f3334a2030e
Repository: http://labmaster3.local/git/llvm-zorg.git
  • refs/remotes/origin/main
Test Result (no failures)