[Jenkins]Jenkins

Changes

Summary

  1. [IR] Fix typo in comment of Intrinsics.td (NFC) (details)
  2. [TableGen] Use range-based for loops (NFC) (details)
  3. BPF: fix FIELD_EXISTS relocation with array subscripts (details)
  4. [PowerPC] Remove extra swap for extract+vperm on LE (details)
  5. [mlir][linalg] Add IndexedGenericOp to GenericOp canonicalization. (details)
  6. [XCOFF] handle string constants generation for AIX (details)
  7. [MLIR][SPIRV] Properly (de-)serialize BranchConditionalOp. (details)
Commit e388b9399b03a78219adb3488ec8b2e2a6abcf46 by qixingxue
[IR] Fix typo in comment of Intrinsics.td (NFC)
The file was modifiedllvm/include/llvm/IR/Intrinsics.td
Commit e6cf3d64412c1ddd2fcece337fe0a5f80e386a48 by coelacanthus
[TableGen] Use range-based for loops (NFC)

Use range-based for loops in TableGen.

Reviewed By: Paul-C-Anagnostopoulos

Differential Revision: https://reviews.llvm.org/D101994
The file was modifiedllvm/utils/TableGen/AsmWriterEmitter.cpp
The file was modifiedllvm/utils/TableGen/CodeGenRegisters.cpp
The file was modifiedllvm/utils/TableGen/InstrInfoEmitter.cpp
The file was modifiedllvm/utils/TableGen/DFAPacketizerEmitter.cpp
The file was modifiedllvm/utils/TableGen/IntrinsicEmitter.cpp
The file was modifiedllvm/utils/TableGen/FastISelEmitter.cpp
The file was modifiedllvm/utils/TableGen/X86DisassemblerTables.cpp
The file was modifiedllvm/utils/TableGen/FixedLenDecoderEmitter.cpp
The file was modifiedllvm/utils/TableGen/GICombinerEmitter.cpp
The file was modifiedllvm/utils/TableGen/RegisterInfoEmitter.cpp
The file was modifiedllvm/utils/TableGen/AsmMatcherEmitter.cpp
The file was modifiedllvm/utils/TableGen/CodeGenSchedule.cpp
The file was modifiedllvm/utils/TableGen/RISCVCompressInstEmitter.cpp
Commit 605c811d2b0f71c576740c9a54629804353bf67a by yhs
BPF: fix FIELD_EXISTS relocation with array subscripts

Lorenz Bauer reported an issue in bpf mailing list ([1]) where
for FIELD_EXISTS relocation, if the object is an array subscript,
the patched immediate is the object offset from the base address,
instead of 1.

Currently in BPF AbstractMemberAccess pass, the final offset
from the base address is the patched offset except FIELD_EXISTS
which is 1 unconditionally. In this particular case, the last
data structure access is not a field (struct/union offset)
so it didn't hit the place to set patched immediate to be 1.

This patch fixed the issue by checking the relocation type.
If the type is FIELD_EXISTS, just set to 1.
Tested by modifying some bpf selftests, libbpf is okay with
such types with FIELD_EXISTS relocation.

 [1] https://lore.kernel.org/bpf/CACAyw99n-cMEtVst7aK-3BfHb99GMEChmRLCvhrjsRpHhPrtvA@mail.gmail.com/

Differential Revision: https://reviews.llvm.org/D102036
The file was addedllvm/test/CodeGen/BPF/CORE/intrinsic-fieldinfo-existence-4.ll
The file was modifiedllvm/lib/Target/BPF/BPFAbstractMemberAccess.cpp
Commit f7294ac8093a2fbd8c00254580eaac6c4e1f7b24 by qiucofan
[PowerPC] Remove extra swap for extract+vperm on LE

This is a simple fix on LE. On BE, vector shuffles are categorized into
different ops. We may need more work to eliminate these in
tablegen/pre-isel.

Reviewed By: nemanjai

Differential Revision: https://reviews.llvm.org/D101605
The file was modifiedllvm/test/CodeGen/PowerPC/vec_extract_p9.ll
The file was modifiedllvm/lib/Target/PowerPC/PPCInstrVSX.td
Commit 26e916334ebc3cb34f1c020e00c731bd60b0323a by gysit
[mlir][linalg] Add IndexedGenericOp to GenericOp canonicalization.

Replace all `linalg.indexed_generic` ops by `linalg.generic` ops that access the iteration indices using the `linalg.index` op.

Differential Revision: https://reviews.llvm.org/D101612
The file was modifiedmlir/lib/Dialect/Linalg/IR/LinalgOps.cpp
The file was modifiedmlir/test/Dialect/Linalg/canonicalize.mlir
The file was modifiedmlir/include/mlir/Dialect/Linalg/IR/LinalgStructuredOps.td
The file was modifiedmlir/test/Dialect/Linalg/tile-indexed-generic.mlir
The file was modifiedmlir/test/Dialect/Linalg/fusion-indexed-generic.mlir
The file was modifiedmlir/test/Dialect/Linalg/reshape_fusion.mlir
The file was modifiedmlir/test/Dialect/Linalg/fusion-tensor.mlir
The file was modifiedmlir/test/Dialect/Linalg/bufferize.mlir
The file was modifiedmlir/test/Dialect/Linalg/tile-tensors.mlir
The file was modifiedmlir/test/Dialect/Linalg/canonicalize-duplicate-inputs.mlir
Commit a95473c563bf5b6d657f5e5fa99bd551b2df339b by czhengsz
[XCOFF] handle string constants generation for AIX

This follows https://www.ibm.com/docs/en/aix/7.2?topic=constants-string

Reviewed By: hubert.reinterpretcast

Differential Revision: https://reviews.llvm.org/D101280
The file was modifiedllvm/lib/MC/MCAsmStreamer.cpp
The file was modifiedllvm/include/llvm/MC/MCAsmInfo.h
The file was modifiedllvm/lib/MC/MCAsmInfoXCOFF.cpp
The file was addedllvm/test/CodeGen/PowerPC/aix-filename-special-character-double-quotation.ll
The file was addedllvm/test/CodeGen/PowerPC/aix-filename-special-character-single-quotation.ll
Commit e4dee7e7309a060bd8dd3c9df0a708157fc935d4 by kareem.ergawy
[MLIR][SPIRV] Properly (de-)serialize BranchConditionalOp.

Implements proper (de-)serialization logic for BranchConditionalOp when
such ops have true/false target operands.

Reviewed By: antiagainst

Differential Revision: https://reviews.llvm.org/D101602
The file was modifiedmlir/lib/Target/SPIRV/Deserialization/Deserializer.cpp
The file was modifiedmlir/lib/Target/SPIRV/Deserialization/Deserializer.h
The file was modifiedmlir/lib/Target/SPIRV/Serialization/Serializer.cpp
The file was modifiedmlir/test/Target/SPIRV/phi.mlir