Changes

Summary

  1. [PassManager] add helper function to hold set of vector passes (2nd try) (details)
  2. [GlobalISel][IRTranslator] Fix bit-test lowering dropping phi edges. (details)
  3. [RISCV] Validate the SEW and LMUL operands to __builtin_rvv_vsetvli(max) (details)
  4. [scudo] [GWP-ASan] Add GWP-ASan variant of scudo benchmarks. (details)
  5. [libc] Rever "Simplifies multi implementations and benchmarks". (details)
  6. [mlir][linalg] Restrict distribution to parallel dims (details)
  7. [TargetLowering] Only inspect attributes in the arguments for ArgListEntry (details)
  8. [PowerPC] Spilling to registers does not require frame index scavenging (details)
  9. [lld-macho][nfc] Clean up tests (details)
  10. [lld-macho] Treat undefined symbols uniformly (details)
  11. [lld-macho] Fix order file arch filtering (details)
  12. [mlir][sparse] complete migration to sparse tensor type (details)
  13. [Scudo] Use GWP-ASan's aligned allocations and fixup postalloc hooks. (details)
  14. [Inliner] Fix noalias metadata handling for instructions simplified during cloning (PR50270) (details)
  15. [ORC] Use a unique_function rather than std::function for dispatchTask. (details)
  16. [NFC] Use ArgListEntry indirect types more in ISel lowering (details)
  17. [lld][WebAssembly] Initial support merging string data (details)
  18. [VecLib] Add support for vector fns from Darwin's libsystem. (details)
  19. [InstCombine] Fold comparison of integers by parts (details)
  20. [mlir][Python] Finish adding RankedTensorType support for encoding. (details)
  21. [mlir] Fix windows build bot break due to use of `alloca` in a test. (details)
  22. [test] Put aix-xcoff-huge-relocs.ll under expensive checks (details)
  23. [libcxx] removes `weak_equality` and `strong_equality` from <compare> (details)
  24. [NFC][X86][MCA] AMD Zen 3: add tests for same-reg MMX PCMPEQ (details)
  25. [X86] AMD Zen 3: same-reg PCMPEQ is an MMX all-ones dep breaking idiom (details)
  26. [NFC][X86][MCA] AMD Zen 3: add tests for same-reg XMM SSE PCMP (details)
  27. [X86] AMD Zen 3: same-reg SSE XMM PCMP is dep breaking one-idiom (details)
  28. [NFC][X86][MCA] AMD Zen 3: add tests for same-re AVX XMM VPCMP (details)
  29. [X86] AMD Zen 3: same-reg AVX XMM VPCMP is dep breaking one-idiom (details)
  30. [NFC][X86][MCA] AMD Zen 3: add tests for same-re AVX YMM VPCMP (details)
  31. [X86] AMD Zen 3: same-reg AVX YMM VPCMP is dep breaking one-idiom (details)
  32. [clang-tidy] Aliasing: Add support for captures. (details)
  33. [clang-tidy] Aliasing: Add more support for captures. (details)
  34. [clang-tidy] Aliasing: Add support for aggregates with references. (details)
  35. [InstCombine] add tests for extract-subvector of insert; NFC (details)
  36. [InstCombine] fold extract subvector of bitcast insertelt (details)
  37. Remove some unnecessary explicit defaulted copy ctors to cleanup -Wdeprecated-copy (details)
  38. Clangd Matchers.h: Fix -Wdeprecated-copy by making the defaulted copy ctor and deleted copy assignment operators explicit (details)
  39. [Hexagon] Handle loads and stores of scalar predicate vectors (details)
Commit 88d8f10baf30b0df18eb542c426afc29b69f1313 by spatel
[PassManager] add helper function to hold set of vector passes (2nd try)

This is better no-functional-change-intended than the 1st attempt.
As noted in D102002, there were at least 2 diffs that went
unchecked in pass manager regressions tests: different pass
parameters (SimplifyCFG) and an extension point/callback.
Those should be lifted from the original code blocks correctly
now.
The file was modifiedllvm/lib/Passes/PassBuilder.cpp
The file was modifiedllvm/include/llvm/Transforms/IPO/PassManagerBuilder.h
The file was modifiedllvm/lib/Transforms/IPO/PassManagerBuilder.cpp
The file was modifiedllvm/include/llvm/Passes/PassBuilder.h
Commit dc75499998352ffbbe0d1da196631ddb73ad47f3 by Amara Emerson
[GlobalISel][IRTranslator] Fix bit-test lowering dropping phi edges.

For contiguous ranges we drop the last bit-test case but in doing so we skip
adding the new MBB PHI edges to the list of replacement PHI edges, and as a
result we incorrectly omit them in the G_PHI in finishPendingPhis().

Was found when bootstrapping clang with -O3 and GlobalISel enabled on Apple Silicon.
The file was modifiedllvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/irtranslator-switch-bittest.ll
Commit 18f3a14e1328c813fa5dbacc9bb931d22f0669cd by craig.topper
[RISCV] Validate the SEW and LMUL operands to __builtin_rvv_vsetvli(max)

These are required to be constants, this patch makes sure they
are in the accepted range of values.

These are usually created by wrappers in the riscv_vector.h header
which should always be correct. This patch protects against a user
using the builtin directly.

Reviewed By: khchen

Differential Revision: https://reviews.llvm.org/D102086
The file was modifiedclang/include/clang/Basic/DiagnosticSemaKinds.td
The file was addedclang/test/CodeGen/RISCV/rvv_errors.c
The file was modifiedclang/include/clang/Sema/Sema.h
The file was modifiedclang/lib/Sema/SemaChecking.cpp
Commit 8936608e6f4dbd2a80acde660849cd87ef5c9d26 by 31459023+hctim
[scudo] [GWP-ASan] Add GWP-ASan variant of scudo benchmarks.

GWP-ASan is the "production" variant as compiled by compiler-rt, and it's useful to be able to benchmark changes in GWP-ASan or Scudo's GWP-ASan hooks across versions. GWP-ASan is sampled, and sampled allocations are much slower, but given the amount of allocations that happen under test here - we actually get a reasonable representation of GWP-ASan's negligent performance impact between runs.

Reviewed By: cryptoad

Differential Revision: https://reviews.llvm.org/D101865
The file was modifiedcompiler-rt/lib/scudo/standalone/benchmarks/CMakeLists.txt
The file was modifiedcompiler-rt/lib/scudo/standalone/benchmarks/malloc_benchmark.cpp
The file was modifiedcompiler-rt/lib/scudo/standalone/combined.h
Commit 0c64cef8943546fce28936bb51cce2e22f88c698 by sivachandra
[libc] Rever "Simplifies multi implementations and benchmarks".

This reverts commit 541f107871bc9c020925a6e5342542a47c902d12 as the bots
are failing with unknown architecture "x86-64-v*". Will let the original
author decide on the right course of action to correct the problem and
reland.
The file was addedlibc/src/string/aarch64/CMakeLists.txt
The file was modifiedlibc/cmake/modules/LLVMLibCCheckCpuFeatures.cmake
The file was addedlibc/src/string/x86_64/CMakeLists.txt
The file was modifiedlibc/test/src/string/CMakeLists.txt
The file was modifiedlibc/src/string/CMakeLists.txt
Commit 7e71823f1deb54a1465bc4040f4e3158357f71df by antiagainst
[mlir][linalg] Restrict distribution to parallel dims

According to the API contract, LinalgLoopDistributionOptions
expects to work on parallel iterators. When getting processor
information, only loop ranges for parallel dimensions should
be fed in. But right now after generating scf.for loop nests,
we feed in *all* loops, including the ones materialized for
reduction iterators. This can cause unexpected distribution
of reduction dimensions. This commit fixes it.

Reviewed By: mravishankar

Differential Revision: https://reviews.llvm.org/D102079
The file was modifiedmlir/test/lib/Transforms/TestLinalgTransforms.cpp
The file was modifiedmlir/test/Dialect/Linalg/tile-and-distribute.mlir
The file was modifiedmlir/lib/Dialect/Linalg/Utils/Utils.cpp
Commit 16748bd2fb1fe10d7d097961f1988327338f3f9f by aeubanks
[TargetLowering] Only inspect attributes in the arguments for ArgListEntry

Parameter attributes are considered part of the function [1], and like
mismatched calling conventions [2], we can't have the verifier check for
mismatched parameter attributes.

[1] https://llvm.org/docs/LangRef.html#parameter-attributes
[2] https://llvm.org/docs/FAQ.html#why-does-instcombine-simplifycfg-turn-a-call-to-a-function-with-a-mismatched-calling-convention-into-unreachable-why-not-make-the-verifier-reject-it

Reviewed By: rnk

Differential Revision: https://reviews.llvm.org/D101806
The file was modifiedllvm/test/CodeGen/AMDGPU/callee-special-input-vgprs-packed.ll
The file was modifiedllvm/test/CodeGen/X86/preallocated.ll
The file was modifiedllvm/test/CodeGen/SystemZ/args-03.ll
The file was modifiedllvm/test/CodeGen/AArch64/arm64-this-return.ll
The file was addedllvm/test/CodeGen/X86/mismatched-byval.ll
The file was modifiedllvm/test/CodeGen/SPARC/64abi.ll
The file was modifiedllvm/test/CodeGen/X86/fast-cc-merge-stack-adj.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/call-argument-types.ll
The file was modifiedllvm/test/CodeGen/AArch64/tailcall-explicit-sret.ll
The file was modifiedllvm/test/CodeGen/SystemZ/args-02.ll
The file was modifiedllvm/test/CodeGen/ARM/returned-ext.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/callee-special-input-vgprs.ll
The file was modifiedllvm/docs/ReleaseNotes.rst
The file was modifiedllvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
The file was modifiedllvm/test/CodeGen/ARM/this-return.ll
The file was modifiedllvm/test/CodeGen/X86/movtopush.ll
The file was modifiedllvm/test/CodeGen/X86/fast-cc-pass-in-regs.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/gfx-callable-argument-types.ll
The file was modifiedllvm/test/CodeGen/X86/pop-stack-cleanup.ll
The file was modifiedllvm/test/CodeGen/AArch64/bitfield-extract.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/tail-call-amdgpu-gfx.ll
The file was modifiedllvm/test/CodeGen/ARM/ipra-r0-returned.ll
The file was modifiedllvm/test/CodeGen/X86/tailcall-msvc-conventions.ll
Commit 6215f49b8f2fa479535ec27a0f029081ac394100 by stefanp
[PowerPC] Spilling to registers does not require frame index scavenging

If spills are to registers instead of to the stack then a copy will be used
and frame index scavenging is not required.

This patch adds debug info to frame index scavenging and makes sure that
spilling to registers does not cause frame index scavenging.

Reviewed By: nemanjai, #powerpc

Differential Revision: https://reviews.llvm.org/D101360
The file was addedllvm/test/CodeGen/PowerPC/frame_index_scavenging.mir
The file was modifiedllvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
Commit 3d5e5066f1af50ea622d136e9543aedae178c8e5 by jezng
[lld-macho][nfc] Clean up tests

* Remove unnecessary `rm -rf %t`s
* Have lc-linker-option.ll use the right comment marker
The file was modifiedlld/test/MachO/dependency-info.s
The file was modifiedlld/test/MachO/adhoc-codesign.s
The file was modifiedlld/test/MachO/invalid/undefined-symbol.s
The file was modifiedlld/test/MachO/t.s
The file was modifiedlld/test/MachO/why-load.s
The file was modifiedlld/test/MachO/u.s
The file was modifiedlld/test/MachO/flat-namespace.s
The file was modifiedlld/test/MachO/lc-linker-option.ll
The file was modifiedlld/test/MachO/U-dynamic-lookup.s
The file was modifiedlld/test/MachO/sub-library.s
Commit 2516b0b5261d5f1fe7cfe357550a826f88fc68b7 by jezng
[lld-macho] Treat undefined symbols uniformly

In particular, we should apply the `-undefined` behavior to all
such symbols, include those that are specified via the command line
(i.e.  `-e`, `-u`, and `-exported_symbol`). ld64 supports this too.

Reviewed By: #lld-macho, thakis

Differential Revision: https://reviews.llvm.org/D102143
The file was modifiedlld/MachO/Writer.cpp
The file was modifiedlld/test/MachO/u.s
The file was modifiedlld/MachO/SymbolTable.h
The file was modifiedlld/MachO/Driver.cpp
The file was modifiedlld/test/MachO/entry-symbol.s
The file was modifiedlld/test/MachO/export-options.s
The file was modifiedlld/MachO/SymbolTable.cpp
Commit b1c3c2e4fc219c23e311fe56d8687fdf6bba3c89 by jezng
[lld-macho] Fix order file arch filtering

We had a hardcoded check and a stale TODO, written back when we only had
support for one architecture.

Reviewed By: #lld-macho, thakis

Differential Revision: https://reviews.llvm.org/D102154
The file was modifiedlld/MachO/Driver.cpp
The file was modifiedlld/test/MachO/order-file.s
The file was modifiedlld/MachO/InputFiles.cpp
The file was modifiedlld/MachO/Target.h
Commit 96a23911f6d72cc1ef0788b34caa553f1ce99c5d by ajcbik
[mlir][sparse] complete migration to sparse tensor type

A very elaborate, but also very fun revision because all
puzzle pieces are finally "falling in place".

1. replaces lingalg annotations + flags with proper sparse tensor types
2. add rigorous verification on sparse tensor type and sparse primitives
3. removes glue and clutter on opaque pointers in favor of sparse tensor types
4. migrates all tests to use sparse tensor types

NOTE: next CL will remove *all* obsoleted sparse code in Linalg

Reviewed By: bixia

Differential Revision: https://reviews.llvm.org/D102095
The file was modifiedmlir/lib/ExecutionEngine/SparseUtils.cpp
The file was modifiedmlir/test/Dialect/SparseTensor/sparse_2d.mlir
The file was modifiedmlir/test/Dialect/SparseTensor/sparse_3d.mlir
The file was modifiedmlir/test/Dialect/SparseTensor/sparse_lower.mlir
The file was modifiedmlir/lib/Dialect/SparseTensor/Transforms/SparseTensorPasses.cpp
The file was modifiedmlir/test/Dialect/SparseTensor/conversion.mlir
The file was modifiedmlir/test/Dialect/SparseTensor/roundtrip.mlir
The file was modifiedmlir/test/Dialect/SparseTensor/sparse_nd.mlir
The file was modifiedmlir/lib/Dialect/SparseTensor/Transforms/Sparsification.cpp
The file was modifiedmlir/test/Dialect/SparseTensor/roundtrip_encoding.mlir
The file was modifiedmlir/test/Dialect/SparseTensor/invalid_encoding.mlir
The file was modifiedmlir/test/Integration/Dialect/SparseTensor/CPU/sparse_matvec.mlir
The file was removedmlir/test/Dialect/SparseTensor/sparse_invalid.mlir
The file was modifiedmlir/include/mlir/Dialect/SparseTensor/Transforms/Passes.h
The file was addedmlir/test/Dialect/SparseTensor/invalid.mlir
The file was modifiedmlir/lib/Dialect/SparseTensor/Transforms/SparseTensorConversion.cpp
The file was modifiedmlir/test/Dialect/SparseTensor/sparse_1d.mlir
The file was modifiedmlir/test/Integration/Dialect/SparseTensor/CPU/sparse_sum.mlir
The file was modifiedmlir/test/Integration/Dialect/SparseTensor/CPU/sparse_sampled_matmul.mlir
The file was modifiedmlir/include/mlir/Dialect/SparseTensor/IR/SparseTensor.h
The file was modifiedmlir/test/Dialect/SparseTensor/sparse_parallel.mlir
The file was modifiedmlir/include/mlir/Dialect/SparseTensor/IR/SparseTensorOps.td
The file was modifiedmlir/test/Dialect/SparseTensor/sparse_storage.mlir
The file was modifiedmlir/test/Dialect/SparseTensor/sparse_vector.mlir
The file was modifiedmlir/lib/Dialect/SparseTensor/IR/SparseTensorDialect.cpp
Commit e78b64df98878d1da56275e0c272ed58364da3ad by 31459023+hctim
[Scudo] Use GWP-ASan's aligned allocations and fixup postalloc hooks.

This patch does a few cleanup things:
1. The non-standalone scudo has a problem where GWP-ASan allocations
may not meet alignment requirements where Scudo was requested to have
alignment >= 16. Use the new GWP-ASan API to fix this.
2. The standalone variant loses some debugging information inside of
GWP-ASan because we ask GWP-ASan to allocate an aligned size in the
frontend. This means reports end up with 'UaF on a 16-byte allocation'
for a 1-byte allocation with 16-byte alignment. Also use the new API to
fix this.
3. Add post-alloc hooks for GWP-ASan intercepted allocations, and add
stats tracking for GWP-ASan allocations.
4. Add a small test that checks the alignment of the frontend
allocator, so that it can be used under GWP-ASan torture mode.
5. Add GWP-ASan torture mode as a testing configuration to catch these
regressions.

Depends on D94830, D95889.

Reviewed By: cryptoad

Differential Revision: https://reviews.llvm.org/D95884
The file was addedcompiler-rt/test/scudo/standalone/unit/gwp_asan/lit.site.cfg.py.in
The file was modifiedcompiler-rt/lib/scudo/standalone/stats.h
The file was modifiedcompiler-rt/lib/scudo/standalone/tests/wrappers_cpp_test.cpp
The file was modifiedcompiler-rt/lib/scudo/standalone/combined.h
The file was modifiedcompiler-rt/test/scudo/standalone/CMakeLists.txt
The file was modifiedcompiler-rt/lib/scudo/scudo_allocator.cpp
The file was modifiedcompiler-rt/lib/scudo/standalone/tests/wrappers_c_test.cpp
The file was modifiedcompiler-rt/lib/gwp_asan/common.h
Commit aa9b02ac75350a6c7c949dd24d5c6a931be26ff9 by nikita.ppv
[Inliner] Fix noalias metadata handling for instructions simplified during cloning (PR50270)

Instead of using VMap, which may include instructions from the
caller as a result of simplification, iterate over the
(FirstNewBlock, Caller->end()) range, which will only include new
instructions.

Fixes https://bugs.llvm.org/show_bug.cgi?id=50270.

Differential Revision: https://reviews.llvm.org/D102110
The file was modifiedllvm/lib/Transforms/Utils/InlineFunction.cpp
The file was addedllvm/test/Transforms/Inline/pr50270.ll
Commit 9507bace6c122898ac1e7c01bbdcf3c448214c81 by Lang Hames
[ORC] Use a unique_function rather than std::function for dispatchTask.
The file was modifiedllvm/include/llvm/ExecutionEngine/Orc/Core.h
Commit 85af8a8c1b574faa0d5d57d189ae051debdfada8 by aeubanks
[NFC] Use ArgListEntry indirect types more in ISel lowering

For opaque pointers, we're trying to avoid uses of
PointerType::getElementType().

A couple of ISel places use PointerType::getElementType(). Some of these
are easy to fix by using ArgListEntry's indirect types.

The inalloca type wasn't stored there, as opposed to preallocated and
byval which have their indirect types available, so add it and use it.

Differential Revision: https://reviews.llvm.org/D101713
The file was modifiedllvm/include/llvm/CodeGen/TargetLowering.h
The file was modifiedllvm/lib/CodeGen/SelectionDAG/FastISel.cpp
The file was modifiedllvm/include/llvm/IR/InstrTypes.h
The file was modifiedllvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
The file was modifiedllvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
Commit 5000a1b4b9edeb9e994f2a5b36da8d48599bea49 by sbc
[lld][WebAssembly] Initial support merging string data

This change adds support for a new WASM_SEG_FLAG_STRINGS flag in
the object format which works in a similar fashion to SHF_STRINGS
in the ELF world.

Unlike the ELF linker this support is currently limited:
- No support for SHF_MERGE (non-string merging)
- Always do full tail merging ("lo" can be merged with "hello")
- Only support single byte strings (p2align 0)

Like the ELF linker merging is only performed at `-O1` and above.

This fixes part of https://bugs.llvm.org/show_bug.cgi?id=48828,
although crucially it doesn't not currently support debug sections
because they are not represented by data segments (they are custom
sections)

Differential Revision: https://reviews.llvm.org/D97657
The file was modifiedllvm/lib/MC/MCSectionWasm.cpp
The file was addedllvm/test/MC/WebAssembly/section-flags-changed.s
The file was modifiedlld/wasm/Driver.cpp
The file was modifiedllvm/tools/obj2yaml/wasm2yaml.cpp
The file was modifiedllvm/lib/MC/MCObjectFileInfo.cpp
The file was modifiedllvm/lib/MC/WasmObjectWriter.cpp
The file was modifiedllvm/include/llvm/BinaryFormat/Wasm.h
The file was modifiedlld/wasm/InputFiles.cpp
The file was modifiedlld/wasm/Writer.cpp
The file was modifiedllvm/include/llvm/MC/MCContext.h
The file was modifiedllvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
The file was modifiedlld/wasm/Symbols.cpp
The file was modifiedlld/wasm/OutputSegment.h
The file was modifiedlld/wasm/CMakeLists.txt
The file was modifiedllvm/lib/Target/WebAssembly/AsmParser/WebAssemblyAsmParser.cpp
The file was modifiedllvm/lib/MC/MCContext.cpp
The file was modifiedlld/wasm/InputChunks.cpp
The file was modifiedllvm/lib/ObjectYAML/WasmYAML.cpp
The file was modifiedlld/wasm/SyntheticSections.cpp
The file was modifiedlld/wasm/InputChunks.h
The file was addedlld/test/wasm/merge-string.s
The file was modifiedllvm/include/llvm/MC/MCSectionWasm.h
The file was addedlld/wasm/OutputSegment.cpp
The file was modifiedllvm/lib/MC/MCParser/WasmAsmParser.cpp
The file was modifiedllvm/lib/Object/WasmObjectFile.cpp
Commit 93a9a8a8d90f5b9bb6965ebb1104082692d41833 by flo
[VecLib] Add support for vector fns from Darwin's libsystem.

This patch adds support for Darwin's libsystem math vector functions to
TLI. Darwin's libsystem provides a range of vector functions for libm
functions.

This initial patch only adds the 2 x double and 4 x float versions,
which are available on both X86 and ARM64. On X86, wider vector versions
are supported as well.

Reviewed By: jroelofs

Differential Revision: https://reviews.llvm.org/D101856
The file was modifiedllvm/lib/Analysis/TargetLibraryInfo.cpp
The file was addedllvm/test/CodeGen/Generic/replace-intrinsics-with-veclib-darwin-libsystem-m.ll
The file was addedllvm/test/Transforms/LoopVectorize/AArch64/veclib-calls-libsystem-darwin.ll
The file was modifiedllvm/include/llvm/Analysis/VecFuncs.def
The file was modifiedllvm/include/llvm/Analysis/TargetLibraryInfo.h
Commit 463ea28e96c78f484d9ea44912d9bc70ff084c86 by nikita.ppv
[InstCombine] Fold comparison of integers by parts

Let's say you represent (i32, i32) as an i64 from which the parts
are extracted with lshr/trunc. Then, if you compare two tuples by
parts you get something like A[0] == B[0] && A[1] == B[1], just
that the part extraction happens by lshr/trunc and not a narrow
load or similar.

The fold implemented here reduces such equality comparisons by
converting them into a comparison on a larger part of the integer
(which might be the whole integer). It handles both the "and of eq"
and the conjugated "or of ne" case.

I'm being conservative with one-use for now, though this could be
relaxed if profitable (the base pattern converts 11 instructions
into 5 instructions, but there's quite a few variations on how it
can play out).

Differential Revision: https://reviews.llvm.org/D101232
The file was modifiedllvm/test/Transforms/InstCombine/eq-of-parts.ll
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
Commit a2c8aebd8f8f81ba0af1c50580036faf73e8e2dc by stellaraccident
[mlir][Python] Finish adding RankedTensorType support for encoding.

Differential Revision: https://reviews.llvm.org/D102184
The file was modifiedmlir/test/CAPI/ir.c
The file was modifiedmlir/lib/CAPI/IR/BuiltinTypes.cpp
The file was modifiedmlir/test/python/ir/builtin_types.py
The file was modifiedmlir/include/mlir-c/BuiltinTypes.h
The file was modifiedmlir/lib/Bindings/Python/IRTypes.cpp
The file was modifiedmlir/test/python/dialects/sparse_tensor/dialect.py
Commit 295087644a468c47a1dbfaca2b5ea552204ab35f by stellaraccident
[mlir] Fix windows build bot break due to use of `alloca` in a test.

Differential Revision: https://reviews.llvm.org/D102189
The file was modifiedmlir/test/CAPI/sparse_tensor.c
Commit edfa44b732984541105917934b1d9838fbf368ae by aeubanks
[test] Put aix-xcoff-huge-relocs.ll under expensive checks

It is an order of magnitude slower than the second slowest test
according to obj/llvm/test/.lit_test_times.txt.

The two slowest are:
2.870437e+02 CodeGen/PowerPC/aix-xcoff-huge-relocs.ll
2.850697e+01 tools/llvm-readobj/ELF/file-header-machine-types.test

Reviewed By: hubert.reinterpretcast

Differential Revision: https://reviews.llvm.org/D102190
The file was modifiedllvm/test/CodeGen/PowerPC/aix-xcoff-huge-relocs.ll
Commit 4ff2fe1df0cea28e3ef2963116385c86bf3b5055 by cjdb
[libcxx] removes `weak_equality` and `strong_equality` from <compare>

`weak_equality` and `strong_equality` were removed before being
standardised, and need to be removed.

Also adjusts `common_comparison_category` since its test needed
adjusting due to the equality deletions.

Differential Revision: https://reviews.llvm.org/D100283
The file was removedlibcxx/test/std/language.support/cmp/cmp.strongeq/cmp.strongeq.pass.cpp
The file was modifiedlibcxx/include/compare
The file was modifiedlibcxx/test/std/language.support/cmp/cmp.weakord/weakord.pass.cpp
The file was modifiedlibcxx/test/std/language.support/cmp/cmp.common/common_comparison_category.pass.cpp
The file was modifiedlibcxx/test/std/language.support/cmp/cmp.partialord/partialord.pass.cpp
The file was modifiedlibcxx/test/std/language.support/cmp/cmp.strongord/strongord.pass.cpp
The file was removedlibcxx/test/std/language.support/cmp/cmp.weakeq/cmp.weakeq.pass.cpp
Commit ba225ce961b4ec5e4d64b393b042bbaae5e9b41b by lebedev.ri
[NFC][X86][MCA] AMD Zen 3: add tests for same-reg MMX PCMPEQ
The file was addedllvm/test/tools/llvm-mca/X86/Znver3/one-idioms-mmx.s
Commit b24edfff4fb16549b3e5ec434ca79dd86fdb4e43 by lebedev.ri
[X86] AMD Zen 3: same-reg PCMPEQ is an MMX all-ones dep breaking idiom

They are, however, not zero-cycle, and do actually execute.

As measured by exegesis, and confirmed by ref docs.
The file was modifiedllvm/test/tools/llvm-mca/X86/Znver3/one-idioms-mmx.s
The file was modifiedllvm/lib/Target/X86/X86ScheduleZnver3.td
Commit 0e538f937a02eb5a1a999319ef023932be64e130 by lebedev.ri
[NFC][X86][MCA] AMD Zen 3: add tests for same-reg XMM SSE PCMP
The file was addedllvm/test/tools/llvm-mca/X86/Znver3/one-idioms-sse-xmm.s
Commit 0f3bcb97efa8ac6c3277390c3fa2085ee72b074e by lebedev.ri
[X86] AMD Zen 3: same-reg SSE XMM PCMP is dep breaking one-idiom

As measured by exegesis, and confirmed by ref docs.
Much like with MMX PCMP, it does actually have to execute, though.
The file was modifiedllvm/test/tools/llvm-mca/X86/Znver3/one-idioms-sse-xmm.s
The file was modifiedllvm/lib/Target/X86/X86ScheduleZnver3.td
Commit f59db6c4f84590aeeaf7753b8957a58cad12867b by lebedev.ri
[NFC][X86][MCA] AMD Zen 3: add tests for same-re AVX XMM VPCMP
The file was addedllvm/test/tools/llvm-mca/X86/Znver3/one-idioms-avx-xmm.s
Commit 29532453370044a4c2ddeea130a3db1648b42aa9 by lebedev.ri
[X86] AMD Zen 3: same-reg AVX XMM VPCMP is dep breaking one-idiom

As measured by exegesis, and confirmed by ref docs.
Again, it's not zero-cycle.
The file was modifiedllvm/lib/Target/X86/X86ScheduleZnver3.td
The file was modifiedllvm/test/tools/llvm-mca/X86/Znver3/one-idioms-avx-xmm.s
Commit 5864e7b86b919651e63ede7ba77ddca48385ea4d by lebedev.ri
[NFC][X86][MCA] AMD Zen 3: add tests for same-re AVX YMM VPCMP
The file was addedllvm/test/tools/llvm-mca/X86/Znver3/one-idioms-avx-ymm.s
Commit 6a64c462eb82f5f37e4ce512f4c25c474ddfcc4c by lebedev.ri
[X86] AMD Zen 3: same-reg AVX YMM VPCMP is dep breaking one-idiom

As measured by exegesis, and confirmed by ref docs.
Still not zero-cycle :)
The file was modifiedllvm/lib/Target/X86/X86ScheduleZnver3.td
The file was modifiedllvm/test/tools/llvm-mca/X86/Znver3/one-idioms-avx-ymm.s
Commit 43f4331edfb595979f6854351d24f9a9219595fa by Artem Dergachev
[clang-tidy] Aliasing: Add support for captures.

The utility function clang::tidy::utils::hasPtrOrReferenceInFunc() scans the
function for pointer/reference aliases to a given variable. It currently scans
for operator & over that variable and for declarations of references to that
variable.

This patch makes it also scan for C++ lambda captures by reference
and for Objective-C block captures.

Differential Revision: https://reviews.llvm.org/D96215
The file was modifiedclang-tools-extra/test/clang-tidy/checkers/bugprone-redundant-branch-condition.cpp
The file was modifiedclang-tools-extra/test/clang-tidy/checkers/bugprone-infinite-loop.cpp
The file was modifiedclang-tools-extra/clang-tidy/utils/Aliasing.cpp
Commit 9b292e0edcd4e889dbcf4bbaad6c1cc80fffcfd1 by Artem Dergachev
[clang-tidy] Aliasing: Add more support for captures.

D96215 takes care of the situation where the variable is captured into
a nearby lambda. This patch takes care of the situation where
the current function is the lambda and the variable is one of its captures
from an enclosing scope.

The analogous problem for ^{blocks} is already handled automagically
by D96215.

Differential Revision: https://reviews.llvm.org/D101787
The file was modifiedclang-tools-extra/clang-tidy/utils/Aliasing.cpp
The file was modifiedclang-tools-extra/test/clang-tidy/checkers/bugprone-redundant-branch-condition.cpp
The file was modifiedclang-tools-extra/test/clang-tidy/checkers/bugprone-infinite-loop.cpp
Commit 91ca3269a1b544db1303b496101fd9d6fe953277 by Artem Dergachev
[clang-tidy] Aliasing: Add support for aggregates with references.

When a variable is used in an initializer of an aggregate
for its reference-type field this counts as aliasing.

Differential Revision: https://reviews.llvm.org/D101791
The file was modifiedclang-tools-extra/test/clang-tidy/checkers/bugprone-infinite-loop.cpp
The file was modifiedclang-tools-extra/clang-tidy/utils/Aliasing.cpp
Commit 8a74cc139d1fbafcf1dd0482490633924a46599a by spatel
[InstCombine] add tests for extract-subvector of insert; NFC
The file was modifiedllvm/test/Transforms/InstCombine/shufflevec-bitcast.ll
Commit 5577e866912e86147206ffc586e4f080c59ae4bf by spatel
[InstCombine] fold extract subvector of bitcast insertelt

This is visible in the original example from:
https://llvm.org/PR50055
(but this change doesn't solve the bug)

https://alive2.llvm.org/ce/z/vM_Yq-
The file was modifiedllvm/test/Transforms/InstCombine/shufflevec-bitcast.ll
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineVectorOps.cpp
Commit 6dc2a6a8c9a0e4f8b46a0ba05430b77229789b8e by dblaikie
Remove some unnecessary explicit defaulted copy ctors to cleanup -Wdeprecated-copy

These types also wanted to be/were copy assignable, and using the
implicit copy ctor is deprecated in the presence of an explicit copy
ctor.

Removing the explicit copy ctor provides the desired behavior - both
ctor and assignment operator are available implicitly.

Also while I was nearby there were some missing std::moves on shared
pointer parameters.
The file was modifiedlldb/source/Plugins/Language/CPlusPlus/LibCxxMap.cpp
The file was modifiedlldb/include/lldb/Symbol/UnwindPlan.h
The file was modifiedlldb/include/lldb/DataFormatters/DumpValueObjectOptions.h
The file was modifiedlldb/include/lldb/Utility/Timeout.h
The file was modifiedlldb/source/Plugins/Language/CPlusPlus/LibCxxList.cpp
Commit 174606877df46f3e8ce0c60a4c744687d3ee3271 by dblaikie
Clangd Matchers.h: Fix -Wdeprecated-copy by making the defaulted copy ctor and deleted copy assignment operators explicit
The file was modifiedclang-tools-extra/clangd/unittests/Matchers.h
Commit 8b9c15c2819bc4736e2c8315c6e0e71e8b7483bf by kparzysz
[Hexagon] Handle loads and stores of scalar predicate vectors

Handle v2i1, v4i1, and v8i1.
The file was modifiedllvm/lib/Target/Hexagon/HexagonISelLowering.cpp
The file was addedllvm/test/CodeGen/Hexagon/isel-memory-vNi1.ll