SuccessChanges

Summary

  1. [AArch64][GlobalISel] Make G_USUBO legal and select it. (details)
  2. [RISCV] Don't create LMUL=8 pseudo instructions for ternary widening arithmetic instructions (details)
  3. [RISCV] Correct DWARF number for vector registers. (details)
  4. [NewPM][opt] Run the "default" AA pipeline by default (details)
  5. [CodeGen] Use llvm::append_range (NFC) (details)
  6. [llvm] Don't include StringSwitch.h where unnecessary (NFC) (details)
  7. [llvm] Use isDigit (NFC) (details)
  8. [mlir] Enable passing crash reproducer stream factory method (details)
  9. Revert "[NewPM][opt] Run the "default" AA pipeline by default" (details)
  10. [AMDGPU][Inliner] Remove amdgpu-inline and add a new TTI inline hook (details)
  11. [NFC] Disallow unused prefixes under llvm/test (details)
  12. [ASTReader] Allow controlling separately whether validation should be disabled for a PCH vs a module file (details)
  13. [JITLink][ELF/x86-64] Range check 32-bit relocs. (details)
  14. [NewPM][opt] Run the "default" AA pipeline by default (details)
  15. [test] Make incorrect-exit-count.ll work under NPM (details)
  16. [mlir][Linalg] Introduce linalg.pad_tensor op. (details)
  17. [mlir][StandardToSPIRV] Add support for lowering uitofp to SPIR-V (details)
Commit 3dedad475da45c05bc4f66cd14e9f44581edf0bc by Amara Emerson
[AArch64][GlobalISel] Make G_USUBO legal and select it.

The expansion for wide subtractions includes G_USUBO.

Differential Revision: https://reviews.llvm.org/D95032
The file was modifiedllvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
The file was addedllvm/test/CodeGen/AArch64/GlobalISel/select-saddo.mir
The file was modifiedllvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/legalize-add.mir
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/legalize-sub.mir
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
The file was addedllvm/test/CodeGen/AArch64/GlobalISel/select-ssubo.mir
The file was addedllvm/test/CodeGen/AArch64/GlobalISel/select-usubo.mir
Commit f8f1b20e6b30624d2c0d18dc6a2d61643650d0c4 by craig.topper
[RISCV] Don't create LMUL=8 pseudo instructions for ternary widening arithmetic instructions

These instructions produce 2*SEW result so the input can't have
an LMUL=8 or the result would need a non-existant LMUL=16. So
only create pseudos for LMUL up to 4.

Differential Revision: https://reviews.llvm.org/D95189
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
Commit 5d354220d44f11c70f36d5a357ec2a2208a6ab92 by kai.wang
[RISCV] Correct DWARF number for vector registers.

The DWARF numbers of vector registers are already defined in
riscv-elf-psabi. The DWARF number for vector is start from 96.
Correct the DWARF numbers of vector registers.

Differential Revision: https://reviews.llvm.org/D94749
The file was modifiedllvm/lib/Target/RISCV/RISCVRegisterInfo.td
Commit be611431cd1f5c826a55b531db92a63e84323866 by aeubanks
[NewPM][opt] Run the "default" AA pipeline by default

We tend to assume that the AA pipeline is by default the default AA
pipeline and it's confusing when it's empty instead.

PR48779

Reviewed By: asbirlea

Differential Revision: https://reviews.llvm.org/D95117
The file was modifiedllvm/test/Other/new-pass-manager.ll
The file was modifiedllvm/test/Other/new-pm-thinlto-postlink-samplepgo-defaults.ll
The file was modifiedllvm/test/Transforms/LoopVectorize/optimal-epilog-vectorization.ll
The file was modifiedllvm/test/Transforms/Inline/cgscc-incremental-invalidate.ll
The file was modifiedllvm/test/Other/new-pm-pr42726-cgscc.ll
The file was modifiedllvm/test/Transforms/LoopRotate/pr35210.ll
The file was modifiedllvm/test/Analysis/MemorySSA/pr43569.ll
The file was modifiedllvm/test/Transforms/ThinLTOBitcodeWriter/pr33536.ll
The file was modifiedllvm/test/Other/new-pm-thinlto-defaults.ll
The file was modifiedllvm/test/Other/new-pm-thinlto-prelink-samplepgo-defaults.ll
The file was modifiedllvm/test/Transforms/PhaseOrdering/globalaa-retained.ll
The file was modifiedllvm/test/Transforms/Coroutines/coro-elide-musttail.ll
The file was modifiedllvm/test/Transforms/LoopVersioningLICM/loopversioningLICM2.ll
The file was modifiedllvm/test/Transforms/PhaseOrdering/ARM/arm_fill_q7.ll
The file was modifiedllvm/test/Other/pass-pipeline-parsing.ll
The file was modifiedllvm/test/Transforms/PhaseOrdering/X86/addsub-inseltpoison.ll
The file was modifiedllvm/test/Transforms/LoopVectorize/PowerPC/optimal-epilog-vectorization.ll
The file was modifiedllvm/test/Transforms/Coroutines/coro-retcon.ll
The file was modifiedllvm/test/Transforms/PhaseOrdering/X86/addsub.ll
The file was modifiedllvm/test/Transforms/PhaseOrdering/X86/vdiv.ll
The file was modifiedllvm/test/Transforms/SimplifyCFG/X86/invalidate-dom.ll
The file was modifiedllvm/test/Other/new-pm-thinlto-prelink-pgo-defaults.ll
The file was modifiedllvm/test/Transforms/LoopVersioningLICM/loopversioningLICM1.ll
The file was modifiedllvm/test/Other/new-pm-lto-defaults.ll
The file was modifiedllvm/test/Other/new-pm-defaults.ll
The file was modifiedllvm/test/Transforms/OpenMP/parallel_region_merging.ll
The file was modifiedllvm/test/Other/new-pm-thinlto-postlink-pgo-defaults.ll
The file was modifiedllvm/test/Transforms/PhaseOrdering/pr39282.ll
The file was modifiedllvm/test/CodeGen/Hexagon/loop-idiom/pmpy-mod.ll
The file was modifiedllvm/test/Transforms/ThinLTOBitcodeWriter/split-vfunc.ll
The file was modifiedllvm/tools/opt/NewPMDriver.cpp
The file was modifiedllvm/test/Transforms/PhaseOrdering/X86/SROA-after-loop-unrolling.ll
The file was modifiedllvm/test/Transforms/PhaseOrdering/X86/masked-memory-ops.ll
The file was modifiedllvm/test/Other/loop-pm-invalidation.ll
The file was modifiedllvm/test/Transforms/PhaseOrdering/X86/loop-idiom-vs-indvars.ll
The file was modifiedllvm/test/Transforms/PhaseOrdering/instcombine-sroa-inttoptr.ll
Commit c5c4dbd2790736008b1c60f1b737dfb824b90144 by kazu
[CodeGen] Use llvm::append_range (NFC)
The file was modifiedllvm/lib/CodeGen/MachineRegisterInfo.cpp
The file was modifiedllvm/lib/CodeGen/MachineCSE.cpp
The file was modifiedllvm/lib/CodeGen/Analysis.cpp
The file was modifiedllvm/lib/CodeGen/MIRCanonicalizerPass.cpp
The file was modifiedllvm/lib/CodeGen/MachineVerifier.cpp
The file was modifiedllvm/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp
The file was modifiedllvm/lib/CodeGen/SplitKit.cpp
The file was modifiedllvm/lib/CodeGen/CodeGenPrepare.cpp
Commit cfa241680fd6c5d804fa57406100692f923d679f by kazu
[llvm] Don't include StringSwitch.h where unnecessary (NFC)
The file was modifiedllvm/lib/Target/MSP430/AsmParser/MSP430AsmParser.cpp
The file was modifiedllvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
The file was modifiedllvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.cpp
The file was modifiedllvm/tools/dsymutil/dsymutil.cpp
The file was modifiedllvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
The file was modifiedllvm/lib/Target/AVR/AsmParser/AVRAsmParser.cpp
The file was modifiedllvm/lib/ObjectYAML/COFFEmitter.cpp
The file was modifiedllvm/tools/llvm-cvtres/llvm-cvtres.cpp
The file was modifiedllvm/lib/Support/X86TargetParser.cpp
The file was modifiedllvm/lib/Analysis/ObjCARCInstKind.cpp
The file was modifiedllvm/lib/MC/MCParser/COFFMasmParser.cpp
The file was modifiedllvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
The file was modifiedllvm/lib/IR/Core.cpp
Commit 551aaa24afe6d029cc96399bcece948a5217530b by kazu
[llvm] Use isDigit (NFC)
The file was modifiedllvm/lib/DebugInfo/Symbolize/Symbolize.cpp
The file was modifiedllvm/include/llvm/TableGen/Record.h
The file was modifiedllvm/lib/IR/AsmWriter.cpp
The file was modifiedllvm/lib/ProfileData/SampleProfReader.cpp
The file was modifiedllvm/lib/Support/Triple.cpp
The file was modifiedllvm/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp
The file was modifiedllvm/lib/CodeGen/TargetLoweringBase.cpp
Commit aee622fa200de9ad28334cf74416f2fd5391e2ee by jpienaar
[mlir] Enable passing crash reproducer stream factory method

Add factory to create streams for logging the reproducer. Allows for more general logging (beyond file) and logging the configuration/module separately (logged in order, configuration before module).

Also enable querying filename of ToolOutputFile.

Differential Revision: https://reviews.llvm.org/D94868
The file was modifiedmlir/include/mlir/Pass/PassManager.h
The file was modifiedmlir/lib/Pass/Pass.cpp
The file was modifiedllvm/include/llvm/Support/ToolOutputFile.h
The file was modifiedmlir/docs/PassManagement.md
Commit ba9b4ea4eeaef039e80df10695a11e6ed35d415a by aeubanks
Revert "[NewPM][opt] Run the "default" AA pipeline by default"

This reverts commit be611431cd1f5c826a55b531db92a63e84323866.

Other/new-pm-lto-defaults.ll failing
The file was modifiedllvm/test/Other/new-pm-thinlto-prelink-pgo-defaults.ll
The file was modifiedllvm/test/Other/new-pass-manager.ll
The file was modifiedllvm/test/Transforms/PhaseOrdering/instcombine-sroa-inttoptr.ll
The file was modifiedllvm/test/Transforms/LoopVersioningLICM/loopversioningLICM1.ll
The file was modifiedllvm/test/Other/new-pm-lto-defaults.ll
The file was modifiedllvm/test/Transforms/ThinLTOBitcodeWriter/split-vfunc.ll
The file was modifiedllvm/test/Transforms/SimplifyCFG/X86/invalidate-dom.ll
The file was modifiedllvm/test/Transforms/OpenMP/parallel_region_merging.ll
The file was modifiedllvm/test/Transforms/PhaseOrdering/pr39282.ll
The file was modifiedllvm/test/Other/new-pm-thinlto-defaults.ll
The file was modifiedllvm/test/Transforms/LoopVectorize/optimal-epilog-vectorization.ll
The file was modifiedllvm/test/Transforms/PhaseOrdering/X86/SROA-after-loop-unrolling.ll
The file was modifiedllvm/test/Analysis/MemorySSA/pr43569.ll
The file was modifiedllvm/test/Transforms/Coroutines/coro-retcon.ll
The file was modifiedllvm/test/Other/loop-pm-invalidation.ll
The file was modifiedllvm/test/Transforms/PhaseOrdering/X86/loop-idiom-vs-indvars.ll
The file was modifiedllvm/test/Other/new-pm-thinlto-postlink-samplepgo-defaults.ll
The file was modifiedllvm/test/Transforms/PhaseOrdering/X86/addsub-inseltpoison.ll
The file was modifiedllvm/test/Transforms/PhaseOrdering/X86/masked-memory-ops.ll
The file was modifiedllvm/test/Transforms/Inline/cgscc-incremental-invalidate.ll
The file was modifiedllvm/test/Transforms/LoopRotate/pr35210.ll
The file was modifiedllvm/test/Transforms/PhaseOrdering/globalaa-retained.ll
The file was modifiedllvm/test/Other/new-pm-pr42726-cgscc.ll
The file was modifiedllvm/test/Other/new-pm-thinlto-prelink-samplepgo-defaults.ll
The file was modifiedllvm/test/Transforms/ThinLTOBitcodeWriter/pr33536.ll
The file was modifiedllvm/test/Transforms/Coroutines/coro-elide-musttail.ll
The file was modifiedllvm/test/Transforms/PhaseOrdering/X86/vdiv.ll
The file was modifiedllvm/test/CodeGen/Hexagon/loop-idiom/pmpy-mod.ll
The file was modifiedllvm/test/Transforms/LoopVectorize/PowerPC/optimal-epilog-vectorization.ll
The file was modifiedllvm/test/Transforms/PhaseOrdering/X86/addsub.ll
The file was modifiedllvm/test/Transforms/LoopVersioningLICM/loopversioningLICM2.ll
The file was modifiedllvm/test/Other/new-pm-defaults.ll
The file was modifiedllvm/test/Transforms/PhaseOrdering/ARM/arm_fill_q7.ll
The file was modifiedllvm/test/Other/new-pm-thinlto-postlink-pgo-defaults.ll
The file was modifiedllvm/test/Other/pass-pipeline-parsing.ll
The file was modifiedllvm/tools/opt/NewPMDriver.cpp
Commit a11bf9a7fbd3693d6d4bca8ef2ba1d2f0758f9be by aeubanks
[AMDGPU][Inliner] Remove amdgpu-inline and add a new TTI inline hook

Having a custom inliner doesn't really fit in with the new PM's
pipeline. It's also extra technical debt.

amdgpu-inline only does a couple of custom things compared to the normal
inliner:
1) It disables inlining if the number of BBs in a function would exceed
   some limit
2) It increases the threshold if there are pointers to private arrays(?)

These can all be handled as TTI inliner hooks.
There already exists a hook for backends to multiply the inlining
threshold.

This way we can remove the custom amdgpu-inline pass.

This caused inline-hint.ll to fail, and after some investigation, it
looks like getInliningThresholdMultiplier() was previously getting
applied twice in amdgpu-inline (https://reviews.llvm.org/D62707 fixed it
not applying at all, so some later inliner change must have fixed
something), so I had to change the threshold in the test.

Reviewed By: rampitec

Differential Revision: https://reviews.llvm.org/D94153
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h
The file was modifiedllvm/utils/gn/secondary/llvm/lib/Target/AMDGPU/BUILD.gn
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPU.h
The file was modifiedllvm/test/Transforms/Inline/AMDGPU/inline-hint.ll
The file was modifiedllvm/lib/Analysis/InlineCost.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/amdgpu-inline.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/opt-pipeline.ll
The file was modifiedllvm/test/Transforms/Inline/AMDGPU/amdgpu-inline-alloca-argument.ll
The file was modifiedllvm/test/Transforms/Inline/AMDGPU/inline-amdgpu-vecbonus.ll
The file was modifiedllvm/include/llvm/CodeGen/BasicTTIImpl.h
The file was modifiedllvm/lib/Analysis/TargetTransformInfo.cpp
The file was modifiedllvm/include/llvm/Analysis/TargetTransformInfoImpl.h
The file was modifiedllvm/include/llvm/Analysis/TargetTransformInfo.h
The file was removedllvm/lib/Target/AMDGPU/AMDGPUInline.cpp
The file was modifiedllvm/lib/Target/AMDGPU/CMakeLists.txt
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/inline-maxbb.ll
Commit c042aff8860df3cad2b274bf0a495e83ae36ddee by mtrofin
[NFC] Disallow unused prefixes under llvm/test

This patch sets the default for llvm tests, with the exception of tests
under Reduce, because quite a few of them use 'FileCheck' as parameter
to a tool, and including a flag as that parameter would complicate
matters.

The rest of the patch undo-es the lit.local.cfg changes we progressively
introduced as temporary measure to avoid regressions under various
directories.

Differential Revision: https://reviews.llvm.org/D95111
The file was modifiedllvm/test/Instrumentation/HWAddressSanitizer/basic.ll
The file was modifiedllvm/test/lit.cfg.py
The file was modifiedllvm/test/MC/RISCV/lit.local.cfg
The file was removedllvm/test/CodeGen/lit.local.cfg
The file was modifiedllvm/test/Instrumentation/MemorySanitizer/reduce.ll
The file was modifiedllvm/test/Instrumentation/MemorySanitizer/check-array.ll
The file was modifiedllvm/test/FileCheck/lit.local.cfg
The file was modifiedllvm/test/Instrumentation/HWAddressSanitizer/prologue.ll
The file was modifiedllvm/test/MC/AArch64/lit.local.cfg
The file was removedllvm/test/Other/lit.local.cfg
The file was modifiedllvm/test/Instrumentation/MemorySanitizer/freeze.ll
The file was modifiedllvm/test/Instrumentation/MemorySanitizer/msan_x86_bts_asm.ll
The file was modifiedllvm/test/Instrumentation/MemorySanitizer/check-struct.ll
The file was modifiedllvm/test/Instrumentation/MemorySanitizer/msan_eager.ll
The file was removedllvm/test/Analysis/lit.local.cfg
The file was removedllvm/test/Transforms/lit.local.cfg
The file was modifiedllvm/test/Instrumentation/AddressSanitizer/global_metadata_array.ll
The file was modifiedllvm/test/MC/AMDGPU/lit.local.cfg
The file was modifiedllvm/test/Instrumentation/MemorySanitizer/array_types.ll
The file was modifiedllvm/test/MC/ARM/lit.local.cfg
The file was addedllvm/test/Reduce/lit.local.cfg
The file was modifiedllvm/test/Instrumentation/MemorySanitizer/msan_asm_conservative.ll
Commit b0e89906f5b7e505a1ea315ab4ff612b1607fda8 by kyrtzidis
[ASTReader] Allow controlling separately whether validation should be disabled for a PCH vs a module file

This addresses an issue with how the PCH preable works, specifically:

1. When using a PCH/preamble the module hash changes and a different cache directory is used
2. When the preamble is used, PCH & PCM validation is disabled.

Due to combination of #1 and #2, reparsing with preamble enabled can end up loading a stale module file before a header change and using it without updating it because validation is disabled and it doesn’t check that the header has changed and the module file is out-of-date.

rdar://72611253

Differential Revision: https://reviews.llvm.org/D95159
The file was addedclang/test/Index/preamble-reparse-changed-module.m
The file was modifiedclang/lib/Serialization/ASTReader.cpp
The file was addedclang/test/Index/Inputs/preamble-reparse-changed-module/head.h
The file was modifiedclang/lib/Frontend/ChainedIncludesSource.cpp
The file was modifiedclang/lib/Frontend/FrontendActions.cpp
The file was modifiedclang/include/clang/Serialization/ASTReader.h
The file was modifiedclang/tools/c-index-test/core_main.cpp
The file was modifiedclang/lib/Frontend/FrontendAction.cpp
The file was modifiedclang/lib/Frontend/PrecompiledPreamble.cpp
The file was modifiedclang/lib/Frontend/ASTUnit.cpp
The file was modifiedclang/include/clang/Lex/PreprocessorOptions.h
The file was modifiedclang/lib/Frontend/CompilerInstance.cpp
The file was modifiedclang/include/clang/Frontend/CompilerInstance.h
The file was addedclang/test/Index/Inputs/preamble-reparse-changed-module/new-head.h
The file was modifiedclang/include/clang/Driver/Options.td
The file was addedclang/test/Index/Inputs/preamble-reparse-changed-module/module.modulemap
The file was modifiedclang/tools/c-index-test/c-index-test.c
Commit f9b5f6937ebed5dccabfc3c287f11d18b68a36f6 by Lang Hames
[JITLink][ELF/x86-64] Range check 32-bit relocs.

Also switch to using little_<b> / ulittle_<b> types to write results for
consistency with MachO.
The file was modifiedllvm/lib/ExecutionEngine/JITLink/ELF_x86_64.cpp
Commit 6699029b67bf0f5389896f9f929a344b64cfd9c7 by aeubanks
[NewPM][opt] Run the "default" AA pipeline by default

We tend to assume that the AA pipeline is by default the default AA
pipeline and it's confusing when it's empty instead.

PR48779

Initially reverted due to BasicAA running analyses in an unspecified
order (multiple function calls as parameters), fixed by fetching
analyses before the call to construct BasicAA.

Reviewed By: asbirlea

Differential Revision: https://reviews.llvm.org/D95117
The file was modifiedllvm/test/Transforms/LoopVectorize/optimal-epilog-vectorization.ll
The file was modifiedllvm/test/Transforms/PhaseOrdering/X86/vdiv.ll
The file was modifiedllvm/test/Other/new-pm-thinlto-prelink-samplepgo-defaults.ll
The file was modifiedllvm/test/Transforms/LoopVersioningLICM/loopversioningLICM1.ll
The file was modifiedllvm/test/Analysis/MemorySSA/pr43569.ll
The file was modifiedllvm/test/Transforms/PhaseOrdering/pr39282.ll
The file was modifiedllvm/test/Other/new-pm-thinlto-prelink-pgo-defaults.ll
The file was modifiedllvm/test/Transforms/PhaseOrdering/X86/addsub-inseltpoison.ll
The file was modifiedllvm/test/Transforms/PhaseOrdering/X86/loop-idiom-vs-indvars.ll
The file was modifiedllvm/test/Transforms/OpenMP/parallel_region_merging.ll
The file was modifiedllvm/test/Transforms/PhaseOrdering/ARM/arm_fill_q7.ll
The file was modifiedllvm/test/Other/new-pm-thinlto-postlink-samplepgo-defaults.ll
The file was modifiedllvm/test/Transforms/Inline/cgscc-incremental-invalidate.ll
The file was modifiedllvm/test/Other/new-pm-pr42726-cgscc.ll
The file was modifiedllvm/test/Other/pass-pipeline-parsing.ll
The file was modifiedllvm/tools/opt/NewPMDriver.cpp
The file was modifiedllvm/test/Transforms/PhaseOrdering/X86/addsub.ll
The file was modifiedllvm/test/Transforms/ThinLTOBitcodeWriter/split-vfunc.ll
The file was modifiedllvm/test/Transforms/PhaseOrdering/X86/masked-memory-ops.ll
The file was modifiedllvm/test/Transforms/PhaseOrdering/instcombine-sroa-inttoptr.ll
The file was modifiedllvm/test/Transforms/Coroutines/coro-retcon.ll
The file was modifiedllvm/test/Transforms/LoopVectorize/PowerPC/optimal-epilog-vectorization.ll
The file was modifiedllvm/lib/Analysis/BasicAliasAnalysis.cpp
The file was modifiedllvm/test/Other/new-pass-manager.ll
The file was modifiedllvm/test/Transforms/LoopVersioningLICM/loopversioningLICM2.ll
The file was modifiedllvm/test/Transforms/PhaseOrdering/X86/SROA-after-loop-unrolling.ll
The file was modifiedllvm/test/Transforms/ThinLTOBitcodeWriter/pr33536.ll
The file was modifiedllvm/test/Transforms/Coroutines/coro-elide-musttail.ll
The file was modifiedllvm/test/Transforms/SimplifyCFG/X86/invalidate-dom.ll
The file was modifiedllvm/test/Other/loop-pm-invalidation.ll
The file was modifiedllvm/test/Transforms/LoopRotate/pr35210.ll
The file was modifiedllvm/test/CodeGen/Hexagon/loop-idiom/pmpy-mod.ll
The file was modifiedllvm/test/Other/new-pm-defaults.ll
The file was modifiedllvm/test/Transforms/PhaseOrdering/globalaa-retained.ll
The file was modifiedllvm/test/Other/new-pm-lto-defaults.ll
The file was modifiedllvm/test/Other/new-pm-thinlto-defaults.ll
The file was modifiedllvm/test/Other/new-pm-thinlto-postlink-pgo-defaults.ll
Commit f374138058b6f7ddfeeb145a5c98b9c8d0d95f82 by aeubanks
[test] Make incorrect-exit-count.ll work under NPM
The file was modifiedllvm/test/Analysis/ScalarEvolution/incorrect-exit-count.ll
Commit 16d4bbef30a9e625e04653047759d5636f9e58a5 by hanchung
[mlir][Linalg] Introduce linalg.pad_tensor op.

`linalg.pad_tensor` is an operation that pads the `source` tensor
with given `low` and `high` padding config.

Example 1:

```mlir
  %pad_value = ... : f32
  %1 = linalg.pad_tensor %0 low[1, 2] high[2, 3] {
  ^bb0(%arg0 : index, %arg1 : index):
    linalg.yield %pad_value : f32
  } : tensor<?x?xf32> to tensor<?x?xf32>
```

Example 2:
```mlir
  %pad_value = ... : f32
  %1 = linalg.pad_tensor %arg0 low[2, %arg1, 3, 3] high[3, 3, %arg1, 2] {
  ^bb0(%arg2: index, %arg3: index, %arg4: index, %arg5: index):
    linalg.yield %pad_value : f32
  } : tensor<1x2x2x?xf32> to tensor<6x?x?x?xf32>
```

Reviewed By: nicolasvasilache

Differential Revision: https://reviews.llvm.org/D93704
The file was modifiedmlir/lib/Dialect/Linalg/IR/LinalgOps.cpp
The file was modifiedmlir/test/Dialect/Linalg/roundtrip.mlir
The file was modifiedmlir/include/mlir/Dialect/Linalg/IR/LinalgOps.td
The file was modifiedmlir/test/Dialect/Linalg/invalid.mlir
Commit 2cb130f7661176f2c2eaa7554f2a55863cfc0ed3 by hanchung
[mlir][StandardToSPIRV] Add support for lowering uitofp to SPIR-V

- Extend spirv::ConstantOp::getZero/One to handle float, vector of int, and vector of float.
- Refactor ZeroExtendI1Pattern to use getZero/One methods.
- Add one more test for lowering std.zexti which extends vector<4xi1> to vector<4xi64>.

Reviewed By: antiagainst

Differential Revision: https://reviews.llvm.org/D95120
The file was modifiedmlir/test/Conversion/StandardToSPIRV/std-ops-to-spirv.mlir
The file was modifiedmlir/lib/Conversion/StandardToSPIRV/StandardToSPIRV.cpp
The file was modifiedmlir/lib/Dialect/SPIRV/IR/SPIRVOps.cpp