Commit
b477b927749707982414d06674c7d2af276e046c
by craig.topper[RISCV] Fix typo in comment. NFC
|
 | clang/utils/TableGen/RISCVVEmitter.cpp |
Commit
0567f0333176e476e15b7f32b463f58f7475ff22
by Anshil.Gandhi[HIP] [AlwaysInliner] Disable AlwaysInliner to eliminate undefined symbols
By default clang emits complete contructors as alias of base constructors if they are the same.
The backend is supposed to emit symbols for the alias, otherwise it causes undefined symbols.
@yaxunl observed that this issue is related to the llvm options `-amdgpu-early-inline-all=true`
and `-amdgpu-function-calls=false`. This issue is resolved by only inlining global values
with internal linkage. The `getCalleeFunction()` in AMDGPUResourceUsageAnalysis also had
to be extended to support aliases to functions. inline-calls.ll was corrected appropriately.
Reviewed By: yaxunl, #amdgpu
Differential Revision: https://reviews.llvm.org/D109707
|
| clang/lib/Driver/ToolChains/Clang.cpp |
| llvm/lib/Target/AMDGPU/AMDGPUResourceUsageAnalysis.cpp |
| llvm/lib/Target/AMDGPU/AMDGPUAlwaysInlinePass.cpp |
 | clang/test/CodeGenCUDA/amdgpu-alias-undef-symbols.cu |
| llvm/test/CodeGen/AMDGPU/inline-calls.ll |
Commit
684b6265b31cabf422b01cd8937a3641c6df914f
by craig.topper[RISCV][TableGen] Remove HasMaskedOffOperand as a member of RVVIntrinsic. NFC
This value is only used by the RVVIntrinsic constructor. We don't
need it to be a member.
|
| clang/utils/TableGen/RISCVVEmitter.cpp |
Commit
87c016078ad72c46505461e4ff8bfa04819fe7ba
by michaelrj[libc] add atof, strtof and strtod
Add the string to floating point conversion functions.
Long doubles aren't supported yet, but floats and doubles are. The
primary algorithm used is the Eisel-Lemire ParseNumberF64 algorithm,
with the Simple Decimal Conversion algorithm as backup.
Links for more information on the algorithms:
Number Parsing at a Gigabyte per Second, Software: Practice and
Experience 51 (8), 2021 (https://arxiv.org/abs/2101.11408)
https://nigeltao.github.io/blog/2020/eisel-lemire.html
https://nigeltao.github.io/blog/2020/parse-number-f64-simple.html
Differential Revision: https://reviews.llvm.org/D109261
|
| libc/src/__support/CMakeLists.txt |
| libc/src/stdlib/atof.h |
| libc/src/stdlib/strtof.cpp |
| libc/src/__support/str_to_float.h |
| libc/test/src/__support/CMakeLists.txt |
| libc/test/src/stdlib/atof_test.cpp |
| libc/config/linux/x86_64/entrypoints.txt |
| libc/test/src/__support/str_to_float_test.cpp |
| libc/test/src/stdlib/CMakeLists.txt |
| libc/src/stdlib/strtof.h |
| libc/fuzzing/stdlib/StringParserOutputDiff.h |
| libc/src/stdlib/strtod.h |
| libc/fuzzing/stdlib/CMakeLists.txt |
| libc/test/src/__support/str_to_float_comparison_data.txt |
| libc/test/src/stdlib/strtof_test.cpp |
| libc/test/src/stdlib/strtod_test.cpp |
| libc/src/__support/high_precision_decimal.h |
| libc/test/src/__support/str_to_float_comparison_test.cpp |
| libc/spec/stdc.td |
| libc/src/stdlib/CMakeLists.txt |
| libc/fuzzing/stdlib/atof_fuzz.cpp |
| libc/src/stdlib/strtod.cpp |
| libc/src/stdlib/atof.cpp |
| libc/src/__support/detailed_powers_of_ten.h |
Commit
4ada6c2aafffd90c87900cab0adbb4d43c874b9b
by rob.suderman[mlir][tosa] Adds a canonicalization to the transpose op if the perms are a no op
Reviewed By: rsuderman
Differential Revision: https://reviews.llvm.org/D112037
|
| mlir/test/Dialect/Tosa/canonicalize.mlir |
| mlir/lib/Dialect/Tosa/IR/TosaOps.cpp |
Commit
cb5a10199b32b5e1104ed36a490be73fa3bdf5ca
by aeubanks[test] Remove tests pinned to the legacy PM
Now that the legacy PM is deprecated for the optimization pipeline, we
can start deleting legacy PM tests.
For tests that test both PMs, merge the RUN lines.
Delete tests specific to the legacy PM.
|
| clang/test/Profile/gcc-flag-compatibility.c |
| clang/test/CodeGen/aggregate-assign-call.c |
| clang/test/CodeGenCXX/conditional-temporaries.cpp |
| clang/test/CodeGenCXX/merge-functions.cpp |
| clang/test/Driver/memtag.c |
| clang/test/CodeGenCXX/nrvo.cpp |
| clang/test/Driver/dfsan.c |
| clang/test/Driver/sancov.c |
| clang/test/Driver/memtag_lto.c |
| clang/test/CodeGen/X86/avx512fp16-complex.c |
| clang/test/CodeGen/split-debug-single-file.c |
| clang/test/CodeGenCXX/member-function-pointer-calls.cpp |
| clang/test/CodeGenCXX/ubsan-coroutines.cpp |
| clang/test/Driver/asan.c |
| clang/test/CodeGen/callback_annotated.c |
| clang/test/CodeGen/complex-math.c |
| clang/test/CodeGen/cspgo-instrumentation_lto.c |
| clang/test/CodeGen/lifetime.c |
| clang/test/CodeGenOpenCL/convergent.cl |
| clang/test/CodeGen/split-lto-unit.c |
| clang/test/CodeGen/pgo-sample.c |
| clang/test/CodeGen/attr-arm-sve-vector-bits-call.c |
| clang/test/CodeGen/pgo-instrumentation.c |
| clang/test/CodeGen/use-sample-profile-attr.c |
 | clang/test/Misc/pr32207.c |
| clang/test/CodeGen/available-externally-suppress.c |
| clang/test/Driver/tsan.c |
| clang/test/CodeGen/X86/builtin-movdir.c |
| clang/test/Profile/gcc-flag-compatibility-aix.c |
| clang/test/Driver/msan.c |
| clang/test/CodeGen/X86/x86_64-instrument-functions.c |
| clang/test/CodeGen/cspgo-instrumentation.c |
| clang/test/CodeGen/thinlto-debug-pm.c |
| clang/test/Frontend/optimization-remark-line-directive.c |
Commit
15fefcb9eb3a2b9080b44e3784608597666000ec
by aeubanks[opt] Directly translate -O# to -passes='default<O#>'
Right now when we see -O# we add the corresponding 'default<O#>' into
the list of passes to run when translating legacy -pass-name. This has
the side effect of not using the default AA pipeline.
Instead, treat -O# as -passes='default<O#>', but don't allow any other
-passes or -pass-name. I think we can keep `opt -O#` as shorthand for
`opt -passes='default<O#>` but disallow anything more than just -O#.
Tests need to be updated to not use `opt -O# -pass-name`.
Reviewed By: asbirlea
Differential Revision: https://reviews.llvm.org/D112036
|
| llvm/test/Transforms/LoopVectorize/PowerPC/widened-massv-call.ll |
| llvm/test/Transforms/LoopVectorize/PowerPC/reg-usage.ll |
| llvm/test/Transforms/LoopVectorize/X86/metadata-enable.ll |
| llvm/test/CodeGen/AMDGPU/extra-sroa-after-unroll.ll |
| llvm/test/Transforms/Inline/devirtualize-3.ll |
| llvm/test/Transforms/LoopVectorize/X86/x86_fp80-vector-store.ll |
| llvm/test/Other/opt-On.ll |
| llvm/test/Transforms/LoopVersioningLICM/metadata.ll |
| llvm/test/Transforms/LoopVectorize/X86/float-induction-x86.ll |
| llvm/test/CodeGen/NVPTX/nvvm-reflect-arch.ll |
| llvm/test/Instrumentation/MemorySanitizer/msan_llvm_strip_invariant.ll |
| llvm/tools/opt/opt.cpp |
| llvm/test/Transforms/MergeFunc/mergefunc-preserve-debug-info.ll |
| llvm/test/CodeGen/NVPTX/nvvm-reflect.ll |
| llvm/test/CodeGen/AMDGPU/r600.amdgpu-alias-analysis.ll |
| llvm/test/Transforms/LoopVectorize/global_alias.ll |
| llvm/test/Instrumentation/MemorySanitizer/msan_llvm_launder_invariant.ll |
| llvm/test/Transforms/LoopVersioningLICM/loopversioningLICM3.ll |
| llvm/test/Transforms/GlobalOpt/long-compilation-global-sra.ll |
Commit
f24532ae91d540bcc2a6a5f29f89c8ea42907ef3
by jinghamFollow-on to fix a test from c5011aed9c297d6ddd8ee4f77453b215aa27554a.
I need to set a fake default platform for the UnitTest test to run on other
systems.
|
| lldb/unittests/Interpreter/TestCommandPaths.cpp |
Commit
252386ac81f944ab713dfd5158e67cd547fba53c
by springerm[mlir] Add enclosingOpOk parameter to properlyDominates
Differential Revision: https://reviews.llvm.org/D111959
|
| mlir/include/mlir/IR/Dominance.h |
Commit
fd26ca4e7515e7dd32ae02e777bd21693afc68ff
by springerm[mlir][scf] Add insideMutuallyExclusiveBranches helper
This helper function checks if two given ops are in mutually exclusive branches of the same scf::IfOp.
Differential Revision: https://reviews.llvm.org/D111957
|
| mlir/include/mlir/Dialect/SCF/SCF.h |
| mlir/lib/Dialect/SCF/SCF.cpp |
Commit
bc03a9c066bf9990a1d595cb80ad51ae40fb759a
by Lang HamesSimplify the TableManager class and move it into a public header.
Moves visitEdge into the TableManager derivatives, replacing the fixEdgeKind
methods in those classes. The visitEdge method takes on responsibility for
updating the edge target, as well as its kind.
|
| llvm/include/llvm/ExecutionEngine/JITLink/TableManager.h |
| llvm/lib/ExecutionEngine/JITLink/ELF_x86_64.cpp |
| llvm/lib/ExecutionEngine/JITLink/TableManager.h |
Commit
21bb463e9639719f1aae9535825a40732eda487b
by jeffniu22[mlir] fix bugs with NamedAttrList
- `assign` with ArrayRef was calling `append`
- `assign` with empty ArrayRef was not clearing storage
Reviewed By: jpienaar
Differential Revision: https://reviews.llvm.org/D112043
|
| mlir/unittests/IR/OperationSupportTest.cpp |
| mlir/include/mlir/IR/OperationSupport.h |
| mlir/lib/IR/BuiltinAttributes.cpp |
Commit
facff468b6c47b954aebd297c90bd44accaa54c6
by kai.wang[RISCV] Reorder the vector register allocation order.
GPR uses argument registers as the first group of registers to allocate.
This patch uses vector argument registers, v8 to v23, as the first group
to allocate.
Differential Revision: https://reviews.llvm.org/D111304
|
| llvm/test/CodeGen/RISCV/rvv/vtruncs-sdnode-rv32.ll |
| llvm/test/CodeGen/RISCV/rvv/vnsrl-rv64.ll |
| llvm/test/CodeGen/RISCV/rvv/vssubu-sdnode.ll |
| llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-logic.ll |
| llvm/test/CodeGen/RISCV/rvv/vmv.x.s-rv32.ll |
| llvm/test/CodeGen/RISCV/rvv/vreductions-int-vp.ll |
| llvm/test/CodeGen/RISCV/rvv/vadd-vp.ll |
| llvm/test/CodeGen/RISCV/rvv/vmaxu-rv32.ll |
| llvm/test/CodeGen/RISCV/byval.ll |
| llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-xu-rv32.ll |
| llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-x-f-rv32.ll |
| llvm/test/CodeGen/RISCV/rvv/setcc-integer-rv32.ll |
| llvm/test/CodeGen/RISCV/rvv/vmsbc-rv32.ll |
| llvm/test/CodeGen/RISCV/rvv/vwmul-rv64.ll |
| llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmul-vp.ll |
| llvm/test/CodeGen/RISCV/rvv/vwmul-rv32.ll |
| llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-xu-f-rv64.ll |
| llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsub-vp.ll |
| llvm/test/CodeGen/RISCV/rvv/vcompress-rv32.ll |
| llvm/test/CodeGen/RISCV/rvv/vwmulsu-rv64.ll |
| llvm/test/CodeGen/RISCV/rvv/vaaddu-rv32.ll |
| llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll |
| llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsrl-vp.ll |
| llvm/test/CodeGen/RISCV/rvv/vleff-rv32.ll |
| llvm/test/CodeGen/RISCV/rvv/vfwsub-rv32.ll |
| llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll |
| llvm/test/CodeGen/RISCV/rvv/vreductions-int-rv32.ll |
| llvm/test/CodeGen/RISCV/rvv/vwaddu-rv64.ll |
| llvm/test/CodeGen/RISCV/rvv/vfncvt-rod-f-f-rv64.ll |
| llvm/test/CodeGen/RISCV/rvv/rv32-spill-vector-csr.ll |
| llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vshl-vp.ll |
| llvm/test/CodeGen/RISCV/rvv/load-add-store-8.ll |
| llvm/test/CodeGen/RISCV/rvv/vshl-vp.ll |
| llvm/test/CodeGen/RISCV/rvv/vsub-vp.ll |
| llvm/test/CodeGen/RISCV/rvv/vpopc-rv32.ll |
| llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll |
| llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-splat.ll |
| llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-x-rv64.ll |
| llvm/test/CodeGen/RISCV/rvv/vsmul-rv32.ll |
| llvm/test/CodeGen/RISCV/rvv/vor-rv32.ll |
| llvm/test/CodeGen/RISCV/calls.ll |
| llvm/test/CodeGen/RISCV/rvv/named-vector-shuffle-reverse.ll |
| llvm/test/CodeGen/RISCV/rvv/vfdiv-vp.ll |
| llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-f-rv64.ll |
| llvm/test/CodeGen/RISCV/rvv/vfwsub-rv64.ll |
| llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrem-vp.ll |
| llvm/test/CodeGen/RISCV/rvv/vpopc-rv64.ll |
| llvm/test/CodeGen/RISCV/rvv/vluxei-rv32.ll |
| llvm/test/CodeGen/RISCV/rvv/vxor-rv32.ll |
| llvm/test/CodeGen/RISCV/rvv/vfncvt-xu-f-rv32.ll |
| llvm/test/CodeGen/RISCV/double-calling-conv.ll |
| llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap.ll |
| llvm/test/CodeGen/RISCV/rvv/vfwadd-rv64.ll |
| llvm/test/CodeGen/RISCV/rvv/vsbc-rv32.ll |
| llvm/test/CodeGen/RISCV/rvv/vfncvt-f-f-rv32.ll |
| llvm/test/CodeGen/RISCV/rvv/stepvector.ll |
| llvm/test/CodeGen/RISCV/rvv/vmsbc.borrow.in-rv32.ll |
| llvm/test/CodeGen/RISCV/rvv/vmsge-rv64.ll |
| llvm/test/CodeGen/RISCV/rvv/setcc-fp-rv64.ll |
| llvm/test/CodeGen/RISCV/rvv/vselect-fp-rv64.ll |
| llvm/test/CodeGen/RISCV/rvv/vwsub-rv32.ll |
| llvm/test/CodeGen/RISCV/rvv/vmfgt-rv64.ll |
| llvm/test/CodeGen/RISCV/rvv/vfncvt-f-xu-rv32.ll |
| llvm/test/CodeGen/RISCV/rvv/vmsbf-rv64.ll |
| llvm/test/CodeGen/RISCV/rvv/load-add-store-64.ll |
| llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssubu.ll |
| llvm/test/CodeGen/RISCV/rvv/vfncvt-f-x-rv32.ll |
| llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-load-store.ll |
| llvm/test/CodeGen/RISCV/rvv/vfncvt-f-x-rv64.ll |
| llvm/test/CodeGen/RISCV/rvv/vreductions-mask.ll |
| llvm/test/CodeGen/RISCV/rvv/vfwadd.w-rv64.ll |
| llvm/test/CodeGen/RISCV/rvv/vmsgeu-rv32.ll |
| llvm/test/CodeGen/RISCV/rvv/vmsgt-rv32.ll |
| llvm/test/CodeGen/RISCV/rvv/vand-vp.ll |
| llvm/test/CodeGen/RISCV/rvv/vrem-sdnode-rv32.ll |
| llvm/test/CodeGen/RISCV/rvv/vwsubu-rv64.ll |
| llvm/test/CodeGen/RISCV/rvv/vnsra-rv32.ll |
| llvm/test/CodeGen/RISCV/rvv/vfmul-vp.ll |
| llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll |
| llvm/test/CodeGen/RISCV/rvv/zvlsseg-zero-vl.ll |
| llvm/test/CodeGen/RISCV/rvv/vwaddu.w-rv64.ll |
| llvm/test/CodeGen/RISCV/rvv/vrsub-sdnode-rv32.ll |
| llvm/test/CodeGen/RISCV/rvv/urem-seteq-vec.ll |
| llvm/test/CodeGen/RISCV/rvv/vmsif-rv32.ll |
| llvm/test/CodeGen/RISCV/rvv/vmadc.carry.in-rv64.ll |
| llvm/test/CodeGen/RISCV/rvv/access-fixed-objects-by-rvv.ll |
| llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-splat.ll |
| llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-xu-f-rv32.ll |
| llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsra-vp.ll |
| llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmacc.ll |
| llvm/test/CodeGen/RISCV/rvv/vfncvt-x-f-rv32.ll |
| llvm/test/CodeGen/RISCV/rvv/vmsbf-rv32.ll |
| llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmul-vp.ll |
| llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode-rv64.ll |
| llvm/test/CodeGen/RISCV/rvv/vmfle-rv32.ll |
| llvm/test/CodeGen/RISCV/rvv/vmv.s.x-rv32.ll |
| llvm/test/CodeGen/RISCV/rvv/vmulh-rv32.ll |
| llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll |
| llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-bitcast.ll |
| llvm/test/CodeGen/RISCV/rvv/vsaddu-sdnode.ll |
| llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz.ll |
| llvm/test/CodeGen/RISCV/rvv/constant-folding.ll |
| llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vdiv-vp.ll |
| llvm/test/CodeGen/RISCV/rvv/vpgather-sdnode.ll |
| llvm/test/CodeGen/RISCV/rvv/vrgatherei16-rv32.ll |
| llvm/test/CodeGen/RISCV/rvv/vmul-rv32.ll |
| llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-mask-vp.ll |
| llvm/test/CodeGen/RISCV/rvv/vmadd-sdnode.ll |
| llvm/test/CodeGen/RISCV/rvv/vssub-sdnode.ll |
| llvm/test/CodeGen/RISCV/rvv/vwsubu.w-rv32.ll |
| llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-conv.ll |
| llvm/test/CodeGen/RISCV/rvv/interleave-crash.ll |
| llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll |
| llvm/test/CodeGen/RISCV/rvv/vor-vp.ll |
| llvm/test/CodeGen/RISCV/rvv/vsrl-vp.ll |
| llvm/test/CodeGen/RISCV/rvv/vmslt-rv64.ll |
| llvm/test/CodeGen/RISCV/rvv/vfwcvt-x-f-rv32.ll |
| llvm/test/CodeGen/RISCV/rvv/vmsne-rv64.ll |
| llvm/test/CodeGen/RISCV/rvv/vcompress-rv64.ll |
| llvm/test/CodeGen/RISCV/rvv/vreductions-fp-vp.ll |
| llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssub.ll |
| llvm/test/CodeGen/RISCV/rvv/vmerge-rv32.ll |
| llvm/test/CodeGen/RISCV/rvv/vfptoi-sdnode.ll |
| llvm/test/CodeGen/RISCV/rvv/vor-sdnode-rv32.ll |
| llvm/test/CodeGen/RISCV/rvv/vmacc-rv32.ll |
| llvm/test/CodeGen/RISCV/rvv/vwmulu-rv64.ll |
| llvm/test/CodeGen/RISCV/rvv/rv64-spill-zvlsseg.ll |
| llvm/test/CodeGen/RISCV/rvv/vwsubu.w-rv64.ll |
| llvm/test/CodeGen/RISCV/rvv/vnmsac-rv32.ll |
| llvm/lib/Target/RISCV/RISCVRegisterInfo.td |
| llvm/test/CodeGen/RISCV/rvv/vmfle-rv64.ll |
| llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfadd-vp.ll |
| llvm/test/CodeGen/RISCV/rvv/vfslide1up-rv32.ll |
| llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-store-fp.ll |
| llvm/test/CodeGen/RISCV/rvv/vfptrunc-sdnode.ll |
| llvm/test/CodeGen/RISCV/rvv/vmax-rv32.ll |
| llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll |
| llvm/test/CodeGen/RISCV/rvv/vdiv-rv32.ll |
| llvm/test/CodeGen/RISCV/rvv/vrem-vp.ll |
| llvm/test/CodeGen/RISCV/rvv/vfwadd.w-rv32.ll |
| llvm/test/CodeGen/RISCV/rvv/vmfeq-rv64.ll |
| llvm/test/CodeGen/RISCV/rvv/select-sra.ll |
| llvm/test/CodeGen/RISCV/rvv/vxor-vp.ll |
| llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-x-f-rv64.ll |
| llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode-rv32.ll |
| llvm/test/CodeGen/RISCV/rvv/legalize-scalable-vectortype.ll |
| llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode-rv64.ll |
| llvm/test/CodeGen/RISCV/rvv/vfwsub.w-rv64.ll |
| llvm/test/CodeGen/RISCV/rvv/vrem-sdnode-rv64.ll |
| llvm/test/CodeGen/RISCV/rvv/vsadd-rv32.ll |
| llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv-fastcc.ll |
| llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctpop.ll |
| llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmul.ll |
| llvm/test/CodeGen/RISCV/rvv/vreductions-fp-sdnode.ll |
| llvm/test/CodeGen/RISCV/rvv/abs-sdnode.ll |
| llvm/test/CodeGen/RISCV/rvv/extract-subvector.ll |
| llvm/test/CodeGen/RISCV/rvv/vmflt-rv32.ll |
| llvm/test/CodeGen/RISCV/rvv/vadd-sdnode-rv32.ll |
| llvm/test/CodeGen/RISCV/rvv/vmaxu-sdnode-rv32.ll |
| llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vxor-vp.ll |
| llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-setcc.ll |
| llvm/test/CodeGen/RISCV/double-previous-failure.ll |
| llvm/test/CodeGen/RISCV/rvv/vmul-sdnode-rv32.ll |
| llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int-vp.ll |
| llvm/test/CodeGen/RISCV/rvv/vfwcvt-x-f-rv64.ll |
| llvm/test/CodeGen/RISCV/rvv/vwsubu-rv32.ll |
| llvm/test/CodeGen/RISCV/rvv/fixed-vectors-elen.ll |
| llvm/test/CodeGen/RISCV/rvv/vwadd.w-rv64.ll |
| llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv64.ll |
| llvm/test/CodeGen/RISCV/rvv/vmfge-rv64.ll |
| llvm/test/CodeGen/RISCV/rvv/fixed-vectors-select-int.ll |
| llvm/test/CodeGen/RISCV/rvv/vadd-rv32.ll |
| llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-setcc.ll |
| llvm/test/CodeGen/RISCV/rvv/mscatter-sdnode.ll |
| llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz.ll |
| llvm/test/CodeGen/RISCV/rvv/vselect-mask.ll |
| llvm/test/CodeGen/RISCV/rvv/combine-splats.ll |
| llvm/test/CodeGen/RISCV/rvv/vzext-rv32.ll |
| llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-vrgather.ll |
| llvm/test/CodeGen/RISCV/rvv/vfrsub-vp.ll |
| llvm/test/CodeGen/RISCV/rvv/vzext-rv64.ll |
| llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-x-rv32.ll |
| llvm/test/CodeGen/RISCV/rvv/vrgather-rv64.ll |
| llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll |
| llvm/test/CodeGen/RISCV/rvv/vmax-sdnode-rv32.ll |
| llvm/test/CodeGen/RISCV/rvv/vmsgtu-rv64.ll |
| llvm/test/CodeGen/RISCV/rvv/vrsub-vp.ll |
| llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv.ll |
| llvm/test/CodeGen/RISCV/rvv/vmsgt-rv64.ll |
| llvm/test/CodeGen/RISCV/rvv/vreductions-int-rv64.ll |
| llvm/test/CodeGen/RISCV/rvv/vremu-sdnode-rv64.ll |
| llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfrdiv-vp.ll |
| llvm/test/CodeGen/RISCV/rvv/vfwsub.w-rv32.ll |
| llvm/test/CodeGen/RISCV/rvv/vmsof-rv64.ll |
| llvm/test/CodeGen/RISCV/rvv/vnmsub-sdnode.ll |
| llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vreductions-mask.ll |
| llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-buildvec.ll |
| llvm/test/CodeGen/RISCV/rvv/vsplats-i1.ll |
| llvm/test/CodeGen/RISCV/rvv/localvar.ll |
| llvm/test/CodeGen/RISCV/rvv/vmflt-rv64.ll |
| llvm/test/CodeGen/RISCV/rvv/vmfne-rv32.ll |
| llvm/test/CodeGen/RISCV/rvv/vwaddu-rv32.ll |
| llvm/test/CodeGen/RISCV/rvv/combine-store-fp.ll |
| llvm/test/CodeGen/RISCV/rvv/fixed-vectors-unaligned.ll |
| llvm/test/CodeGen/RISCV/rvv/insertelt-i1.ll |
| llvm/test/CodeGen/RISCV/rvv/vmin-rv32.ll |
| llvm/test/CodeGen/RISCV/rvv/vrem-rv32.ll |
| llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv32.ll |
| llvm/test/CodeGen/RISCV/rvv/vmul-vp.ll |
| llvm/test/CodeGen/RISCV/rvv/vwmulu-rv32.ll |
| llvm/test/CodeGen/RISCV/rvv/fixed-vector-strided-load-store.ll |
| llvm/test/CodeGen/RISCV/rvv/vxor-sdnode-rv32.ll |
| llvm/test/CodeGen/RISCV/rvv/fixed-vectors-i2fp.ll |
| llvm/test/CodeGen/RISCV/rvv/vfncvt-f-f-rv64.ll |
| llvm/test/CodeGen/RISCV/rvv/mask-exts-truncs-rv32.ll |
| llvm/test/CodeGen/RISCV/rvv/vsub-sdnode-rv32.ll |
| llvm/test/CodeGen/RISCV/rvv/insertelt-fp-rv64.ll |
| llvm/test/CodeGen/RISCV/rvv/vfsub-vp.ll |
| llvm/test/CodeGen/RISCV/rvv/vpscatter-sdnode.ll |
| llvm/test/CodeGen/RISCV/rvv/insert-subvector.ll |
| llvm/test/CodeGen/RISCV/rvv/vmulh-sdnode-rv32.ll |
| llvm/test/CodeGen/RISCV/rvv/vsext-rv32.ll |
| llvm/test/CodeGen/RISCV/rvv/load-mask.ll |
| llvm/test/CodeGen/RISCV/rvv/vfpext-sdnode.ll |
| llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv32.ll |
| llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsaddu.ll |
| llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll |
| llvm/test/CodeGen/RISCV/rvv/vmfne-rv64.ll |
| llvm/test/CodeGen/RISCV/rvv/vtruncs-sdnode-rv64.ll |
| llvm/test/CodeGen/RISCV/rvv/setcc-integer-rv64.ll |
| llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll |
| llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-xu-f-rv32.ll |
| llvm/test/CodeGen/RISCV/rvv/fixed-vectors-select-fp.ll |
| llvm/test/CodeGen/RISCV/rvv/vfncvt-xu-f-rv64.ll |
| llvm/test/CodeGen/RISCV/rvv/vfwmul-rv64.ll |
| llvm/test/CodeGen/RISCV/rvv/extractelt-fp-rv64.ll |
| llvm/test/CodeGen/RISCV/rvv/vfwcvt-xu-f-rv64.ll |
| llvm/test/CodeGen/RISCV/rvv/vnclipu-rv32.ll |
| llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll |
| llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll |
| llvm/test/CodeGen/RISCV/rvv/vselect-fp-rv32.ll |
| llvm/test/CodeGen/RISCV/rvv/rvv-framelayout.ll |
| llvm/test/CodeGen/RISCV/rvv/vmsof-rv32.ll |
| llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vor-vp.ll |
| llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-splat.ll |
| llvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll |
| llvm/test/CodeGen/RISCV/rvv/vmsbc.borrow.in-rv64.ll |
| llvm/test/CodeGen/RISCV/rvv/vsext-rv64.ll |
| llvm/test/CodeGen/RISCV/rvv/vrgather-rv32.ll |
| llvm/test/CodeGen/RISCV/rvv/setcc-fp-rv32.ll |
| llvm/test/CodeGen/RISCV/rvv/select-int.ll |
| llvm/test/CodeGen/RISCV/rvv/vmseq-rv32.ll |
| llvm/test/CodeGen/RISCV/rvv/vmadc-rv32.ll |
| llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfrsub-vp.ll |
| llvm/test/CodeGen/RISCV/rvv/vmfeq-rv32.ll |
| llvm/test/CodeGen/RISCV/rvv/vsetvli-regression.ll |
| llvm/test/CodeGen/RISCV/rvv/vnclipu-rv64.ll |
| llvm/test/CodeGen/RISCV/rvv/vand-rv32.ll |
| llvm/test/CodeGen/RISCV/rvv/vremu-vp.ll |
| llvm/test/CodeGen/RISCV/rvv/vwadd.w-rv32.ll |
| llvm/test/CodeGen/RISCV/rvv/vmfgt-rv32.ll |
| llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-vrgather.ll |
| llvm/test/CodeGen/RISCV/rvv/vadc-rv32.ll |
| llvm/test/CodeGen/RISCV/rvv/saddo-sdnode.ll |
| llvm/test/CodeGen/RISCV/rvv/vfncvt-f-xu-rv64.ll |
| llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmulu.ll |
| llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfsub-vp.ll |
| llvm/test/CodeGen/RISCV/rvv/vssubu-rv32.ll |
| llvm/test/CodeGen/RISCV/rvv/vexts-sdnode-rv32.ll |
| llvm/test/CodeGen/RISCV/rvv/vslide1down-rv32.ll |
| llvm/test/CodeGen/RISCV/rvv/vmsgtu-rv32.ll |
| llvm/test/CodeGen/RISCV/rvv/vnsrl-rv32.ll |
| llvm/test/CodeGen/RISCV/rvv/vwadd-rv32.ll |
| llvm/test/CodeGen/RISCV/rvv/vremu-rv32.ll |
| llvm/test/CodeGen/RISCV/rvv/vmsge-rv32.ll |
| llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-i1.ll |
| llvm/test/CodeGen/RISCV/rvv/vnmsub-rv32.ll |
| llvm/test/CodeGen/RISCV/rvv/vwmulsu-rv32.ll |
| llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfdiv-vp.ll |
| llvm/test/CodeGen/RISCV/rvv/vnclip-rv32.ll |
| llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int.ll |
| llvm/test/CodeGen/RISCV/rvv/vfslide1up-rv64.ll |
| llvm/test/CodeGen/RISCV/rvv/vwsub-rv64.ll |
| llvm/test/CodeGen/RISCV/rvv/extload-truncstore.ll |
| llvm/test/CodeGen/RISCV/rvv/vminu-rv32.ll |
| llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll |
| llvm/test/CodeGen/RISCV/rvv/vsaddu-rv32.ll |
| llvm/test/CodeGen/RISCV/rvv/insertelt-fp-rv32.ll |
| llvm/test/CodeGen/RISCV/rvv/vasub-rv32.ll |
| llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-exttrunc.ll |
| llvm/test/CodeGen/RISCV/rvv/vasubu-rv32.ll |
| llvm/test/CodeGen/RISCV/fastcc-int.ll |
| llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-load-fp.ll |
| llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode-rv32.ll |
| llvm/test/CodeGen/RISCV/rvv/vmulhsu-rv32.ll |
| llvm/test/CodeGen/RISCV/rvv/vmsle-rv32.ll |
| llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vdivu-vp.ll |
| llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmaccu.ll |
| llvm/test/CodeGen/RISCV/rvv/vrsub-rv32.ll |
| llvm/test/CodeGen/RISCV/rvv/extractelt-fp-rv32.ll |
| llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-i1.ll |
| llvm/test/CodeGen/RISCV/rvv/vfadd-vp.ll |
| llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abs.ll |
| llvm/test/CodeGen/RISCV/rvv/vand-sdnode-rv32.ll |
| llvm/test/CodeGen/RISCV/rvv/vluxei-rv64.ll |
| llvm/test/CodeGen/RISCV/rvv/vmsltu-rv64.ll |
| llvm/test/CodeGen/RISCV/rvv/vmulhu-rv32.ll |
| llvm/test/CodeGen/RISCV/rvv/vwadd-rv64.ll |
| llvm/test/CodeGen/RISCV/rvv/select-fp.ll |
| llvm/test/CodeGen/RISCV/rvv/vfrdiv-vp.ll |
| llvm/test/CodeGen/RISCV/rvv/extractelt-i1.ll |
| llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect.ll |
| llvm/test/CodeGen/RISCV/rvv/vfncvt-x-f-rv64.ll |
| llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-xu-rv64.ll |
| llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll |
| llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-load-int.ll |
| llvm/test/CodeGen/RISCV/rvv/vnclip-rv64.ll |
| llvm/test/CodeGen/RISCV/rvv/vmsltu-rv32.ll |
| llvm/test/CodeGen/RISCV/rvv/vselect-int-rv32.ll |
| llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll |
| llvm/test/CodeGen/RISCV/rvv/mask-exts-truncs-rv64.ll |
| llvm/test/CodeGen/RISCV/rvv/vfwmul-rv32.ll |
| llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-shuffles.ll |
| llvm/test/CodeGen/RISCV/rvv/vloxei-rv64.ll |
| llvm/test/CodeGen/RISCV/rvv/vrgatherei16-rv64.ll |
| llvm/test/CodeGen/RISCV/rvv/vmsif-rv64.ll |
| llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse.ll |
| llvm/test/CodeGen/RISCV/rvv/vsm-rv64.ll |
| llvm/test/CodeGen/RISCV/rvv/vwsub.w-rv64.ll |
| llvm/test/CodeGen/RISCV/rvv/vfwadd-rv32.ll |
| llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extload-truncstore.ll |
| llvm/test/CodeGen/RISCV/rvv/vfcopysign-sdnode.ll |
| llvm/test/CodeGen/RISCV/rvv/rv64-spill-vector-csr.ll |
| llvm/test/CodeGen/RISCV/rvv/vsm-rv32.ll |
| llvm/test/CodeGen/RISCV/GlobalISel/calllowering-ret.ll |
| llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpscatter.ll |
| llvm/test/CodeGen/RISCV/rvv/vmadd-rv32.ll |
| llvm/test/CodeGen/RISCV/rvv/vreductions-mask-vp.ll |
| llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-xu-f-rv64.ll |
| llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-store-int.ll |
| llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll |
| llvm/test/CodeGen/RISCV/rvv/vfwcvt-xu-f-rv32.ll |
| llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vand-vp.ll |
| llvm/test/CodeGen/RISCV/rvv/load-add-store-16.ll |
| llvm/test/CodeGen/RISCV/rvv/vwaddu.w-rv32.ll |
| llvm/test/CodeGen/RISCV/rvv/common-shuffle-patterns.ll |
| llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpgather.ll |
| llvm/test/CodeGen/RISCV/rvv/vleff-rv64.ll |
| llvm/test/CodeGen/RISCV/rvv/vaadd-rv32.ll |
| llvm/test/CodeGen/RISCV/rvv/insertelt-int-rv32.ll |
| llvm/test/CodeGen/RISCV/rvv/vloxei-rv32.ll |
| llvm/test/CodeGen/RISCV/rvv/vwsub.w-rv32.ll |
| llvm/test/CodeGen/RISCV/rvv/addi-scalable-offset.mir |
| llvm/test/CodeGen/RISCV/rvv/vssub-rv32.ll |
| llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv32.ll |
| llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract.ll |
| llvm/test/CodeGen/RISCV/select-optimize-multiple.mir |
| llvm/test/CodeGen/RISCV/rvv/vitofp-sdnode.ll |
| llvm/test/CodeGen/RISCV/rvv/load-add-store-32.ll |
| llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll |
| llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vadd-vp.ll |
| llvm/test/CodeGen/RISCV/rvv/vmin-sdnode-rv32.ll |
| llvm/test/CodeGen/RISCV/rvv/vmsne-rv32.ll |
| llvm/test/CodeGen/RISCV/rvv/vminu-sdnode-rv32.ll |
| llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsadd.ll |
| llvm/test/CodeGen/RISCV/rvv/vfirst-rv32.ll |
| llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrsub-vp.ll |
| llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-subvector.ll |
| llvm/test/CodeGen/RISCV/rvv/vdivu-rv32.ll |
| llvm/test/CodeGen/RISCV/rvv/vsub-rv32.ll |
| llvm/test/CodeGen/RISCV/rvv/vsadd-sdnode.ll |
| llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vremu-vp.ll |
| llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-f-rv32.ll |
| llvm/test/CodeGen/RISCV/rvv/vmsgeu-rv64.ll |
| llvm/test/CodeGen/RISCV/rvv/vdivu-vp.ll |
| llvm/test/CodeGen/RISCV/rvv/vslide1up-rv32.ll |
| llvm/test/CodeGen/RISCV/rvv/insertelt-int-rv64.ll |
| llvm/test/CodeGen/RISCV/rvv/mask-reg-alloc.mir |
| llvm/test/CodeGen/RISCV/rvv/vfncvt-rod-f-f-rv32.ll |
| llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-x-f-rv64.ll |
| llvm/test/CodeGen/RISCV/rvv/vremu-sdnode-rv32.ll |
| llvm/test/CodeGen/RISCV/copy-frameindex.mir |
| llvm/test/CodeGen/RISCV/rvv/vfirst-rv64.ll |
| llvm/test/CodeGen/RISCV/rvv/vnsra-rv64.ll |
| llvm/test/CodeGen/RISCV/rvv/vsra-vp.ll |
| llvm/test/CodeGen/RISCV/rvv/vmslt-rv32.ll |
| llvm/test/CodeGen/RISCV/rvv/vmsleu-rv32.ll |
| llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp-vp.ll |
| llvm/test/CodeGen/RISCV/rvv/rv32-spill-zvlsseg.ll |
| llvm/test/CodeGen/RISCV/rvv/vslide1up-rv64.ll |
| llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-x-f-rv32.ll |
| llvm/test/CodeGen/RISCV/rvv/vmsle-rv64.ll |
| llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll |
| llvm/test/CodeGen/RISCV/rvv/vmadc.carry.in-rv32.ll |
| llvm/test/CodeGen/RISCV/rvv/vmfge-rv32.ll |
| llvm/test/CodeGen/RISCV/rvv/vmsleu-rv64.ll |
| llvm/test/CodeGen/RISCV/rvv/vexts-sdnode-rv64.ll |
| llvm/test/CodeGen/RISCV/rvv/vdiv-vp.ll |
| llvm/test/CodeGen/RISCV/rvv/vmseq-rv64.ll |
Commit
e678c51177102845c93529d457b020f969125373
by phosek[Support][ThinLTO] Move ThinLTO caching to LLVM Support library
We would like to move ThinLTO’s battle-tested file caching mechanism to
the LLVM Support library so that we can use it elsewhere in LLVM.
Patch By: noajshu
Differential Revision: https://reviews.llvm.org/D111371
|
| llvm/include/llvm/LTO/legacy/LTOCodeGenerator.h |
| lld/ELF/LTO.cpp |
| llvm/lib/Support/CMakeLists.txt |
| llvm/tools/gold/gold-plugin.cpp |
| llvm/include/llvm/LTO/LTO.h |
| llvm/include/llvm/LTO/Caching.h |
| llvm/tools/llvm-lto2/llvm-lto2.cpp |
| llvm/utils/gn/secondary/llvm/lib/LTO/BUILD.gn |
| llvm/lib/LTO/CMakeLists.txt |
| llvm/lib/Support/Caching.cpp |
| lld/wasm/LTO.cpp |
| llvm/utils/gn/secondary/llvm/lib/Support/BUILD.gn |
| clang/docs/tools/clang-formatted-files.txt |
| llvm/lib/LTO/LTOCodeGenerator.cpp |
| lld/COFF/LTO.cpp |
| lld/MachO/LTO.cpp |
| llvm/lib/LTO/Caching.cpp |
| clang/lib/CodeGen/BackendUtil.cpp |
| llvm/tools/llvm-lto/llvm-lto.cpp |
| llvm/include/llvm/Support/Caching.h |
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