Commit
d5c6b8407c12d39a78f42a216369407cb2d7b511
by aaronFactor out renaming logic from readability-identifier-naming Before this patch, readability-identifier-naming contained a significant amount of logic for (a) checking the style of identifiers, followed by (b) renaming/ applying fix-its. This patch factors out (b) into a separate base class so that it can be reused by other checks that want to do renaming. This also cleans up readability-identifier-naming significantly, since now it only needs to be concerned with the interesting details of (a).
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 | clang-tools-extra/clang-tidy/readability/IdentifierNamingCheck.h |
 | clang-tools-extra/clang-tidy/readability/IdentifierNamingCheck.cpp |
 | clang-tools-extra/clang-tidy/utils/CMakeLists.txt |
 | clang-tools-extra/clang-tidy/utils/RenamerClangTidyCheck.cpp |
 | clang-tools-extra/clang-tidy/utils/RenamerClangTidyCheck.h |
Commit
cbc63fbdc43b01387b9a604d953cd7627a0a15e2
by llvmgnsyncbot[gn build] Port d5c6b8407c1
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 | llvm/utils/gn/secondary/clang-tools-extra/clang-tidy/utils/BUILD.gn |
Commit
8b321929483ee3c4070a10c457733c1bddd10b51
by a.bataev[OPENMP]Avoid string concat where possible and use standard name generation function, NFC.
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 | clang/lib/CodeGen/CGOpenMPRuntime.cpp |
Commit
52b44902d059e68c6b5553c1d043f768c516064a
by spatel[IR] fix crash in Constant::isElementWiseEqual() with FP types We lifted this code from InstCombine for general usage in: rL369842 ...but it's not safe as-is. There are no existing users that can trigger this bug, but I discovered it via crashing several regression tests when trying to use it for select folding in InstSimplify. ICmp requires (vector) integer types, so give up on anything that's not integer or FP (pointers and ?) then bitcast the constants before trying the match. That matches the definition of "equal or undef" that I was looking for. If someone wants an FP-aware version of equality (deal with NaN, -0.0), that could be a different mode or different function. Differential Revision: https://reviews.llvm.org/D72784
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 | llvm/unittests/IR/ConstantsTest.cpp |
 | llvm/lib/IR/Constants.cpp |
Commit
3a05c3969c18b5520e360b78fc63cda39a6be98f
by dschuff[WebAssembly] Track frame registers through VReg and local allocation This change has 2 components: Target-independent: add a method getDwarfFrameBase to TargetFrameLowering. It describes how the Dwarf frame base will be encoded. That can be a register (the default), the CFA (which replaces NVPTX-specific logic in DwarfCompileUnit), or a DW_OP_WASM_location descriptr. WebAssembly: Allow WebAssemblyFunctionInfo::getFrameRegister to return the correct virtual register instead of FP32/SP32 after WebAssemblyReplacePhysRegs has run. Make WebAssemblyExplicitLocals store the local it allocates for the frame register. Use this local information to implement getDwarfFrameBase The result is that the DW_AT_frame_base attribute is correctly encoded for each subprogram, and each param and local variable has a correct DW_AT_location that uses DW_OP_fbreg to refer to the frame base. Differential Revision: https://reviews.llvm.org/D71681
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 | llvm/test/MC/WebAssembly/dwarfdump.ll |
 | llvm/test/CodeGen/WebAssembly/multi-return.ll |
 | llvm/lib/Target/WebAssembly/WebAssemblyRegisterInfo.cpp |
 | llvm/lib/Target/WebAssembly/WebAssemblyReplacePhysRegs.cpp |
 | llvm/lib/Target/WebAssembly/WebAssemblyMachineFunctionInfo.h |
 | llvm/lib/Target/WebAssembly/WebAssemblyOptimizeLiveIntervals.cpp |
 | llvm/lib/Target/NVPTX/NVPTXFrameLowering.h |
 | lld/test/wasm/debuginfo.test |
 | llvm/lib/Target/NVPTX/NVPTXFrameLowering.cpp |
 | llvm/test/MC/WebAssembly/debug-info.ll |
 | llvm/include/llvm/CodeGen/TargetFrameLowering.h |
 | llvm/test/MC/WebAssembly/debug-localvar.ll |
 | llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp |
 | llvm/lib/Target/WebAssembly/WebAssemblyExplicitLocals.cpp |
 | llvm/lib/Target/WebAssembly/WebAssemblyFrameLowering.cpp |
 | llvm/lib/CodeGen/TargetFrameLoweringImpl.cpp |
 | llvm/lib/Target/WebAssembly/WebAssemblyFrameLowering.h |
Commit
202446c639fdd27a54c3be268154a7c66af4f36d
by kparzyszAdd BuiltinsHexagonDep.def to clang module map
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 | clang/include/clang/module.modulemap |
Commit
fa4112fffc6bd81ba44a9e6ffb19f4314f6e37b0
by sbc[llvm-nm] Use `StringRef` over `const std::string &` params Differential Revision: https://reviews.llvm.org/D72718
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 | llvm/tools/llvm-nm/llvm-nm.cpp |
Commit
91e758b7329b4ff134684e661af93a85c436a460
by arsenm2AMDGPU: Move permlane discard vdst_in optimization This case can be handled as a regular selection pattern, so move it out of the weird post-isel folding code which doesn't have an exactly equivalent place in GlobalISel. I think it doesn't make much sense to do this optimization here though, and it would be more useful in instcombine. There's not really any new information that will be gained during lowering since these inputs were known from the beginning.
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 | llvm/lib/Target/AMDGPU/SIISelLowering.cpp |
 | llvm/lib/Target/AMDGPU/VOP3Instructions.td |
Commit
3ef8cdf6660fc20baeb09eae5008b741f178b624
by arsenm2AMDGPU: Do permlane16 vdst_in discard optimization in InstCombine There's more potential value to discarding the source value earlier, since we always know the value of the fi/bc bits.
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 | llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp |
 | llvm/test/Transforms/InstCombine/AMDGPU/amdgcn-intrinsics.ll |
Commit
80906d9d16043377ad322c7c44d8a4d3f9914808
by dschuffRevert "[WebAssembly] Track frame registers through VReg and local allocation" This reverts commit 3a05c3969c18b5520e360b78fc63cda39a6be98f. It breaks under expensive-checks and on Windows
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 | llvm/lib/Target/WebAssembly/WebAssemblyFrameLowering.cpp |
 | llvm/test/MC/WebAssembly/debug-info.ll |
 | llvm/test/CodeGen/WebAssembly/multi-return.ll |
 | llvm/include/llvm/CodeGen/TargetFrameLowering.h |
 | llvm/test/MC/WebAssembly/dwarfdump.ll |
 | llvm/lib/Target/WebAssembly/WebAssemblyExplicitLocals.cpp |
 | llvm/lib/Target/WebAssembly/WebAssemblyRegisterInfo.cpp |
 | llvm/lib/Target/WebAssembly/WebAssemblyMachineFunctionInfo.h |
 | llvm/lib/Target/NVPTX/NVPTXFrameLowering.h |
 | lld/test/wasm/debuginfo.test |
 | llvm/lib/Target/NVPTX/NVPTXFrameLowering.cpp |
 | llvm/test/MC/WebAssembly/debug-localvar.ll |
 | llvm/lib/Target/WebAssembly/WebAssemblyFrameLowering.h |
 | llvm/lib/Target/WebAssembly/WebAssemblyOptimizeLiveIntervals.cpp |
 | llvm/lib/Target/WebAssembly/WebAssemblyReplacePhysRegs.cpp |
 | llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp |
 | llvm/lib/CodeGen/TargetFrameLoweringImpl.cpp |
Commit
6c4d37733403bf3fda260f1b05fc899427a61cdc
by Vedant Kumarlldb: xfail TestCrossDSOTailCalls.py and TestCrossObjectTailCalls.py on arm/aarch64 This effectively reverts commit 8d2f252bb8e4d199be8498c4ee2245117ef08fd2, which went a bit too far and disabled these on all non-Darwin systems.
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 | lldb/packages/Python/lldbsuite/test/functionalities/tail_call_frames/cross_dso/TestCrossDSOTailCalls.py |
 | lldb/packages/Python/lldbsuite/test/functionalities/tail_call_frames/cross_object/TestCrossObjectTailCalls.py |
Commit
9050d0fb593c60628f47caa122c01ea1dc7a1bf5
by phosek[libcxx] Temporarily switch back to pthread backend for Fuchsia We switched to C11 thread API on Fuchsia in ab9aefe, but further testing showed that Fuchsia's C11 mutex implementation needs a few improvements for this to be usable, so we temporarily switch back to the pthread implementation until those issues are addressed. Differential Revision: https://reviews.llvm.org/D72862
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 | libcxx/include/__config |
Commit
51b521c07a7a784d087d6a4c176b132cc4e36db7
by sbc[lld][WebAssembly] Use a more meaningful name for stub functions When we generate these stub functions on signature mismatches give them a more meaningful name so that when people see this in stack traces is gives a clue as the what is going on. See: https://github.com/emscripten-core/emscripten/issues/10226 Differential Revision: https://reviews.llvm.org/D72881
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 | lld/test/wasm/signature-mismatch.ll |
 | lld/wasm/SymbolTable.cpp |
 | lld/test/wasm/signature-mismatch-export.ll |
Commit
73f371c31d2774b3e4d51e4e276737d54922aa18
by zinenko[mlir] NFC: Fix trivial typos Summary: Fix trivial typos Differential Revision: https://reviews.llvm.org/D72672
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 | mlir/include/mlir/Dialect/VectorOps/VectorOps.td |
 | mlir/tools/mlir-tblgen/SPIRVUtilsGen.cpp |
 | mlir/utils/spirv/define_inst.sh |
 | mlir/include/mlir/Dialect/SPIRV/SPIRVTypes.h |
 | mlir/lib/Dialect/SPIRV/SPIRVOps.cpp |
 | mlir/include/mlir/Dialect/SPIRV/SPIRVBase.td |
 | mlir/lib/Dialect/GPU/Transforms/MemoryPromotion.cpp |
 | mlir/include/mlir/Dialect/SPIRV/SPIRVAvailability.td |
Commit
a4a42160c4463eac74c5d0cfa9a88c4971d8a23e
by zinenko[mlir] support translation of multidimensional vectors to LLVM IR Summary: MLIR unlike LLVM IR supports multidimensional vector types. Such types are lowered to nested LLVM IR arrays wrapping an LLVM IR vector for the innermost dimension of the MLIR vector. MLIR supports constants of such types using ElementsAttr for values. Introduce support for converting ElementsAttr into LLVM IR Constant Aggregates recursively. This enables translation of multidimensional vector constants from MLIR to LLVM IR. Differential Revision: https://reviews.llvm.org/D72846
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 | mlir/lib/Target/LLVMIR/ModuleTranslation.cpp |
 | mlir/test/Target/llvmir.mlir |
 | mlir/test/Target/llvmir-invalid.mlir |
Commit
42b3c38903c9c80e129ce678db7f522967e91eeb
by Jan Korous[clangd][test] Disable a particular testcase in FindExplicitReferencesTest when LLVM_ENABLE_EXPENSIVE_CHECKS The test is failing on our CI bots. Seems like the order of results for one target is undefined. (post-commit review) Differential Revision: https://reviews.llvm.org/D72883
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 | clang-tools-extra/clangd/unittests/FindTargetTests.cpp |
Commit
9b549f26fab6900b5328c0c6239fd77c7527159c
by arsenm2AMDGPU: Update clang test
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 | clang/test/CodeGenOpenCL/builtins-amdgcn-gfx10.cl |
Commit
25b542c61fe364fa86163723b9e35cb7db28bcb4
by a.bataev[OPENMP]Do not emit RTTI descriptor for NVPTX devices. Need to disable emission of RTTI descriptors for NVPTX devices to be able to use dynamic classes without unresolved symbols at link stage.
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 | clang/test/OpenMP/nvptx_target_pure_deleted_codegen.cpp |
 | clang/lib/CodeGen/CodeGenModule.cpp |
Commit
b82d18e1e8e6a997f304cbf591e92af02e067fdb
by Jessica Paquette[AArch64][GlobalISel] Change G_FCONSTANTs feeding into stores into G_CONSTANTS Given the following situation: x = G_FCONSTANT (something that can't be materialized) G_STORE x, some_addr We know that x must be materialized as at least a single mov. However, at the time of selection, the G_STORE will have been regbankselected to a FPR store. So, as a result, you'll get an unnecessary fmov into the G_STORE. Storing a constant value in a GPR and a constant value in a FPR are the same. So, whenever you see a G_FCONSTANT that feeds into only G_STORES, so might as well make it a G_CONSTANT. This adds a target-specific combine which changes G_FCONSTANTs feeding into G_STOREs into G_CONSTANTs. Differential Revision: https://reviews.llvm.org/D72814
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 | llvm/lib/Target/AArch64/AArch64PreLegalizerCombiner.cpp |
 | llvm/test/CodeGen/AArch64/GlobalISel/combine-fconstant.mir |
 | llvm/lib/Target/AArch64/AArch64Combine.td |