SuccessChanges

Summary

  1. Refactored getSingleBranchSchedulers, since now we use LLVMBuildFactory for all of the builders. (details)
  2. Got rid of legacy schedulers. (details)
Commit 993dd9a2b15d0dbfbad4c86377b8fca9cfed0852 by gkistanova
Refactored getSingleBranchSchedulers, since now we use LLVMBuildFactory for all of the builders.
The file was modifiedbuildbot/osuosl/master/config/schedulers.py (diff)
Commit 9c39add1f0c8aba6f5835466e72226890cc962cd by gkistanova
Got rid of legacy schedulers.
The file was modifiedbuildbot/osuosl/master/master.cfg (diff)

Summary

  1. PowerPC: Fix SPE extloadf32 handling. (details)
  2. PowerPC: Don't lower SELECT_CC to PPCISD::FSEL on SPE (details)
Commit 914dbf4808d46632cc7b8dda861a11f978083416 by jrh29
PowerPC: Fix SPE extloadf32 handling.

The patterns were incorrect copies from the FPU code, and are
unnecessary, since there's no extended load for SPE.  Just let LLVM
itself do the work by marking it expand.

Reviewed By: #powerpc, lkail
Differential Revision: https://reviews.llvm.org/D78670
The file was modifiedllvm/lib/Target/PowerPC/PPCInstrSPE.td
The file was modifiedllvm/test/CodeGen/PowerPC/spe.ll
The file was modifiedllvm/lib/Target/PowerPC/PPCISelLowering.cpp
Commit 7e9153e940e21a937ff3a0e7425eb1b24bd1bb76 by jrh29
PowerPC: Don't lower SELECT_CC to PPCISD::FSEL on SPE

SPE doesn't have a fsel instruction, so don't try to lower to it.

This fixes a "Cannot select: tN: f64 = PPCISD::FSEL tX, tY, tZ" error.

Reviewed By: #powerpc, lkail
Differential Revision: https://reviews.llvm.org/D77773
The file was addedllvm/test/CodeGen/PowerPC/spe-fastmath.ll
The file was modifiedllvm/lib/Target/PowerPC/PPCISelLowering.cpp