Changes

Summary

  1. Fix a capitalisation problem (details)
Commit 0b51f5220a80f7a99b6d9e0d2f9129d62792f2d7 by gribozavr
Fix a capitalisation problem

The build system doesn't accept "All" here, we must pass "all".
The file was modifiedbuildbot/osuosl/master/config/builders.py (diff)

Summary

  1. [DSE] Add capture-before test cases with loads. (details)
  2. [ARM] Prevent continuous folding of SUBC (details)
  3. [mlir][Linalg] Replace DenseSet by UnionFind in ComprehensiveBufferize - NFC (details)
  4. [mlir][Linalg] Make codegen strategy late transformations opt-in (details)
  5. [gn build] (manually) port 2c42a73d6c39 (details)
  6. [ARM] Move fetching of ARMSubtarget into the scopes that need it. NFC. (details)
  7. [lldb] [Windows] Fix an incorrect assert in NativeRegisterContextWindows_arm (details)
  8. [CostModel][X86] Adjust bitreverse/ctpop/ctlz/cttz AVX2+ costs based on llvm-mca reports (details)
  9. [PhaseOrdering] add tests for PR47023; NFC (details)
  10. [InstCombine] Transform X == 0 ? 0 : X * Y --> X * freeze(Y) (details)
  11. [RISCV][compiler-rt] Add missing __riscv_save_1/0 labels for RV64 (details)
  12. [RISCV][compiler-rt] Move RV64 __riscv_restore_1/0 directives next to labels (details)
Commit 05c120823b6893c1384835d47656125cdd751550 by flo
[DSE] Add capture-before test cases with loads.

Add a set of test cases where redundant stores may be removable,
depending on whether a local allocation gets captured before performing
a load.
The file was addedllvm/test/Transforms/DeadStoreElimination/captures-before-load.ll
Commit a2332d5332c3ede49adf1c71481e9efab7ca88c7 by david.green
[ARM] Prevent continuous folding of SUBC

Under some situations under Thumb1, we could be stuck in an infinite
loop recombining the same instruction. This puts a limit on that, not
combining SUBC with SUBE repeatedly.
The file was modifiedllvm/test/CodeGen/ARM/select_const.ll
The file was modifiedllvm/lib/Target/ARM/ARMISelLowering.cpp
Commit e3889b30590a8d61eec42b08bbe3708322c15205 by nicolas.vasilache
[mlir][Linalg] Replace DenseSet by UnionFind in ComprehensiveBufferize - NFC

AliasInfo can now use union-find for a much more efficient implementation.
This brings no functional changes but large performance gains on more complex examples.

Differential Revision: https://reviews.llvm.org/D109819
The file was modifiedmlir/lib/Dialect/Linalg/Transforms/ComprehensiveBufferize.cpp
Commit 660f281b5e755663b2d8ad061075eb5f5abdf9fb by nicolas.vasilache
[mlir][Linalg] Make codegen strategy late transformations opt-in

Summary: Making the late transformations opt-in results in less surprising behavior when composing multiple calls to the codegen strategy.

Reviewers:

Subscribers:

Differential revision: https://reviews.llvm.org/D109820
The file was modifiedmlir/test/lib/Dialect/Linalg/TestLinalgCodegenStrategy.cpp
The file was modifiedmlir/include/mlir/Dialect/Linalg/Transforms/CodegenStrategy.h
Commit afc45ff06fac83209c631f2573789fde48b8b397 by thakis
[gn build] (manually) port 2c42a73d6c39
The file was modifiedllvm/utils/gn/secondary/llvm/test/BUILD.gn
Commit b33a43e57c8c4405cfa3d1a8fb187063d3857c34 by martin
[ARM] Move fetching of ARMSubtarget into the scopes that need it. NFC.

This was requested in D38253, but missed back then.

Differential Revision: https://reviews.llvm.org/D109046
The file was modifiedllvm/lib/Target/ARM/ARMAsmPrinter.cpp
Commit b4133a21cef49edb57cf96bb7d7518099d61e910 by martin
[lldb] [Windows] Fix an incorrect assert in NativeRegisterContextWindows_arm

This codepath hadn't been exercised in a build with asserts before.

Differential Revision: https://reviews.llvm.org/D109778
The file was modifiedlldb/source/Plugins/Process/Windows/Common/NativeRegisterContextWindows_arm.cpp
Commit 0767e43d87453e76e418cabb2b96fdacd1a4981c by llvm-dev
[CostModel][X86] Adjust bitreverse/ctpop/ctlz/cttz AVX2+ costs based on llvm-mca reports

Based off the worse case numbers generated by D103695, the AVX2/512 bit reversing/counting costs were higher than necessary (based off instruction counts instead of actual throughput).
The file was modifiedllvm/lib/Target/X86/X86TargetTransformInfo.cpp
The file was modifiedllvm/test/Analysis/CostModel/X86/bitreverse.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/cttz.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/cttz.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/ctlz.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/ctlz.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/ctpop.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/ctpop.ll
Commit be1028053e935524620de91a30035f1ff0a7f9aa by spatel
[PhaseOrdering] add tests for PR47023; NFC
The file was addedllvm/test/Transforms/PhaseOrdering/X86/store-constant-merge.ll
Commit f5d89523567b08420ff3fa48a6fc50dbf530afa8 by spatel
[InstCombine] Transform X == 0 ? 0 : X * Y --> X * freeze(Y)

Enabled mul folding optimization that was previously disabled
by being incorrect.
To preserve correctness, mul's operand that is not compared
with zero in select's condition is now frozen.

Related bug: https://bugs.llvm.org/show_bug.cgi?id=51286

Correctness:
https://alive2.llvm.org/ce/z/bHef7J
https://alive2.llvm.org/ce/z/QcR7sf
https://alive2.llvm.org/ce/z/vvBLzt
https://alive2.llvm.org/ce/z/jGDXgq
https://alive2.llvm.org/ce/z/3Pe8Z4
https://alive2.llvm.org/ce/z/LGga8M
https://alive2.llvm.org/ce/z/CTG5fs

Differential Revision: https://reviews.llvm.org/D108408
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
The file was modifiedllvm/test/Transforms/InstCombine/select.ll
Commit 3c885190af219417a71e315e7c5999e67b783d03 by jrtc27
[RISCV][compiler-rt] Add missing __riscv_save_1/0 labels for RV64

These got missed in D91717.
The file was modifiedcompiler-rt/lib/builtins/riscv/save.S
Commit bbca392a7f31bb76f024481292d900618988e780 by jrtc27
[RISCV][compiler-rt] Move RV64 __riscv_restore_1/0 directives next to labels

This looks like it was copied from the RV32 version and not properly
updated. This has no functional effect but is not good style.
The file was modifiedcompiler-rt/lib/builtins/riscv/restore.S