Changes

Summary

  1. [Clang] Always set opaque pointers mode (details)
  2. [InstCombine] Fix inbounds preservation when swapping GEPs (PR44206) (details)
  3. [X86] narrowExtractedVectorSelect - don't peek through bitcasts to find source vector (details)
  4. attributes: introduce allockind attr for describing allocator fn behavior (details)
  5. BuildLibCalls: infer allockind attributes on relevant functions (details)
  6. Revert "[Libomptarget] Add `leaf` attribute to `vprintf` declaration" (details)
  7. [AArch64] Remove references to Streaming SVE from target features. (details)
  8. [Driver][Modules] Remove dependence on linking support from clang/test/Driver/modules.cpp (details)
  9. LangRef: fix bad indentation in allockind bullets (details)
  10. [X86] combineEXTRACT_SUBVECTOR - pull out repeated getVectorNumElements() calls. NFC. (details)
  11. [clangd] ExtractVariable support for C and Objective-C (details)
  12. [AMDGPU] gfx11 Image instructions (details)
  13. [PS5] Tweak dllexport test (details)
  14. [Scalarizer] Regenerate test checks (NFC) (details)
  15. [flang] Support BIND(C) variable scope check (details)
  16. [clangd] Minor fixes to ExtractVariableTests missed in D124486 (details)
  17. [Clang][Docs] Document the clang-offload-packager better (details)
  18. [MLIR][Math] Improve docs (NFC) (details)
  19. [Clang][Docs] Fix typo in offload packager reference (details)
  20. [X86] LowerMINMAX - split v4i64 types on AVX1 targets (Issue #55648) (details)
  21. [X86] Add test case for PR55648 (details)
  22. [InstCombine] add tests for icmp of sext i1; NFC (details)
  23. [InstCombine] fold icmp of sext bool based on limited range (details)
  24. [RISCV] Pre-commit tests for D126635. NFC (details)
  25. [RISCV] Fix a few corner case bugs in RISCVMergeBaseOffsetOpt::matchLargeOffset (details)
Commit 858e6273d938cc4d08ee053ddff3fe7b19eb302a by npopov
[Clang] Always set opaque pointers mode

Always set the opaque pointers mode, to make sure that
-no-opaque-pointers continues working when the default on the LLVM
side is flipped.
The file was modifiedclang/lib/CodeGen/CodeGenAction.cpp
Commit 36cbdaa163bd4250923eff0812f0e84ca129347e by npopov
[InstCombine] Fix inbounds preservation when swapping GEPs (PR44206)

When reassociating GEPs, we can only keep inbounds if both original
GEPs were inbounds, and their offsets have the same sign. For the
sake of simplicity, I only handle the case where both offsets are
non-negative here.

It would probably be fine to just not preserve inbounds at all here,
but as I don't see a compile-time impact for adding the
isKnownNonNegative() calls I went with this more conservative
approach.

Fixes https://github.com/llvm/llvm-project/issues/44206.

Differential Revision: https://reviews.llvm.org/D126687
The file was modifiedllvm/test/Transforms/InstCombine/gep-combine-loop-invariant.ll
The file was modifiedllvm/test/Transforms/LoopVectorize/X86/x86-interleaved-accesses-masked-group.ll
The file was modifiedllvm/test/Transforms/LoopVectorize/ARM/mve-reductions.ll
The file was modifiedllvm/lib/Transforms/InstCombine/InstructionCombining.cpp
The file was modifiedllvm/test/Transforms/LoopVectorize/consecutive-ptr-uniforms.ll
The file was modifiedllvm/test/Transforms/LoopVectorize/X86/x86-interleaved-store-accesses-with-gaps.ll
The file was modifiedllvm/test/Transforms/LoopVectorize/interleaved-accesses.ll
Commit b9443cb6fa6ba0be030cb0ed5f556d69c7f7de56 by llvm-dev
[X86] narrowExtractedVectorSelect - don't peek through bitcasts to find source vector

We don't seem to need this for any test coverage and it was making tracking of the uses() of the source vector more difficult

Noticed while investigating Issue #55648
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
Commit 42861faa8e17058f0b4a027bba13ef59a600e051 by augie
attributes: introduce allockind attr for describing allocator fn behavior

I chose to encode the allockind information in a string constant because
otherwise we would get a bit of an explosion of keywords to deal with
the possible permutations of allocation function types.

I'm not sure that CodeGen.h is the correct place for this enum, but it
seemed to kind of match the UWTableKind enum so I put it in the same
place. Constructive suggestions on a better location most certainly
encouraged.

Differential Revision: https://reviews.llvm.org/D123088
The file was modifiedllvm/include/llvm/Bitcode/LLVMBitCodes.h
The file was modifiedllvm/include/llvm/IR/Attributes.h
The file was addedllvm/test/Verifier/allockind.ll
The file was modifiedllvm/lib/Transforms/Utils/CodeExtractor.cpp
The file was modifiedllvm/test/Bitcode/compatibility.ll
The file was modifiedllvm/lib/Bitcode/Reader/BitcodeReader.cpp
The file was modifiedllvm/lib/Bitcode/Writer/BitcodeWriter.cpp
The file was modifiedllvm/lib/IR/AttributeImpl.h
The file was modifiedllvm/docs/LangRef.rst
The file was addedllvm/test/Assembler/allockind-missing.ll
The file was modifiedllvm/include/llvm/AsmParser/LLParser.h
The file was addedllvm/test/Assembler/allockind.ll
The file was modifiedllvm/include/llvm/IR/Attributes.td
The file was modifiedllvm/lib/AsmParser/LLParser.cpp
The file was modifiedllvm/lib/IR/Attributes.cpp
The file was modifiedllvm/lib/IR/Verifier.cpp
Commit 73f664601c105e5897e12bf9766c2f7e79c92e62 by augie
BuildLibCalls: infer allockind attributes on relevant functions

Differential Revision: https://reviews.llvm.org/D123089
The file was modifiedllvm/test/Transforms/InferFunctionAttrs/annotate.ll
The file was modifiedllvm/lib/Transforms/Utils/BuildLibCalls.cpp
Commit ae766526777ae5ff34d2dadb99038b596e3c715f by jhuber6
Revert "[Libomptarget] Add `leaf` attribute to `vprintf` declaration"

This is preventing users from calling `printf` on NVPTX code. Revert for
now until there is a fix.

This reverts commit eda4ef3add4d25345e0b29580776f1576040c525.
The file was modifiedopenmp/libomptarget/DeviceRTL/src/Debug.cpp
Commit 9c38fc111b9e1319ffa8e4a165e40ff7c7814406 by sander.desmalen
[AArch64] Remove references to Streaming SVE from target features.

Following discussion on D120261 and D121208 it seems better to remove the
concept of Streaming SVE from the subtarget/assembler predicates and
instead reason about 'SVE' and 'SME' as its higher level features, rather
than trying to model this runtime mode through explicit feature flags.

This patch is largely NFC.

Reviewed By: paulwalker-arm, david-arm

Differential Revision: https://reviews.llvm.org/D125977
The file was modifiedllvm/test/MC/AArch64/SVE/st3b.s
The file was modifiedllvm/test/MC/AArch64/SVE/sdivr.s
The file was modifiedllvm/test/MC/AArch64/SVE/fnmla.s
The file was modifiedllvm/test/CodeGen/AArch64/sve2-intrinsics-contiguous-conflict-detection.ll
The file was modifiedllvm/test/MC/AArch64/SVE/ld3h.s
The file was modifiedllvm/test/CodeGen/AArch64/sve-intrinsics-reversal.ll
The file was modifiedllvm/test/MC/AArch64/SVE2/sshllt.s
The file was modifiedllvm/test/MC/AArch64/SVE2/uhsubr.s
The file was modifiedllvm/test/MC/AArch64/SVE/cmplt.s
The file was modifiedllvm/test/CodeGen/AArch64/sve2-intrinsics-widening-dsp.ll
The file was modifiedllvm/test/MC/AArch64/SVE/cmpgt.s
The file was modifiedllvm/test/MC/AArch64/SVE/sxtb.s
The file was modifiedllvm/test/MC/AArch64/SVE/orr.s
The file was modifiedllvm/test/MC/AArch64/SVE2/sqxtunt.s
The file was modifiedllvm/test/MC/AArch64/SVE/rdffrs.s
The file was modifiedllvm/test/CodeGen/AArch64/sve2-intrinsics-unary-narrowing.ll
The file was modifiedllvm/test/MC/AArch64/SVE2/sqrshrnt.s
The file was modifiedllvm/test/MC/AArch64/SVE/ldff1w.s
The file was modifiedllvm/test/MC/AArch64/SVE/clasta.s
The file was modifiedllvm/test/MC/AArch64/SVE2/sri.s
The file was modifiedllvm/test/MC/AArch64/SVE/mov.s
The file was modifiedllvm/test/CodeGen/AArch64/sve-intrinsics-pred-creation.ll
The file was modifiedllvm/test/MC/AArch64/SVE/sqdecb.s
The file was modifiedllvm/test/MC/AArch64/SVE/sqdecd.s
The file was modifiedllvm/test/MC/AArch64/SVE2/rax1.s
The file was modifiedllvm/test/MC/AArch64/SVE/cmpls.s
The file was modifiedllvm/test/MC/AArch64/SVE/umax.s
The file was modifiedllvm/test/MC/AArch64/SVE2/sqdmullb.s
The file was modifiedllvm/test/MC/AArch64/SVE2/ssra.s
The file was modifiedllvm/test/MC/AArch64/SVE/uqdecb.s
The file was modifiedllvm/test/MC/AArch64/SVE2/eor3.s
The file was modifiedllvm/test/MC/AArch64/SVE2/ssubwt.s
The file was modifiedllvm/test/MC/AArch64/SVE/sqdech.s
The file was modifiedllvm/test/MC/AArch64/SVE2/sqrdcmlah.s
The file was modifiedllvm/test/MC/AArch64/SVE2/umlalb.s
The file was modifiedllvm/test/MC/AArch64/SVE/fnmsb.s
The file was modifiedllvm/test/MC/AArch64/SVE/prfd.s
The file was modifiedllvm/test/MC/AArch64/SVE/fmad.s
The file was modifiedllvm/test/MC/AArch64/SVE2/sbclb.s
The file was modifiedllvm/test/MC/AArch64/SVE2/fmlalt.s
The file was modifiedllvm/test/MC/AArch64/SVE/ptrues.s
The file was modifiedllvm/test/MC/AArch64/SVE/stnt1h.s
The file was modifiedllvm/test/MC/AArch64/SVE/st1b-sve-only.s
The file was modifiedllvm/test/MC/AArch64/SVE/ld4b.s
The file was modifiedllvm/test/MC/AArch64/SVE2/urshr.s
The file was modifiedllvm/test/MC/AArch64/SVE/fmaxnmv.s
The file was modifiedllvm/test/MC/AArch64/SVE/ld1d-sve-only.s
The file was modifiedllvm/test/MC/AArch64/SVE/cnt.s
The file was modifiedllvm/test/MC/AArch64/SVE/ld4w.s
The file was modifiedllvm/test/MC/AArch64/SVE/msb.s
The file was modifiedllvm/test/MC/AArch64/SVE2/sqrdmlsh.s
The file was modifiedllvm/test/MC/AArch64/SVE/ldnf1b.s
The file was modifiedllvm/test/MC/AArch64/SVE/uqdecw.s
The file was modifiedllvm/test/MC/AArch64/SVE/fmov.s
The file was modifiedllvm/test/MC/AArch64/SVE2/shsub.s
The file was modifiedllvm/test/MC/AArch64/SVE/dupm.s
The file was modifiedllvm/test/MC/AArch64/SVE/fcmne.s
The file was modifiedllvm/test/MC/AArch64/SVE2/ursra.s
The file was modifiedllvm/test/MC/AArch64/SVE/uxtb.s
The file was modifiedllvm/test/MC/AArch64/SVE2/bsl.s
The file was modifiedllvm/test/MC/AArch64/SVE2/smlalb.s
The file was modifiedllvm/test/MC/AArch64/SVE2/uaddlt.s
The file was modifiedllvm/test/MC/AArch64/SVE/clz.s
The file was modifiedllvm/test/MC/AArch64/SVE/cmphi.s
The file was modifiedllvm/test/MC/AArch64/SVE2/smaxp.s
The file was modifiedllvm/test/MC/AArch64/SVE/saddv.s
The file was modifiedllvm/test/MC/AArch64/SVE/ld1b-sve-only.s
The file was modifiedllvm/test/MC/AArch64/SVE/ld1rb.s
The file was modifiedllvm/test/MC/AArch64/SVE/ldnf1d.s
The file was modifiedllvm/test/CodeGen/AArch64/sve-intrinsics-ldN-sret-reg+reg-addr-mode.ll
The file was modifiedllvm/test/MC/AArch64/SVE2/sqabs.s
The file was modifiedllvm/test/MC/AArch64/SVE2/addhnt.s
The file was modifiedllvm/test/MC/AArch64/SVE2/match.s
The file was modifiedllvm/test/CodeGen/AArch64/sve-intrinsics-create-tuple.ll
The file was modifiedllvm/test/MC/AArch64/SVE/brkbs.s
The file was modifiedllvm/test/MC/AArch64/SVE2/suqadd.s
The file was modifiedllvm/test/MC/AArch64/SVE2/srsra.s
The file was modifiedllvm/test/MC/AArch64/SVE/fexpa.s
The file was modifiedllvm/test/MC/AArch64/SVE2/aese.s
The file was modifiedllvm/test/MC/AArch64/SVE2/ssublb.s
The file was modifiedllvm/test/MC/AArch64/SVE2/smulh.s
The file was modifiedllvm/test/MC/AArch64/SVE/ld1sb-sve-only.s
The file was modifiedllvm/test/MC/AArch64/SVE2/uadalp.s
The file was modifiedllvm/test/MC/AArch64/SVE/lslr.s
The file was modifiedllvm/test/MC/AArch64/SVE/fmla.s
The file was modifiedllvm/test/MC/AArch64/SVE/decp.s
The file was modifiedllvm/test/MC/AArch64/SVE/ldnf1sh.s
The file was modifiedllvm/test/MC/AArch64/SVE/st2w.s
The file was modifiedllvm/test/MC/AArch64/SVE/addpl.s
The file was modifiedllvm/test/MC/AArch64/SVE/uqincb.s
The file was modifiedllvm/test/CodeGen/AArch64/sve-intrinsics-while.ll
The file was modifiedllvm/test/MC/AArch64/SVE/decw.s
The file was modifiedllvm/test/MC/AArch64/SVE/incw.s
The file was modifiedllvm/test/MC/AArch64/SVE2/aesimc.s
The file was modifiedllvm/test/MC/AArch64/SVE/ld1h-sve-only.s
The file was modifiedllvm/test/MC/AArch64/SVE/ldnf1w.s
The file was modifiedllvm/test/MC/AArch64/SVE/brkb.s
The file was modifiedllvm/test/MC/AArch64/SVE/fmls.s
The file was modifiedllvm/test/MC/AArch64/SVE2/ushllb.s
The file was modifiedllvm/test/CodeGen/AArch64/sve-intrinsics-fp-converts.ll
The file was modifiedllvm/test/MC/AArch64/SVE2/smlslb.s
The file was modifiedllvm/test/MC/AArch64/SVE/uaddv.s
The file was modifiedllvm/test/MC/AArch64/SVE/mad.s
The file was modifiedllvm/test/CodeGen/AArch64/sve-intrinsics-counting-elems.ll
The file was modifiedllvm/test/MC/AArch64/SVE/smaxv.s
The file was modifiedllvm/test/MC/AArch64/SVE/umulh.s
The file was modifiedllvm/test/MC/AArch64/SVE2/aesmc.s
The file was modifiedllvm/test/MC/AArch64/SVE/incb.s
The file was modifiedllvm/test/MC/AArch64/SVE2/uqshrnt.s
The file was modifiedllvm/test/MC/AArch64/SVE/orns.s
The file was modifiedllvm/test/MC/AArch64/SVE/fcadd.s
The file was modifiedllvm/test/MC/AArch64/SVE/fmul.s
The file was modifiedllvm/test/MC/AArch64/SVE2/fmlslb.s
The file was modifiedllvm/test/MC/AArch64/SVE/eor.s
The file was modifiedllvm/test/MC/AArch64/SVE/smin.s
The file was modifiedllvm/test/MC/AArch64/SVE2/umlslb.s
The file was modifiedllvm/test/MC/AArch64/SVE/decb.s
The file was modifiedllvm/test/MC/AArch64/SVE2/srshl.s
The file was modifiedllvm/test/MC/AArch64/SVE/frsqrts.s
The file was modifiedllvm/test/MC/AArch64/SVE/dech.s
The file was modifiedllvm/test/MC/AArch64/SVE/lsl.s
The file was modifiedllvm/test/MC/AArch64/SVE/ctermne.s
The file was modifiedllvm/test/MC/AArch64/SVE2/flogb.s
The file was modifiedllvm/test/MC/AArch64/SVE/incd.s
The file was modifiedllvm/test/MC/AArch64/SVE/eon.s
The file was modifiedllvm/test/MC/AArch64/SVE2/fmaxnmp.s
The file was modifiedllvm/test/CodeGen/AArch64/sve-intrinsics-stores.ll
The file was modifiedllvm/test/MC/AArch64/SVE/fcmge.s
The file was modifiedllvm/test/MC/AArch64/SVE2/ldnt1w.s
The file was modifiedllvm/test/MC/AArch64/SVE/fmulx.s
The file was modifiedllvm/test/MC/AArch64/SVE/bfmlal.s
The file was modifiedllvm/test/MC/AArch64/SVE/uzp2.s
The file was modifiedllvm/test/MC/AArch64/SVE/udivr.s
The file was modifiedllvm/test/MC/AArch64/SVE/abs.s
The file was modifiedllvm/test/MC/AArch64/SVE2/bgrp.s
The file was modifiedllvm/test/MC/AArch64/SVE2/sabalt.s
The file was modifiedllvm/test/CodeGen/AArch64/sve2-intrinsics-while.ll
The file was modifiedllvm/test/MC/AArch64/SVE/fsqrt.s
The file was modifiedllvm/test/MC/AArch64/SVE/ld1rsb.s
The file was modifiedllvm/test/MC/AArch64/SVE/st3d.s
The file was modifiedllvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
The file was modifiedllvm/test/MC/AArch64/SVE2/uqshlr.s
The file was modifiedllvm/test/MC/AArch64/SVE/sdot.s
The file was modifiedllvm/test/MC/AArch64/SVE/brkns.s
The file was modifiedllvm/test/CodeGen/AArch64/sve2-intrinsics-fp-widening-mul-acc.ll
The file was modifiedllvm/test/MC/AArch64/SVE/ld2w.s
The file was modifiedllvm/test/MC/AArch64/SVE/mul.s
The file was modifiedllvm/test/MC/AArch64/SVE/whilele.s
The file was modifiedllvm/test/MC/AArch64/SVE2/ldnt1sw.s
The file was modifiedllvm/test/MC/AArch64/SVE/ld1sb.s
The file was modifiedllvm/test/MC/AArch64/SVE/trn1.s
The file was modifiedllvm/test/MC/AArch64/SVE/st3h.s
The file was modifiedllvm/test/MC/AArch64/SVE2/sqshrunb.s
The file was modifiedllvm/test/MC/AArch64/SVE2/whilegt.s
The file was modifiedllvm/test/MC/AArch64/SVE2/sqsub.s
The file was modifiedllvm/test/MC/AArch64/SVE/frsqrte.s
The file was modifiedllvm/test/MC/AArch64/SVE/inch.s
The file was modifiedllvm/test/MC/AArch64/SVE/ldff1d.s
The file was modifiedllvm/test/MC/AArch64/SVE2/sabalb.s
The file was modifiedllvm/test/CodeGen/AArch64/sve-intrinsics-insert-extract-tuple.ll
The file was modifiedllvm/test/CodeGen/AArch64/sve2-intrinsics-uniform-complex-arith.ll
The file was modifiedllvm/test/MC/AArch64/SVE/sqadd.s
The file was modifiedllvm/test/MC/AArch64/SVE/whilels.s
The file was modifiedllvm/test/MC/AArch64/SVE2/uaba.s
The file was modifiedllvm/test/MC/AArch64/SVE2/ldnt1sh.s
The file was modifiedllvm/test/MC/AArch64/SVE2/umulh.s
The file was modifiedllvm/test/MC/AArch64/SVE2/usqadd.s
The file was modifiedllvm/test/MC/AArch64/SVE2/whilewr.s
The file was modifiedllvm/test/MC/AArch64/SVE2/pmullt.s
The file was modifiedllvm/test/MC/AArch64/SVE/ld3b.s
The file was modifiedllvm/test/MC/AArch64/SVE2/sqrdmulh.s
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The file was modifiedllvm/test/CodeGen/AArch64/sve-intrinsics-stN-reg-reg-addr-mode.ll
The file was modifiedllvm/test/MC/AArch64/SVE2/bsl2n.s
The file was modifiedllvm/test/CodeGen/AArch64/sve-intrinsics-counting-bits.ll
The file was modifiedllvm/test/MC/AArch64/SVE2/uhsub.s
The file was modifiedllvm/test/MC/AArch64/SVE2/uqshrnb.s
The file was modifiedllvm/test/MC/AArch64/SVE/ldnf1h.s
The file was modifiedllvm/test/MC/AArch64/SVE2/ushllt.s
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The file was modifiedllvm/test/MC/AArch64/SVE/fmin.s
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The file was modifiedllvm/test/MC/AArch64/SVE2/sadalp.s
The file was modifiedllvm/test/MC/AArch64/SVE2/usra.s
The file was modifiedllvm/test/MC/AArch64/SVE/sqincw.s
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The file was modifiedllvm/test/MC/AArch64/SVE2/smullt.s
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The file was modifiedllvm/test/CodeGen/AArch64/sve2-intrinsics-widening-complex-int-arith.ll
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The file was modifiedllvm/test/MC/AArch64/SVE2/nbsl.s
The file was modifiedllvm/test/MC/AArch64/SVE/index.s
The file was modifiedllvm/test/MC/AArch64/SVE2/srshlr.s
The file was modifiedllvm/test/CodeGen/AArch64/sve-intrinsics-stN-reg-imm-addr-mode.ll
The file was modifiedllvm/test/MC/AArch64/SVE/fcmle.s
The file was modifiedllvm/test/MC/AArch64/SVE/ld1sh.s
The file was modifiedllvm/test/MC/AArch64/SVE/decd.s
The file was modifiedllvm/test/MC/AArch64/SVE2/fminnmp.s
The file was modifiedllvm/test/MC/AArch64/SVE/fcmeq.s
The file was modifiedllvm/test/MC/AArch64/SVE/cls.s
The file was modifiedllvm/test/MC/AArch64/SVE/fcvtzs.s
The file was modifiedllvm/test/MC/AArch64/SVE2/rsubhnb.s
The file was modifiedllvm/test/MC/AArch64/SVE2/sqdmlalb.s
The file was modifiedllvm/test/CodeGen/AArch64/sve-intrinsics-sel.ll
The file was modifiedllvm/test/MC/AArch64/SVE2/usubwt.s
The file was modifiedllvm/test/MC/AArch64/SVE2/stnt1b.s
The file was modifiedllvm/test/MC/AArch64/SVE/sqdecw.s
The file was modifiedllvm/test/MC/AArch64/SVE2/shrnb.s
The file was modifiedllvm/test/MC/AArch64/SVE2/shsubr.s
The file was modifiedllvm/test/MC/AArch64/SVE/ld1w.s
The file was modifiedllvm/test/MC/AArch64/SVE/ld2d.s
The file was modifiedllvm/test/MC/AArch64/SVE/frinti.s
The file was modifiedllvm/test/MC/AArch64/SVE/asr.s
The file was modifiedllvm/test/MC/AArch64/SVE/st1w.s
The file was modifiedllvm/test/MC/AArch64/SVE/fnmad.s
The file was modifiedllvm/test/MC/AArch64/SVE2/sqcadd.s
The file was modifiedllvm/test/MC/AArch64/SVE/eors.s
The file was modifiedllvm/test/MC/AArch64/SVE2/whilehs.s
The file was modifiedllvm/test/MC/AArch64/SVE/uqincp.s
The file was modifiedllvm/test/MC/AArch64/SVE2/xar.s
The file was modifiedllvm/test/MC/AArch64/SVE/sxth.s
The file was modifiedllvm/test/MC/AArch64/SVE/ld1rqd.s
The file was modifiedllvm/test/MC/AArch64/SVE/whilelo.s
The file was modifiedllvm/test/MC/AArch64/SVE/fminv.s
The file was modifiedllvm/test/MC/AArch64/SVE/orn.s
The file was modifiedllvm/test/MC/AArch64/SVE/cnth.s
The file was modifiedllvm/test/MC/AArch64/SVE2/smlalt.s
The file was modifiedllvm/test/MC/AArch64/SVE2/uabdlb.s
The file was modifiedllvm/test/MC/AArch64/SVE/ld2h.s
The file was modifiedllvm/test/MC/AArch64/SVE2/splice.s
The file was modifiedllvm/test/MC/AArch64/SVE/smax.s
The file was modifiedllvm/test/MC/AArch64/SVE2/saddlt.s
The file was modifiedllvm/test/MC/AArch64/SVE/fcmgt.s
The file was modifiedllvm/test/MC/AArch64/SVE/fcvt.s
The file was modifiedllvm/test/MC/AArch64/SVE/uqdech.s
The file was modifiedllvm/test/MC/AArch64/SVE2/sminp.s
The file was modifiedllvm/test/MC/AArch64/SVE/fminnm.s
The file was modifiedllvm/test/MC/AArch64/SVE/ldnt1b.s
The file was modifiedllvm/test/MC/AArch64/SVE/ldnt1h.s
The file was modifiedllvm/test/MC/AArch64/SVE2/pmullt-128.s
The file was modifiedllvm/test/MC/AArch64/SVE2/uqrshlr.s
The file was modifiedllvm/test/MC/AArch64/SVE2/sqdmlslt.s
The file was modifiedllvm/test/MC/AArch64/SVE/trn2.s
The file was modifiedllvm/test/MC/AArch64/SVE2/bcax.s
The file was modifiedllvm/test/MC/AArch64/SVE2/sqshl.s
The file was modifiedllvm/test/CodeGen/AArch64/sve-intrinsics-uqdec.ll
The file was modifiedllvm/test/MC/AArch64/SVE/prfd-sve-only.s
The file was modifiedllvm/test/MC/AArch64/SVE/facgt.s
The file was modifiedllvm/test/CodeGen/AArch64/sve2-intrinsics-binary-narrowing-add-sub.ll
The file was modifiedllvm/test/CodeGen/AArch64/sve2-intrinsics-polynomial-arithmetic.ll
The file was modifiedllvm/test/MC/AArch64/SVE/ptrue.s
The file was modifiedllvm/test/MC/AArch64/SVE/incp.s
Commit 35b1cfc76f08faabf3f27c0bd054acc7c854a6ca by Daniel.McIntosh
[Driver][Modules] Remove dependence on linking support from clang/test/Driver/modules.cpp

The new tests in clang/test/Driver/modules.cpp added by D120540 will fail if the
toolchain getting tested doesn't support linking. This reduces the utility of
the test since we would like a failure of this test to reflect a problem with
modules. We should already have other tests that validate linking support.

Reviewed By: ChuanqiXu

Differential Revision: https://reviews.llvm.org/D126669
The file was modifiedclang/test/Driver/modules.cpp
Commit b0a1a308f268249565823b7992249393f2a52887 by augie
LangRef: fix bad indentation in allockind bullets
The file was modifiedllvm/docs/LangRef.rst
Commit af0113cf77b3df93495182507cb41e54927188c7 by llvm-dev
[X86] combineEXTRACT_SUBVECTOR - pull out repeated getVectorNumElements() calls. NFC.
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
Commit ae67984ca6d89c7ccdbdca258cd05c151d8b6431 by davg
[clangd] ExtractVariable support for C and Objective-C

- Use the expression's type for non-C++ as the variable type. This works
  well, but might not preserve the typedefs due to type
  canonicalization.

- Improve support for Objective-C property references which are
  represented using `ObjCPropertyRefExpr` and `BuiltinType::PseudoObject`.

Differential Revision: https://reviews.llvm.org/D124486
The file was modifiedclang-tools-extra/clangd/unittests/tweaks/ExtractVariableTests.cpp
The file was modifiedclang-tools-extra/clangd/refactor/tweaks/ExtractVariable.cpp
Commit e8860bee283855b2e1ce7eefb085a86e9ae3262b by Joseph.Nash
[AMDGPU] gfx11 Image instructions

MC layer support for instructions in the MIMG encoding(Image
instructions).

Contributors:
Carl Ritson <carl.ritson@amd.com>

Patch 13/N for upstreaming of AMDGPU gfx11 architecture.

Depends on D125992

Reviewed By: rampitec, #amdgpu

Differential Revision: https://reviews.llvm.org/D126463
The file was modifiedllvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
The file was addedllvm/test/MC/AMDGPU/gfx11_asm_mimg.s
The file was addedllvm/test/MC/Disassembler/AMDGPU/gfx11_mimg.txt
The file was addedllvm/test/MC/AMDGPU/gfx11_asm_mimg_err.s
The file was modifiedllvm/lib/Target/AMDGPU/MIMGInstructions.td
The file was modifiedllvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
The file was modifiedllvm/lib/Target/AMDGPU/SIInstrFormats.td
Commit 10555a82df22bf67a9c30165e952b44969b46b6f by paul.robinson
[PS5] Tweak dllexport test

Post-commit review pointed out that both PS4 and PS5 were using the
same -std argument, better to use different ones just in case.
The file was modifiedclang/test/SemaCXX/dllexport.cpp
Commit 1257315b20d5f2487c4445c129b7437d5f2debfd by npopov
[Scalarizer] Regenerate test checks (NFC)
The file was modifiedllvm/test/Transforms/Scalarizer/basic.ll
The file was modifiedllvm/test/Transforms/Scalarizer/basic-inseltpoison.ll
Commit f3d8335383672df3b3b950a082c2b11a80cbdb9d by qiaopeixin
[flang] Support BIND(C) variable scope check

As Fortran 2018 C819, a variable with the BIND attribute shall be declared
in the specification part of a module. Add the support for this check.

Reviewed By: klausler

Differential Revision: https://reviews.llvm.org/D126653
The file was addedflang/test/Semantics/resolve113.f90
The file was modifiedflang/lib/Semantics/check-declarations.cpp
Commit c797952d4f012275b2e23f5ffcab1f39eacd184d by davg
[clangd] Minor fixes to ExtractVariableTests missed in D124486
The file was modifiedclang-tools-extra/clangd/unittests/tweaks/ExtractVariableTests.cpp
Commit e22b02d9b4f8bb968628ac7cf2d9a42bf13e2898 by jhuber6
[Clang][Docs] Document the clang-offload-packager better

Summary:
This patch adds more in-depth documentation to the
clang-offload-packacker's binary format. This format is used to create
fat binaries and link them.
The file was modifiedclang/docs/ClangOffloadPackager.rst
Commit 850dbff708f1e371722306363231a3816179ad7b by l.chelini
[MLIR][Math] Improve docs (NFC)

Remove boilerplate examples and add a text at the dialect level to describe
what kind of operands the operations accept (i.e., scalar, tensor or vector).
Left a shorter sentence describing the input operands for each operation as
this redundancy is convenient when browsing the documentation using the
website.

Reviewed By: ftynse

Differential Revision: https://reviews.llvm.org/D126648
The file was modifiedmlir/include/mlir/Dialect/Math/IR/MathBase.td
The file was modifiedmlir/include/mlir/Dialect/Math/IR/MathOps.td
Commit 259a9df963ca5f28f325ed6f6bfe5da639c78cbf by jhuber6
[Clang][Docs] Fix typo in offload packager reference
The file was modifiedclang/docs/ClangOffloadPackager.rst
Commit d5af6a38082b39ae520a328e44dc29ebcb036bb2 by llvm-dev
[X86] LowerMINMAX - split v4i64 types on AVX1 targets (Issue #55648)

Originally we tried to use default expansion for v4i64 types to make it easier to concatenate the results back together, but this can cause infinite loop issues with existing VSELECT splitting code in narrowExtractedVectorSelect if we have other uses of the VSELECT results (e.g. reduction patterns).

To fix the infinite loop, this patch always splits MIN/MAX v4i64 nodes during lowering and I've added a TODO for combineConcatVectorOps to investigate when we can cheaply concatenate VSELECT/BLENDV nodes together.

Fixes #55648 - regression test case will be added in a follow up.
The file was modifiedllvm/test/CodeGen/X86/horizontal-reduce-smax.ll
The file was modifiedllvm/test/CodeGen/X86/vec_minmax_uint.ll
The file was modifiedllvm/test/CodeGen/X86/vector-trunc-ssat.ll
The file was modifiedllvm/test/CodeGen/X86/masked_store_trunc_ssat.ll
The file was modifiedllvm/test/CodeGen/X86/vec_minmax_sint.ll
The file was modifiedllvm/test/CodeGen/X86/vector-pcmp.ll
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
The file was modifiedllvm/test/CodeGen/X86/vector-trunc-usat.ll
The file was modifiedllvm/test/CodeGen/X86/vector-reduce-umax.ll
The file was modifiedllvm/test/CodeGen/X86/vector-trunc-packus.ll
The file was modifiedllvm/test/CodeGen/X86/vector-reduce-smax.ll
The file was modifiedllvm/test/CodeGen/X86/vector-reduce-smin.ll
The file was modifiedllvm/test/CodeGen/X86/horizontal-reduce-umax.ll
The file was modifiedllvm/test/CodeGen/X86/horizontal-reduce-umin.ll
The file was modifiedllvm/test/CodeGen/X86/masked_store_trunc_usat.ll
The file was modifiedllvm/test/CodeGen/X86/vector-reduce-umin.ll
The file was modifiedllvm/test/CodeGen/X86/midpoint-int-vec-256.ll
The file was modifiedllvm/test/CodeGen/X86/vselect-minmax.ll
The file was modifiedllvm/test/CodeGen/X86/horizontal-reduce-smin.ll
Commit a7317a5728edc67bac2cb6d774e649bba10eb533 by llvm-dev
[X86] Add test case for PR55648
The file was addedllvm/test/CodeGen/X86/pr55648.ll
Commit f3fe38448b8c41f828ed03dc704e8b918e3b773e by spatel
[InstCombine] add tests for icmp of sext i1; NFC

These are adapted from the zext tests added for D126171.
The file was modifiedllvm/test/Transforms/InstCombine/icmp-range.ll
Commit 2bf6123f22c65995dec60e02944b459424532d9b by spatel
[InstCombine] fold icmp of sext bool based on limited range

X <=u (sext i1 Y) --> (X == 0) | Y

https://alive2.llvm.org/ce/z/W_tZzo

This is the conjugate/sibling pattern suggested with D126171
for a sign-extended bool value.
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
The file was modifiedllvm/test/Transforms/InstCombine/icmp-range.ll
Commit 3b5456d5f0d1fbfcdf6f6a18e9adec5e42a560ee by craig.topper
[RISCV] Pre-commit tests for D126635. NFC
The file was modifiedllvm/test/CodeGen/RISCV/hoist-global-addr-base.ll
Commit 80c4cf6369459f90e103339fcb9f6767474f478b by craig.topper
[RISCV] Fix a few corner case bugs in RISCVMergeBaseOffsetOpt::matchLargeOffset

The immediate for LUI is stored as 20-bit unsigned value. We need
to sign extend if after shifting by 12 to match the instruction
behavior.

If we find an LUI+ADDI on RV64, it means the constant isn't a
simm32. If it was, we would have emitted LUI+ADDIW from constant
materialization. Make sure the constant is a simm32 before folding.
This appears to match gcc.

A future patch will add support for LUI+ADDIW on RV64.
The file was modifiedllvm/lib/Target/RISCV/RISCVMergeBaseOffset.cpp
The file was modifiedllvm/test/CodeGen/RISCV/hoist-global-addr-base.ll