Commit
daa1c6d9d126ea1666463c44930f00df83f3acd6
by l.lunak[lldb] fix typo
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 | lldb/source/Core/IOHandlerCursesGUI.cpp |
Commit
e218da7ff39df3aeb7c923fbd75aaa8ace581e37
by aqjune[JumpThreading] Add a test for simplification of cast of any op; NFC
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 | llvm/test/Transforms/JumpThreading/threadable-edge-cast.ll |
Commit
e734e8286b4b521d829aaddb6d1cbbd264953625
by aqjune[JumpThreading] Remove cast's constraint
As discussed in D84949, this removes the constraint to cast since it does not cause compile time degradation.
Reviewed By: lebedev.ri
Differential Revision: https://reviews.llvm.org/D85188
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 | llvm/test/Transforms/JumpThreading/threadable-edge-cast.ll |
 | llvm/lib/Transforms/Scalar/JumpThreading.cpp |
Commit
4be13b15d69d9d70506277eb1900eadccd75f608
by paul.walker[SVE] Replace remaining _MERGE_OP1 nodes with _PRED variants.
This is the final bit of work to relax the register allocation requirements when code generating normal LLVM IR, which rarely care about the result of inactive lanes. By using _PRED nodes we can make better use of SVE's reversed instructions.
Also removes a redundant parameter from the min/max tests.
Differential Revision: https://reviews.llvm.org/D85142
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 | llvm/lib/Target/AArch64/SVEInstrFormats.td |
 | llvm/lib/Target/AArch64/AArch64ISelLowering.cpp |
 | llvm/test/CodeGen/AArch64/llvm-ir-to-intrinsic.ll |
 | llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td |
 | llvm/lib/Target/AArch64/AArch64ISelLowering.h |
Commit
79b44a4d470041acf202027054ba86e935d86aa1
by Xing[YAMLTraits] Fix mapping <none> value that followed by comments.
When mapping an optional value, if the value is <none> and followed by comments, there will be a parsing error. This patch helps fix this issue.
e.g.,
When mapping the following YAML,
``` Sections: - Name: blah Type: SHT_foo Flags: [[FLAGS=<none>]] ## some comments. ```
the raw value of `ScalarNode` is "<none> " rather than "<none>". We need to remove the spaces.
Differential Revision: https://reviews.llvm.org/D85180
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 | llvm/include/llvm/Support/YAMLTraits.h |
 | llvm/test/tools/yaml2obj/ELF/none-value.yaml |
Commit
fd6584a22043b254a323635c142b28ce80ae5b5b
by sander.desmalen[AArch64][SVE] Fix CFA calculation in presence of SVE objects.
The CFA is calculated as (SP/FP + offset), but when there are SVE objects on the stack the SP offset is partly scalable and should instead be expressed as the DWARF expression:
SP + offset + scalable_offset * VG
where VG is the Vector Granule register, containing the number of 64bits 'granules' in a scalable vector.
Reviewed By: efriedma
Differential Revision: https://reviews.llvm.org/D84043
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 | llvm/include/llvm/MC/MCDwarf.h |
 | llvm/lib/Target/AArch64/AArch64FrameLowering.h |
 | llvm/test/CodeGen/AArch64/sve-trunc.ll |
 | llvm/lib/Target/AArch64/AArch64FrameLowering.cpp |
 | llvm/lib/Target/AArch64/AArch64RegisterInfo.td |
 | llvm/lib/Target/AArch64/AArch64StackOffset.h |
 | llvm/lib/CodeGen/AsmPrinter/AsmPrinterDwarf.cpp |
 | llvm/test/CodeGen/AArch64/framelayout-sve.mir |
Commit
bb3344c7d8c2703c910dd481ada43ecaf11536a6
by sander.desmalen[AArch64][SVE] Add missing unwind info for SVE registers.
This patch adds a CFI entry for each SVE callee saved register that needs unwind info at an offset from the CFA. The offset is a DWARF expression because the offset is partly scalable.
The CFI entries only cover a subset of the SVE callee-saves and only encodes the lower 64-bits, thus implementing the lowest common denominator ABI. Existing unwinders may support VG but only restore the lower 64-bits.
Reviewed By: efriedma
Differential Revision: https://reviews.llvm.org/D84044
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 | llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp |
 | llvm/lib/Target/AArch64/AArch64RegisterInfo.h |
 | llvm/test/CodeGen/AArch64/framelayout-sve.mir |
 | llvm/lib/Target/AArch64/AArch64FrameLowering.cpp |
 | llvm/lib/Target/AArch64/AArch64FrameLowering.h |
 | llvm/test/CodeGen/AArch64/sve-trunc.ll |
Commit
998c0efee0e6d6909fdee579e6d2694babd99c0f
by aqjune[JumpThreading] Update test freeze.ll; NFC
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 | llvm/test/Transforms/JumpThreading/freeze.ll |
Commit
f003b28363f9e09f3f68a5e08ebcca2635a4cdca
by georgemitenk0v[MLIR][SPIRVToLLVM] Indentation and style fix in tests
This is a first patch that sweeps over tests to fix indentation (tabs to spaces). It also adds label checks and removes redundant matching of `%{{.*}} = `.
The following tests have been fixed: - arithmetic-ops-to-llvm - bitwise-ops-to-llvm - cast-ops-to-llvm - comparison-ops-to-llvm - logical-ops-to-llvm (renamed to match the rest)
Reviewed By: ftynse
Differential Revision: https://reviews.llvm.org/D85181
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 | mlir/test/Conversion/SPIRVToLLVM/arithmetic-ops-to-llvm.mlir |
 | mlir/test/Conversion/SPIRVToLLVM/logical-to-llvm.mlir |
 | mlir/test/Conversion/SPIRVToLLVM/bitwise-ops-to-llvm.mlir |
 | mlir/test/Conversion/SPIRVToLLVM/cast-ops-to-llvm.mlir |
 | mlir/test/Conversion/SPIRVToLLVM/comparison-ops-to-llvm.mlir |
 | mlir/test/Conversion/SPIRVToLLVM/logical-ops-to-llvm.mlir |
Commit
8979a9cdf226066196f1710903d13492e6929563
by pifon[mlir] Fix adding wrong operand value in `promoteMemRefDescriptors`.
The bug was not noticed because we didn't have a lot of custom type conversions directly to LLVM dialect.
Differential Revision: https://reviews.llvm.org/D85192
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 | mlir/lib/Conversion/StandardToLLVM/StandardToLLVM.cpp |
Commit
d4fbbab2e494a59480096a257136ed2b75d07e87
by zinenko[mlir] translate types between MLIR LLVM dialect and LLVM IR
With new LLVM dialect type modeling, the dialect types no longer wrap LLVM IR types. Therefore, they need to be translated to and from LLVM IR during export and import. Introduce the relevant functionality for translating types. It is currently exercised by an ad-hoc type translation roundtripping test that will be subsumed by the actual translation test when the type system transition is complete.
Depends On D84339
Reviewed By: herhut
Differential Revision: https://reviews.llvm.org/D85019
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 | mlir/test/Target/llvmir-types.mlir |
 | mlir/test/lib/Target/CMakeLists.txt |
 | mlir/lib/Target/CMakeLists.txt |
 | mlir/lib/Target/LLVMIR/TypeTranslation.cpp |
 | mlir/tools/mlir-translate/CMakeLists.txt |
 | mlir/include/mlir/Target/LLVMIR/TypeTranslation.h |
 | mlir/test/lib/CMakeLists.txt |
 | mlir/tools/mlir-translate/mlir-translate.cpp |
 | mlir/test/lib/Target/TestLLVMTypeTranslation.cpp |
Commit
6abd7e2e622bc7eabdb673a7815f6673523a1e94
by zinenko[mlir] provide same APIs as existing LLVMType in the new LLVM type modeling
These are intended to smoothen the transition and may be removed in the future in favor of more MLIR-compatible APIs. They intentionally have the same semantics as the existing functions, which must remain stable until the transition is complete.
Depends On D85019
Reviewed By: nicolasvasilache
Differential Revision: https://reviews.llvm.org/D85020
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 | mlir/include/mlir/Dialect/LLVMIR/LLVMTypes.h |
 | mlir/lib/Dialect/LLVMIR/IR/LLVMTypes.cpp |
Commit
20c71e55aad5bf6008c7f5ed63c90ed98907fa99
by spatel[InstSimplify] reduce code for min/max analysis; NFC
This should probably be moved up to some common area eventually when there's another user.
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 | llvm/lib/Analysis/InstructionSimplify.cpp |
Commit
011e15bea3456cf429a801e309c65bef14fa22ad
by spatel[InstSimplify] add tests for min/max with constants; NFC
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 | llvm/test/Transforms/InstSimplify/maxmin_intrinsics.ll |