SuccessChanges

Summary

  1. [RISCV] Support EXTRACT_SUBVECTOR on vector masks (details)
  2. [RISCV] Unify scalable- and fixed-vector INSERT_SUBVECTOR lowering (details)
  3. [RISCV] Fix INSERT/EXTRACT_SUBVECTOR on fractional LMUL types (details)
  4. [RISCV] Support INSERT_SUBVECTOR on vector masks (details)
  5. Use the default seed value for djb hash for StringMap (details)
  6. [AArch64] Adjust dot produce tests. NFC (details)
  7. [AArch64] Add combine for add(udot(0, x, y), z) -> udot(z, x, y). (details)
  8. Revert "Use the default seed value for djb hash for StringMap" (details)
  9. [mlir] Add convenience grouping for tensor type inference (details)
  10. [AArch64] NFC: Cleanup some SVE cost-model tests. (details)
  11. AArch64/GlobalISel: Fix using wrong calling convention for calls (details)
  12. GlobalISel: Move splitToValueTypes to generic code (details)
  13. GlobalISel: Verify G_CONCAT_VECTORS has at least 2 sources (details)
Commit bd4d4216881d2ddba170808a8cd2f7b75cbc8de9 by fraser
[RISCV] Support EXTRACT_SUBVECTOR on vector masks

This patch adds support for extracting subvectors from vector masks.
This can be either extracting a scalable vector from another, or a fixed-length
vector from a fixed-length or scalable vector.

Since RVV lacks a way to slide vector masks down on an element-wise
basis and we don't know the true length of the vector registers, in many
cases we must resort to using equivalently-sized i8 vectors to perform
the operation. When this is not possible we fall back and extend to a
suitable i8 vector.

Support was also added for fixed-length truncation to mask types.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D97475
The file was modifiedllvm/lib/Target/RISCV/RISCVISelLowering.cpp
The file was modifiedllvm/test/CodeGen/RISCV/rvv/extract-subvector.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-subvector.ll
Commit 4ea734e6ec9da0587da733424fe616b7e401cf8c by fraser
[RISCV] Unify scalable- and fixed-vector INSERT_SUBVECTOR lowering

This patch unifies the two disparate paths for lowering INSERT_SUBVECTOR
operations under one roof. Consequently, with this patch it is possible to
support any fixed-length subvector insertion, not just "cast-like" ones.

As before, support for the insertion of mask vectors will come in a
separate patch.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D97543
The file was modifiedllvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
The file was modifiedllvm/lib/Target/RISCV/RISCVISelLowering.cpp
The file was addedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll
Commit e80ca3af82f8177a1b239bab6bb25d08ec86adeb by fraser
[RISCV] Fix INSERT/EXTRACT_SUBVECTOR on fractional LMUL types

This patch fixes a bug where the lowering for INSERT_SUBVECTOR and
EXTRACT_SUBVECTOR would insist on first extracting a register-aligned
LMUL1 vector type before perfoming the slide up/down. This was even if
the vector was a fractional LMUL type, in which case the aligned
EXTRACT_SUBVECTOR was invalid.

This issue only occurred for scalable vector types, but a variety of
tests for both scalable and fixed-length vectors have been added to
ensure this does not regress in the future.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D97556
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-subvector.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/extract-subvector.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/insert-subvector.ll
The file was modifiedllvm/lib/Target/RISCV/RISCVISelLowering.cpp
Commit 3fea9226eecd2069bea93c4fe5955b0b5ff316f7 by fraser
[RISCV] Support INSERT_SUBVECTOR on vector masks

Like with EXTRACT_SUBVECTOR, INSERT_SUBVECTOR poses a problem
for vector masks as RVV isn't able to slide mask types around. We choose
instead to bitcast to equivalently-sized i8 types where we can, else we
zero-extend, perform the operation, and truncate back down.

One test was left disabled due to a crash in the legalizer.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D97559
The file was modifiedllvm/lib/Target/RISCV/RISCVISelLowering.cpp
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/insert-subvector.ll
Commit d84440ec919019ac446241db72cfd905c6ac9dfa by sguelton
Use the default seed value for djb hash for StringMap

See original comment in 560ce2c70fb1fe8e4b9b5e39c54e494a50373ba8
Baiscally the default seed value results in less collision, but changes the
iteration order, which matters for a few test cases.

Differential Revision: https://reviews.llvm.org/D97396
The file was modifiedllvm/test/DebugInfo/X86/debug-pubtables-dwarf64.ll
The file was modifiedllvm/test/tools/llvm-dwarfdump/X86/section_sizes_elf.test
The file was modifiedllvm/lib/Support/StringMap.cpp
The file was modifiedllvm/test/tools/llvm-dwarfdump/X86/section_sizes_macho.test
The file was modifiedllvm/test/tools/llvm-dwarfdump/X86/statistics.ll
The file was modifiedllvm/test/DebugInfo/Generic/accel-table-hash-collisions.ll
The file was modifiedllvm/test/DebugInfo/Generic/debug-names-hash-collisions.ll
The file was modifiedllvm/test/DebugInfo/X86/gnu-public-names.ll
Commit 7d6e4ed1558fefae98cde41d4139131201bd2416 by david.green
[AArch64] Adjust dot produce tests. NFC

This regenerates and splits out the dotproduce tests, adding a few extra
tests for upcoming changes.
The file was modifiedllvm/test/CodeGen/AArch64/neon-dot-product.ll
The file was addedllvm/test/CodeGen/AArch64/neon-dotpattern.ll
The file was addedllvm/test/CodeGen/AArch64/neon-dotreduce.ll
Commit 7abf7dd5efe257b5e7ff72199aa513e7a513b742 by david.green
[AArch64] Add combine for add(udot(0, x, y), z) -> udot(z, x, y).

Given a zero input for a udot, an add can be folded in to take the place
of the input, using thte addition that the instruction naturally
performs.

Differential Revision: https://reviews.llvm.org/D97188
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.cpp
The file was modifiedllvm/test/CodeGen/AArch64/neon-dotreduce.ll
The file was modifiedllvm/test/CodeGen/AArch64/neon-dot-product.ll
Commit 7b319df29bf4ebe690ca0c41761e46d8b0081293 by sguelton
Revert "Use the default seed value for djb hash for StringMap"

This reverts commit d84440ec919019ac446241db72cfd905c6ac9dfa.

It breaks (at least) lldb and lld validation

https://lab.llvm.org/buildbot/#/builders/68/builds/7837
https://lab.llvm.org/buildbot/#/builders/36/builds/5495
The file was modifiedllvm/test/DebugInfo/X86/debug-pubtables-dwarf64.ll
The file was modifiedllvm/test/tools/llvm-dwarfdump/X86/section_sizes_elf.test
The file was modifiedllvm/test/DebugInfo/Generic/debug-names-hash-collisions.ll
The file was modifiedllvm/test/DebugInfo/Generic/accel-table-hash-collisions.ll
The file was modifiedllvm/test/tools/llvm-dwarfdump/X86/section_sizes_macho.test
The file was modifiedllvm/test/DebugInfo/X86/gnu-public-names.ll
The file was modifiedllvm/test/tools/llvm-dwarfdump/X86/statistics.ll
The file was modifiedllvm/lib/Support/StringMap.cpp
Commit 2f0b4db5ea52148a91c57fcb192856bab567de5a by jpienaar
[mlir] Add convenience grouping for tensor type inference

For ops that produces tensor types and implement the shaped type component interface, the type inference interface can be used. Create a grouping of these together to make it easier to specify (it cannot be added into a list of traits, but must rather be appended/concated to one as it isn't a trait but a list of traits).

Differential Revision: https://reviews.llvm.org/D97636
The file was modifiedmlir/include/mlir/Interfaces/InferTypeOpInterface.td
The file was modifiedmlir/test/lib/Dialect/Test/TestOps.td
Commit f870c551f090b6edc83892efd68e9e96ed5c19a8 by sander.desmalen
[AArch64] NFC: Cleanup some SVE cost-model tests.

Moved some of the `sve-getIntrinsicCost-<..>` into a single sve-intrinsics.ll
file, and simplified the tests a bit by bundling all the intrinsics in one
function (instead of testing one intrinsic per function). That makes it easier
to see the cost of the intrinsics.
The file was removedllvm/test/Analysis/CostModel/AArch64/sve-getIntrinsicInstrCost-vector-reduce.ll
The file was removedllvm/test/Analysis/CostModel/AArch64/sve-getIntrinsicInstrCost-vector-reverse.ll
The file was removedllvm/test/Analysis/CostModel/AArch64/sve-getIntrinsicInstrCost-scatter.ll
The file was addedllvm/test/Analysis/CostModel/AArch64/sve-gather.ll
The file was removedllvm/test/Analysis/CostModel/AArch64/sve-getIntrinsicInstrCost-gather.ll
The file was removedllvm/test/Analysis/CostModel/AArch64/sve-getIntrinsicInstrCost-cctz-ctlz.ll
The file was addedllvm/test/Analysis/CostModel/AArch64/sve-intrinsics.ll
The file was removedllvm/test/Analysis/CostModel/AArch64/sve-getIntrinsicInstrCost-vec-insert-extract.ll
The file was addedllvm/test/Analysis/CostModel/AArch64/sve-scatter.ll
Commit b4bfe29415ba9524f56d4ea57eb3adbdb4a82fc9 by Matthew.Arsenault
AArch64/GlobalISel: Fix using wrong calling convention for calls

This was reusing the parent function calling convention instead of the
callee. I'm not sure if there's a case where there's an observable
difference.

I previously missed this in b72a23650f573299aec30846fb844c3558921fb8
The file was modifiedllvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp
Commit 6c260d3bc059b29aa62b91378be4afa2d98d8067 by Matthew.Arsenault
GlobalISel: Move splitToValueTypes to generic code

I copied the nearly identical function from AArch64 into AMDGPU, so
fix this duplication.

Mips and X86 have their own more exotic versions which should be
removed. However replacing those is better left for a separate patch
since it requires other changes to avoid regressions.
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
The file was modifiedllvm/lib/Target/AArch64/GISel/AArch64CallLowering.h
The file was modifiedllvm/lib/Target/Mips/MipsCallLowering.cpp
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUCallLowering.h
The file was modifiedllvm/lib/Target/X86/X86CallLowering.cpp
The file was modifiedllvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp
The file was modifiedllvm/lib/Target/ARM/ARMCallLowering.cpp
The file was modifiedllvm/lib/Target/ARM/ARMCallLowering.h
The file was modifiedllvm/include/llvm/CodeGen/GlobalISel/CallLowering.h
The file was modifiedllvm/lib/CodeGen/GlobalISel/CallLowering.cpp
Commit 361cfdf2284193365f2830008625975f55112428 by Matthew.Arsenault
GlobalISel: Verify G_CONCAT_VECTORS has at least 2 sources
The file was modifiedllvm/lib/CodeGen/MachineVerifier.cpp
The file was modifiedllvm/test/MachineVerifier/test_g_concat_vectors.mir