Commit
8f6c623e874624c1f247f93bf457d5196a84cec6
by david.green[AArch64] Replace AEK_CRYPTO with relevant features in cpu definitions
This replaces AEK_CRYPTO in the AArch64TargetParser definitions, replacing the composite Crypto features with the constituent parts. AEK_CRYPTO is replaced with either AEK_AES | AEK_SHA2 or AEK_AES | AEK_SHA2 | AEK_SHA3 | AEK_SHA4 depending on if the cpu is Arm-v8.4+. This helps get the features correct in some more places like target(cpu=..) attributes.
Otherwise this is hopefully an NFC for -mcpu options but seems like a cleaner design.
Differential Revision: https://reviews.llvm.org/D142548
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 | clang/test/CodeGen/aarch64-targetattr.c (diff) |
 | llvm/include/llvm/TargetParser/AArch64TargetParser.h (diff) |
 | llvm/unittests/TargetParser/TargetParserTest.cpp (diff) |
 | clang/test/Preprocessor/aarch64-target-features.c (diff) |
 | clang/lib/Driver/ToolChains/Arch/AArch64.cpp (diff) |
Commit
055f2f04e658c7dddd1fc261e5e0c0bd136cc2b5
by Felipe de Azevedo Piovezan[mem2reg][debuginfo] Handle op_deref when converting dbg.declare
The conversion of dbg.declare into dbg.values doesn't take into account the DIExpression attached to the intrinsic. In particular, when converting:
``` store %val, ptr %alloca dbg.declare(ptr %alloca, !SomeVar, !DIExpression()) ```
Mem2Reg will try to figure out if `%val` has the size of `!SomeVar`. If it does, then a non-undef dbg.value is inserted:
``` dbg.value(%val, !SomeVar, !DIExpression()) ```
This makes sense: the alloca is _the_ address of the variable. So a store to the alloca is a store to the variable. However, if the expression in the original intrinsic is a `DW_OP_deref`, this logic is not applicable:
``` store ptr %val, ptr %alloca dbg.declare(ptr %alloca, !SomeVar, !DIExpression(DW_OP_deref)) ```
Here, the alloca is *not* the address of the variable. A store to the alloca is *not* a store to the variable. As such, querying whether `%val` has the same size as `!SomeVar` is meaningless.
This patch addresses the issue by: 1. Allowing the conversion when the expression is _only_ a `DW_OP_deref` without any other expressions (see code comment). 2. Checking that the expression does not start with a `DW_OP_deref` before applying the logic that checks whether the value being stored and the variable have the same length.
Differential Revision: https://reviews.llvm.org/D142160
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 | llvm/include/llvm/IR/DebugInfoMetadata.h (diff) |
 | llvm/lib/IR/DebugInfoMetadata.cpp (diff) |
 | llvm/lib/Transforms/Utils/Local.cpp (diff) |
 | llvm/test/Transforms/Mem2Reg/dbg_declare_to_value_conversions.ll |
|
 | libc/cmake/modules/LLVMLibCArchitectures.cmake (diff) |
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 | libc/cmake/modules/LLVMLibCTestRules.cmake (diff) |
 | libc/test/src/math/differential_testing/CMakeLists.txt (diff) |
 | libc/cmake/modules/LLVMLibCObjectRules.cmake (diff) |
 | libc/CMakeLists.txt (diff) |
|
 | libcxx/include/__algorithm/ranges_minmax.h (diff) |
 | libcxx/include/__algorithm/min.h (diff) |
 | libcxx/include/__algorithm/minmax.h (diff) |
 | libcxx/include/__algorithm/ranges_min.h (diff) |
 | libcxx/test/libcxx/algorithms/lifetimebound.verify.cpp |
 | libcxx/include/__algorithm/max.h (diff) |
 | libcxx/include/__algorithm/ranges_max.h (diff) |
 | libcxx/include/module.modulemap.in (diff) |
Commit
09a3aef0f8f4ef7789713b6edb185f4541858aac
by 31459023+hctimRevert "[AIX][BigArchive] Treat the archive is empty if the first child member offset is zero"
This reverts commit 7f0003c19c3a47f484ea9cc929728808b27ace32.
Reason: This broke the ASan buildbot, see the comments in https://reviews.llvm.org/D138986 for more information.
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 | llvm/include/llvm/Object/Archive.h (diff) |
 | llvm/test/Object/archive-big-read-empty-with-freelist.test (diff) |
 | llvm/lib/Object/Archive.cpp (diff) |
 | llvm/test/Object/archive-big-malformed-first-member.test |
|
 | llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp (diff) |
Commit
4e607ec498786039f1edb8f5fb4834311402e07d
by flo[SCCP] Flip range arguments for NSW region check.
This brings the operand order in line with the NUW handling, which was missed out in 72121a20cda4dc91d0ef5548f930.
At the moment this is NFC as we only additions, but it should fix miscompiles with 024115ab14822a recommitted.
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 | llvm/lib/Transforms/Utils/SCCPSolver.cpp (diff) |
Commit
4ce34bb2a9c8c2ae21c4d67f8af9046fe1ca434c
by aeubanks[CGSCC] Add pass which counts the max number of times we visit a function
This will help with finding potential pathological CGSCC cases.
Reviewed By: asbirlea
Differential Revision: https://reviews.llvm.org/D142853
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 | llvm/lib/Passes/PassBuilder.cpp (diff) |
 | llvm/test/Other/count-visits.ll |
 | llvm/lib/Transforms/Utils/CountVisits.cpp |
 | llvm/lib/Passes/PassBuilderPipelines.cpp (diff) |
 | llvm/include/llvm/Transforms/Utils/CountVisits.h |
 | llvm/utils/gn/secondary/llvm/lib/Transforms/Utils/BUILD.gn (diff) |
 | llvm/lib/Passes/PassRegistry.def (diff) |
 | llvm/lib/Transforms/Utils/CMakeLists.txt (diff) |
Commit
cb05c2ffc79eefe74c569263e27fcb5fad167ba3
by aeubanks[LTO] Demangle the function name in DiagnosticInfoDontCall message
Previously, dontcall attribute message on LTO prints the mangled function name.
Fixes https://github.com/llvm/llvm-project/issues/58933
Reviewed By: aeubanks
Differential Revision: https://reviews.llvm.org/D142844
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 | llvm/lib/IR/DiagnosticInfo.cpp (diff) |
 | llvm/test/CodeGen/X86/attr-dontcall.ll (diff) |
|
 | openmp/libomptarget/plugins/cuda/src/rtl.cpp (diff) |
Commit
52c28d7cf9018f3558268217f6cf91271eb4ac39
by arsenm2clang/OpenCL: Don't use a Function for the block type
The AMDGPU value for this is not really a function. Currently we're emitting IR that isn't true to what will eventually be emitted.
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 | clang/lib/CodeGen/CGBuiltin.cpp (diff) |
 | clang/lib/CodeGen/CGOpenCLRuntime.cpp (diff) |
 | clang/lib/CodeGen/TargetInfo.cpp (diff) |
 | clang/lib/CodeGen/TargetInfo.h (diff) |
 | clang/lib/CodeGen/CGOpenCLRuntime.h (diff) |
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 | clang/test/CodeGenOpenCL/amdgpu-enqueue-kernel.cl (diff) |
 | clang/test/CodeGenOpenCL/cl20-device-side-enqueue.cl (diff) |
 | clang/lib/CodeGen/TargetInfo.cpp (diff) |
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 | clang/test/CodeGenOpenCL/amdgpu-enqueue-kernel.cl (diff) |
Commit
647925648a0fde06b5b44086843f0d8f164a71df
by arsenm2clang/OpenCL: Apply default attributes to enqueued blocks
This was missing important environment context, like denormal-fp-math and target-features. Curiously this seems to be losing nounwind. Note this only fixes the actual invoke kernel. The invoke function is already setting the default attribute set for internal functions. However that is still buggy since it's not applying any use function attributes (it's also missing uniform-work-group-size).
There seem to be too many different functions for setting attributes with inconsistent behavior. The Function overload of addDefaultFunctionAttributes seems to miss the target-cpu and target-features. The AttrBuilder one seems to miss optnone (but that seems to be disallowed on blocks anyway). Neither one calls setTargetAttributes, when it probably should. uniform-work-group-size is also set through AMDGPU code when it should be emitting generically as a language property.
I also noticed update_cc_test_checks for attributes seem to not connect the captured attribute variables to the attributes at the end (although I think the numbers happen to work out correctly).
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 | clang/test/CodeGenOpenCL/amdgpu-enqueue-kernel.cl (diff) |
 | clang/lib/CodeGen/TargetInfo.cpp (diff) |
 | clang/test/CodeGenOpenCL/cl20-device-side-enqueue.cl (diff) |
 | clang/test/CodeGenOpenCL/cl20-device-side-enqueue-attributes.cl |
Commit
76d7a6ad13be601bd93e7c5fa9988326b4e05b6e
by aeubanksRevert "[LTO] Demangle the function name in DiagnosticInfoDontCall message"
This reverts commit cb05c2ffc79eefe74c569263e27fcb5fad167ba3.
Breaks https://lab.llvm.org/buildbot/#/builders/121/builds/27524/steps/4/logs/stdio
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 | llvm/lib/IR/DiagnosticInfo.cpp (diff) |
 | llvm/test/CodeGen/X86/attr-dontcall.ll (diff) |
Commit
155e0cf5dc2ffba0a509b1dea25fb4c31eeb367e
by aeubanksReland [LTO] Demangle the function name in DiagnosticInfoDontCall message
Previously, dontcall attribute message on LTO prints the mangled function name.
Fixes https://github.com/llvm/llvm-project/issues/58933
Relanded with proper IR -> Demangle dependency.
Reviewed By: aeubanks
Differential Revision: https://reviews.llvm.org/D142844
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 | llvm/test/CodeGen/X86/attr-dontcall.ll (diff) |
 | llvm/lib/IR/CMakeLists.txt (diff) |
 | llvm/lib/IR/DiagnosticInfo.cpp (diff) |
Commit
6d9b0759c24e93c2ef1f10ca59c7317c7b440468
by abrachet[MC] Allow .pushsection between .cfi_startproc/.cfi_endproc
This follows the behavior of gnu assemblers. This is useful when writing inline assembly.
Differential Revision: https://reviews.llvm.org/D141893
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 | llvm/lib/MC/MCStreamer.cpp (diff) |
 | llvm/include/llvm/MC/MCStreamer.h (diff) |
 | llvm/test/MC/ELF/cfi-startproc-pushsection.s |
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 | llvm/test/Transforms/SCCP/sub-nuw-nsw-flags.ll |
Commit
17ce615c781f854b6247ea4995bd50f967d1b699
by arsenm2AMDGPU: Fix null dereference in getInstructionUniformity
This was failing when it couldn't find an allocatable class for special physical register inputs (like $mode), which are all scalars.
This avoids numerous test failures when regbankselect is updated to use uniformity analysis.
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 | llvm/lib/Target/AMDGPU/SIInstrInfo.cpp (diff) |
Commit
490e348e67945a4a7e118709579f17b2c96b40bd
by arsenm2AMDGPU: Partially fix machine uniformity for inline asm
This was assuming virtual registers only, and asserting on physical. This was also ignoring AGPRs, and only considering VGPRs.
Reporting the instruction as uniform or not is conceptually wrong, this should be reported per-operand. An inline asm statement could include uniform and non-uniform components. This should report purely for the register defs and ignore the uses.
Fixes asserting on most of the inline asm tests when uniformity analysis is used.
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 | llvm/include/llvm/CodeGen/RegisterBankInfo.h (diff) |
 | llvm/lib/Target/AMDGPU/GCNSubtarget.h (diff) |
 | llvm/lib/Target/AMDGPU/SIInstrInfo.cpp (diff) |
 | llvm/lib/CodeGen/RegisterBankInfo.cpp (diff) |
Commit
40025761564bae5b62c38745ed6edc2667419591
by arsenm2AMDGPU/GlobalISel: Partially fix getGenericInstructionUniformity
This was broken for the common case of instructions which are uniform if their inputs are uniform. This is broken for control flow intrinsics since the API currently does not express which result operand is in question.
This generates failures in just about every intrinsic test when uniformity analysis is performed without this.
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 | llvm/lib/Target/AMDGPU/SIInstrInfo.cpp (diff) |
|
 | clang-tools-extra/clang-tidy/modernize/UseEmplaceCheck.cpp (diff) |
 | clang-tools-extra/test/clang-tidy/checkers/modernize/use-emplace.cpp (diff) |
|
 | clang/docs/LanguageExtensions.rst (diff) |
Commit
3b9606b5cbf6651556158b7162d288c244d178e9
by hansRevert "[LSAN][HWASAN] Run LSAN tests with HWASAN enabled"
This broke the sanitizer tests on Mac, see e.g. https://green.lab.llvm.org/green/job/clang-stage1-RA/32739/ and comment on the code review.
> A lot of tests are disabled by using UNSUPPORTED. The plan is to remove UNSUPPORTED for tests that are fixed. > > Reviewed By: vitalybuka > > Differential Revision: https://reviews.llvm.org/D142676
This reverts commit f9a01630988716f1b52afe6727f34fe86c07c58a. and follow-up commit bf47ffaa76fbda1ba96d41ee2681e45d2445be1e (https://reviews.llvm.org/D142812).
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 | compiler-rt/test/lsan/TestCases/Linux/log-path_test.cpp (diff) |
 | compiler-rt/test/lsan/TestCases/many_tls_keys_thread.cpp (diff) |
 | compiler-rt/test/lsan/TestCases/use_globals_uninitialized.cpp (diff) |
 | compiler-rt/test/lsan/TestCases/use_stacks_threaded.cpp (diff) |
 | compiler-rt/test/lsan/TestCases/use_stacks.cpp (diff) |
 | compiler-rt/test/lsan/TestCases/Linux/libdl_deadlock.cpp (diff) |
 | compiler-rt/test/lsan/TestCases/disabler.c (diff) |
 | compiler-rt/test/lsan/TestCases/swapcontext.cpp (diff) |
 | compiler-rt/test/lsan/TestCases/use_globals_initialized.cpp (diff) |
 | compiler-rt/test/lsan/TestCases/Linux/use_tls_pthread_specific_dynamic.cpp (diff) |
 | compiler-rt/test/lsan/TestCases/recoverable_leak_check.cpp (diff) |
 | compiler-rt/test/lsan/TestCases/malloc_zero.c (diff) |
 | compiler-rt/test/lsan/TestCases/register_root_region.cpp (diff) |
 | compiler-rt/test/lsan/TestCases/ignore_object.c (diff) |
 | compiler-rt/test/lsan/TestCases/leak_check_at_exit.cpp (diff) |
 | compiler-rt/test/lsan/TestCases/suppressions_default.cpp (diff) |
 | compiler-rt/test/lsan/TestCases/use_after_return.cpp (diff) |
 | compiler-rt/test/lsan/TestCases/suppressions_file.cpp (diff) |
 | compiler-rt/test/lsan/TestCases/Linux/guard-page.c (diff) |
 | compiler-rt/test/lsan/TestCases/Linux/disabler_in_tsd_destructor.c (diff) |
 | compiler-rt/test/lsan/TestCases/Linux/fork_threaded.cpp (diff) |
 | compiler-rt/test/lsan/TestCases/realloc_too_big.c (diff) |
 | compiler-rt/test/lsan/lit.common.cfg.py (diff) |
 | compiler-rt/test/lsan/TestCases/Linux/use_tls_static.cpp (diff) |
 | compiler-rt/test/lsan/TestCases/use_registers_extra.cpp (diff) |
 | compiler-rt/test/lsan/TestCases/Linux/use_tls_pthread_specific_static.cpp (diff) |
 | compiler-rt/test/lsan/TestCases/high_allocator_contention.cpp (diff) |
 | compiler-rt/test/lsan/TestCases/link_turned_off.cpp (diff) |
 | compiler-rt/test/lsan/TestCases/many_tls_keys_pthread.cpp (diff) |
 | compiler-rt/test/lsan/TestCases/pointer_to_self.cpp (diff) |
 | compiler-rt/test/lsan/TestCases/use_unaligned.cpp (diff) |
 | compiler-rt/test/lsan/CMakeLists.txt (diff) |
 | compiler-rt/test/lsan/TestCases/Linux/cleanup_in_tsd_destructor.c (diff) |
 | compiler-rt/test/lsan/TestCases/do_leak_check_override.cpp (diff) |
 | compiler-rt/test/lsan/TestCases/use_registers.cpp (diff) |
 | compiler-rt/test/lsan/TestCases/default_options.cpp (diff) |
|
 | llvm/test/Other/count-visits.ll (diff) |
Commit
7d10213317c18e1d24753e5532d2b037db2d2c5c
by floRecommit "[SCCP] Support NUW/NSW inference for all overflowing binary operators."
This reverts commit 43acb61a08fffada31fb2e20e45fcc8492ef76b9.
Recommit the patch after fixing the issue causing the revert in 4e607ec4987. Extra tests have been added in 5c6cb61ad416a544.
Original commit message:
Extend the NUW/NSW inference logic add in 72121a20cd and cdeaf5f28c3dc to all overflowing binary operators.
Reviewed By: nikic
Differential Revision: https://reviews.llvm.org/D142721
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 | llvm/lib/Transforms/Utils/SCCPSolver.cpp (diff) |
 | llvm/test/Transforms/SCCP/sub-nuw-nsw-flags.ll (diff) |
 | llvm/test/Transforms/SCCP/ub-shift.ll (diff) |
 | llvm/test/Transforms/SCCP/widening.ll (diff) |
 | llvm/test/Transforms/SCCP/ip-constant-ranges.ll (diff) |
 | llvm/test/Transforms/SCCP/ip-ranges-binaryops.ll (diff) |
Commit
e9c49901a43f5b16c3df416460b7e4dbdd24ce03
by arsenm2AMDGPU/GlobalISel: Add stub custom regbankselect pass
Uniformity analysis needs to be the fundamental basis for regbank decisions. The considerations of the default pass are secondary, but potentially useful for some edge cases (e.g. selecting AGPRs when arbitrary loads and stores can directly use them). This needs to be a separate pass since it requires new analysis dependencies.
Boilerplate to subclass the existing pass which does nothing different.
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 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fsub.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ballot.i64.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomic-cmpxchg.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mul.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgpu-ffbh-u32.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgpu-wave-address.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-select.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.div.fmas.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.gws.init.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.mfma.gfx90a.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uaddo.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn-exp.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-min.mir (diff) |
 | llvm/lib/Target/AMDGPU/AMDGPURegBankSelect.cpp |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.fmul.legacy.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fcanonicalize.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.mfma.gfx940.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ctlz-zero-undef.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-smax.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.append.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.kill.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.p1.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sext.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ubfx.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ssube.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uadde.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.lds.param.load.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-umin.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.image.sample.1d.ll (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fabs.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-insert.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wqm.demote.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-brcond.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-copy.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.sendmsg.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uniform-load-noclobber.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.sendmsghalt.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-build-vector.mir (diff) |
 | llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-frame-index.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-smin.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sbfx.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-assert-align.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-concat-vector.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptoui.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.mov.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-reg-sequence.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.lds.direct.load.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-zext.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.gws.sema.v.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-or.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-add.s32.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn-s-buffer-load.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.ordered.swap.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.kernarg.segment.ptr.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-bitreverse.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-umin.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-unmerge-values.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptosi.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.update.dpp.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uitofp.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.cvt.pkrtz.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.getreg.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-insert-vector-elt.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.raw.buffer.load.ll (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.consume.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fshr.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-and.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-umulh.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fceil.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.getpc.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.icmp.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-trunc.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.bpermute.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-add.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-zextload.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-or.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-add.v2s16.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.readlane.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-implicit-def.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgpu-ffbl-b32.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-bitcast.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-add.s16.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-cttz-zero-undef.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.live.mask.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.fcmp.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-split-scalar-load-metadata.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fsqrt.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptrtoint.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sadde.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.readfirstlane.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-inttoptr.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.get.waveid.in.workgroup.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-umax.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptrmask.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ps.live.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-shl.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fexp2.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wqm.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sextload.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.div.scale.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fmul.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-widen-scalar-loads.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.memrealtime.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-icmp.s16.mir (diff) |
 | llvm/lib/Target/AMDGPU/CMakeLists.txt (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.ordered.add.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-smulh.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sub.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.writelane.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.mfma.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-and.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-illegal-copy.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fpext.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-block-addr.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-default.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sext-inreg.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-xchg.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-extract-vector-elt.mir (diff) |
 | llvm/lib/Target/AMDGPU/AMDGPURegBankSelect.h |
 | llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.image.load.1d.ll (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.p1.f16.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-icmp.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-max.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.else.64.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.buffer.store.ll (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-merge-values.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sitofp.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-waterfall-agpr.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wwm.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-usubo.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-assert-zext.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-umax.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-phi.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-constant.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fma.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fadd.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-lshr.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.swizzle.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-load.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-and-s1.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-flog2.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fcmp.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-frint.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.class.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-phi-s1.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.buffer.load.ll (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ctpop.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.p2.f16.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-intrinsic-trunc.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-usube.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.buffer.load.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptrunc.mir (diff) |
 | llvm/include/llvm/CodeGen/GlobalISel/RegBankSelect.h (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn-exp-compr.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.memtime.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-dyn-stackalloc.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ashr.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.groupstaticsize.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-xor.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-anyext.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-freeze.mir (diff) |
 | llvm/lib/Target/AMDGPU/AMDGPU.h (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.else.32.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.buffer.load.ll (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.p2.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-fadd.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fneg.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-bswap.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptr-add.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mad_64_32.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.permute.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wqm.vote.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-extract.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-xor.mir (diff) |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-sub.mir (diff) |
|
 | llvm/test/Analysis/DivergenceAnalysis/AMDGPU/MIR/always-uniform-gmir.mir (diff) |
Commit
d558a70abf2624bf0b26fa8cd506277214fea197
by craig.topper[RISCV] Use custom operand parsing for FenceArg.
Rather than parsing a symbol and checking its name, look for an identifier during parsing.
I've also handled the 0 immediate during parsing, though we could let that go through the normal immediate parsing if we need to support expressions that evaluate to 0. We don't have tests for that currently.
Reviewed By: asb, frasercrmck
Differential Revision: https://reviews.llvm.org/D142865
|
 | llvm/lib/Target/RISCV/RISCVInstrInfo.td (diff) |
 | llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp (diff) |
Commit
0b4224011aecb98facd406dc68dacecff40109e8
by minyihh[mlir][AsmPrinter] Gracefully handle empty symbol
The GenericOp printer should support malformed IR without crashing
GitHub issue #59529
Differential Revision: https://reviews.llvm.org/D142818
|
 | mlir/lib/IR/AsmPrinter.cpp (diff) |
Commit
c9986f8263980ce6bc9ef87d96d97911eaad547d
by minyihh[mlir][Pass] Handle spaces in pipeline strings
An user might want to add extra spaces for better readability, e.g: ``` mypm = pm.PassManager.parse(f"""builtin.module( mypass1, func.func(mypass2,mypass3) )""") ``` GitHub issue #59151
The parser was not taking into account the possibility of spaces after `)`or `}`
Differential Revision: https://reviews.llvm.org/D142821
|
 | mlir/test/Pass/pipeline-parsing.mlir (diff) |
 | mlir/test/python/pass_manager.py (diff) |
 | mlir/lib/Pass/PassRegistry.cpp (diff) |
Commit
e1cebe9ed12a46282fb6cc9fa9e172b04e5474ef
by spatel[InstCombine] add tests for icmp-of-and-of-select-of-constants; NFC
This overlaps with the tests proposed in D134064 and providing coverage for D133919, but it is both limited in scope and more comprehensive because there are many potential ways to transform these kinds of patterns.
|
 | llvm/test/Transforms/InstCombine/icmp-select.ll (diff) |
Commit
98855059674cf1b6b415f8c543f2a923771fed27
by spatel[InstCombine] reduce icmp_eq0-of-and-of-select-of-constants
This is the most basic patch to handle fixing issue #57666.
D133919 proposes to handle much more than this in a single patch, but I've used 10 regression tests just to make sure this part is doing what I expected and nothing more, and it already shows even more potential TODO items.
The more general proofs from D133919 are correct, but I want to enable this in smaller steps to reduce risk: https://alive2.llvm.org/ce/z/RrVEyX
Differential Revision: https://reviews.llvm.org/D142847
|
 | llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp (diff) |
 | llvm/test/Transforms/InstCombine/icmp-select.ll (diff) |
|
 | libcxx/include/cmath (diff) |
 | libcxx/include/__type_traits/promote.h (diff) |
Commit
950487bddf1922c87559339a24cf5a77ad59c363
by hoy[Pseudo Probe] Do not instrument EH blocks.
This change avoids inserting probes to EH blocks. Pseudo probe can prevent block merging when probes in the blocks look different. This has a chained effect to passes incurring exponential IR growth (such as jump threading) and as a consequence the compilation may time out. Not inserting probes to EH blocks could mitigate the issue. Another benefit is that both IR size and binary size are smaller. Since EH blocks are usually cold, the change should have minimal impact to profile quality.
Testing:
Out of two internal large benchmarks, no perf impact seen. 1% size savings to both the `text` and the `pseudo_probe` section.
Reviewed By: wenlei
Differential Revision: https://reviews.llvm.org/D142747
|
 | llvm/test/Transforms/SampleProfile/pseudo-probe-eh.ll |
 | llvm/lib/Transforms/IPO/SampleProfileProbe.cpp (diff) |
 | llvm/lib/CodeGen/MachineFunctionSplitter.cpp (diff) |
 | llvm/include/llvm/Analysis/EHUtils.h |
 | llvm/include/llvm/CodeGen/MachineBasicBlock.h (diff) |
 | llvm/include/llvm/CodeGen/MachineSSAContext.h (diff) |
Commit
2bd8aeea7e7d885fbf6c70c0e181b1e8e6b808a5
by Shafik Yaghmour[Clang] Fix unconditional access to Attr pointer when checking if _Nullable is applicable to a type
In TransformAttributedType(...) when checking if _Nullable can be applied to a type it dereferences TL.getAttr() unconditionally which we can see from the code earlier in the function is not correct since it is expected to be nullptr in some cases.
It looks like the correct course of action is to use TL.getModifiedLoc() over TL.getAttr()->getLocation() in the case that TL.getAttr() returns a nullptr.
Fixes: https://github.com/llvm/llvm-project/issues/60344
Differential Revision: https://reviews.llvm.org/D142799
|
 | clang/docs/ReleaseNotes.rst (diff) |
 | clang/lib/Sema/TreeTransform.h (diff) |
 | clang/test/SemaCXX/nullability.cpp (diff) |
Commit
226c444b3882e085daf7c9f8e284cfad44838e32
by Louis Dionne[libc++] Remove <experimental/coroutine>
We've been shipping <coroutine> since LLVM 14, so LLVM 17 won't ship the <experimental/coroutine> header per our policy for removing TSes.
Differential Revision: https://reviews.llvm.org/D108697
|
 | libcxx/test/libcxx/assertions/headers_declare_verbose_abort.sh.cpp (diff) |
 | libcxx/test/std/experimental/language.support/support.coroutines/coroutine.trivial.awaitables/suspend_always.pass.cpp |
 | libcxx/test/std/experimental/language.support/support.coroutines/coroutine.handle/coroutine.handle.con/construct.pass.cpp |
 | libcxx/utils/libcxx/test/features.py (diff) |
 | libcxx/test/std/experimental/language.support/support.coroutines/end.to.end/expected.pass.cpp |
 | libcxx/test/std/experimental/language.support/support.coroutines/end.to.end/multishot_func.pass.cpp |
 | libcxx/test/std/experimental/language.support/support.coroutines/end.to.end/bool_await_suspend.pass.cpp |
 | libcxx/test/libcxx/transitive_includes/cxx2b.csv (diff) |
 | libcxx/test/std/experimental/language.support/support.coroutines/coroutine.handle/coroutine.handle.resumption/destroy.pass.cpp |
 | libcxx/include/experimental/coroutine |
 | libcxx/test/std/experimental/language.support/support.coroutines/coroutine.handle/coroutine.handle.compare/less_comp.pass.cpp |
 | libcxx/test/std/experimental/language.support/support.coroutines/end.to.end/oneshot_func.pass.cpp |
 | libcxx/test/std/experimental/language.support/support.coroutines/coroutine.handle/coroutine.handle.completion/done.pass.cpp |
 | libcxx/test/std/experimental/language.support/support.coroutines/coroutine.handle/coroutine.handle.prom/promise.pass.cpp |
 | libcxx/test/std/experimental/language.support/support.coroutines/coroutine.handle/coroutine.handle.export/from_address.fail.cpp |
 | libcxx/test/std/experimental/language.support/support.coroutines/end.to.end/go.pass.cpp |
 | libcxx/test/libcxx/clang_tidy.sh.cpp (diff) |
 | libcxx/test/libcxx/experimental/language.support/support.coroutines/version.pass.cpp |
 | libcxx/test/libcxx/nasty_macros.compile.pass.cpp (diff) |
 | libcxx/utils/libcxx/test/format.py (diff) |
 | libcxx/test/libcxx/transitive_includes/cxx17.csv (diff) |
 | libcxx/test/libcxx/min_max_macros.compile.pass.cpp (diff) |
 | libcxx/include/experimental/__config (diff) |
 | libcxx/utils/generate_header_tests.py (diff) |
 | libcxx/test/libcxx/experimental/language.support/support.coroutines/dialect_support.pass.cpp |
 | libcxx/test/libcxx/transitive_includes/cxx20.csv (diff) |
 | libcxx/docs/ReleaseNotes.rst (diff) |
 | libcxx/test/libcxx/modules_include.sh.cpp (diff) |
 | libcxx/test/std/experimental/language.support/support.coroutines/coroutine.handle/void_handle.pass.cpp |
 | libcxx/test/libcxx/no_assert_include.compile.pass.cpp (diff) |
 | libcxx/test/libcxx/transitive_includes/cxx14.csv (diff) |
 | libcxx/test/std/experimental/language.support/support.coroutines/coroutine.handle/coroutine.handle.resumption/resume.pass.cpp |
 | libcxx/CMakeLists.txt (diff) |
 | libcxx/test/std/experimental/language.support/support.coroutines/coroutine.handle/coroutine.handle.noop/noop_coroutine.pass.cpp |
 | libcxx/test/libcxx/transitive_includes/cxx11.csv (diff) |
 | libcxx/test/std/experimental/language.support/support.coroutines/coroutine.handle/coroutine.handle.export/address.pass.cpp |
 | libcxx/test/std/experimental/language.support/support.coroutines/includes.pass.cpp |
 | libcxx/test/std/experimental/language.support/support.coroutines/coroutine.handle/coroutine.handle.hash/hash.pass.cpp |
 | libcxx/test/libcxx/double_include.sh.cpp (diff) |
 | libcxx/test/libcxx/transitive_includes.sh.cpp (diff) |
 | libcxx/test/std/experimental/language.support/support.coroutines/coroutine.handle/coroutine.handle.export/from_address.pass.cpp |
 | libcxx/test/std/experimental/language.support/support.coroutines/end.to.end/await_result.pass.cpp |
 | libcxx/test/std/experimental/language.support/support.coroutines/lit.local.cfg |
 | libcxx/test/std/experimental/language.support/support.coroutines/end.to.end/fullexpr-dtor.pass.cpp |
 | libcxx/include/module.modulemap.in (diff) |
 | libcxx/test/std/experimental/language.support/support.coroutines/coroutine.traits/promise_type.pass.cpp |
 | libcxx/test/std/experimental/language.support/support.coroutines/coroutine.trivial.awaitables/suspend_never.pass.cpp |
 | libcxx/test/std/experimental/language.support/support.coroutines/coroutine.handle/coroutine.handle.capacity/operator_bool.pass.cpp |
 | libcxx/test/std/experimental/language.support/support.coroutines/coroutine.handle/coroutine.handle.con/assign.pass.cpp |
 | libcxx/include/CMakeLists.txt (diff) |
 | libcxx/test/std/experimental/language.support/support.coroutines/end.to.end/generator.pass.cpp |
 | libcxx/test/std/experimental/language.support/support.coroutines/coroutine.handle/coroutine.handle.compare/equal_comp.pass.cpp |
 | libcxx/test/libcxx/transitive_includes/cxx03.csv (diff) |
|
 | compiler-rt/test/CMakeLists.txt (diff) |
Commit
0a51eeda1ef43d0f9a73ed2ac15f602262943ea1
by dthorn[NFC] [llvm-cov] Remove unnecessary logic from llvm-cov debuginfod.
Indexed profiles already have a sorted and uniqued binary ID list, and due to this, duplicates are harmless in the list of binary IDs found, since it's set_differenced from the list in the indexed profile.
Differential Revision: https://reviews.llvm.org/D136702
|
 | llvm/lib/ProfileData/Coverage/CoverageMapping.cpp (diff) |
Commit
8b1cd3749eb6872b3a71cee4fe65ae3b9de4dc93
by Jonas Devlieghere[lldb] Use lldbassert in BuildObjCObjectPointerType
This assert is only checked in Debug builds but ignored in all other builds. This replaces this code with lldbassert which should print a warning to the user in release builds and actually asserts in debug builds.
Differential revision: https://reviews.llvm.org/D76697
|
 | lldb/source/Plugins/LanguageRuntime/ObjC/AppleObjCRuntime/AppleObjCTypeEncodingParser.cpp (diff) |
Commit
11066449d49e20f18f46757df07455c6abcedcf1
by daltenty[AIX][CMake] Use top-level tools in llvm_ExternalProject_Add
This change force us to use the top-level CMake's detected tools. We need to do this as a temporary workaround as when using CMake versions >= 3.22 we'll pickup the built llvm-ranlib by default if it's in the path (which it is when doing a sub build via llvm_ExternalProject_Add for the runtimes).
llvm-ranlib runs into problems on AIX due to missing 64-bit functionality to be added by https://reviews.llvm.org/D142479 and https://reviews.llvm.org/D142660. Once those patches land, this can be reverted.
Differential Revision: https://reviews.llvm.org/D142727
|
 | llvm/cmake/modules/LLVMExternalProjectUtils.cmake (diff) |
|
 | utils/bazel/llvm-project-overlay/llvm/BUILD.bazel (diff) |
Commit
8520b0fc59c010675afbfdae71d48893afc7b68b
by medismail.bennani[lldb/swig] Remove deprecated flags for generating bindings
This patch conditionaly removes the `-py3` swig flag that was used to generate python3 bindings, since it's unsued since SWIG 4.1.0.
``` Deprecated command line option: -py3. Ignored, this option is no longer supported ```
This also removes the `-shadow` flag that have been deprecated since 2002.
Differential Revision: https://reviews.llvm.org/D142245
Signed-off-by: Med Ismail Bennani <medismail.bennani@gmail.com>
|
 | lldb/bindings/python/CMakeLists.txt (diff) |
Commit
3301f6e1355b295386ceda654424eddbc30d7784
by kstoimenov[LSAN][HWASAN] Run LSAN tests with HWASAN enabled
A lot of tests are disabled by using UNSUPPORTED. The plan is to remove UNSUPPORTED for tests that are fixed.
Reviewed By: vitalybuka
Differential Revision: https://reviews.llvm.org/D142676
|
 | compiler-rt/test/lsan/TestCases/many_tls_keys_thread.cpp (diff) |
 | compiler-rt/test/lsan/TestCases/default_options.cpp (diff) |
 | compiler-rt/test/lsan/TestCases/swapcontext.cpp (diff) |
 | compiler-rt/test/lsan/TestCases/Linux/log-path_test.cpp (diff) |
 | compiler-rt/test/lsan/TestCases/use_globals_initialized.cpp (diff) |
 | compiler-rt/test/lsan/TestCases/Linux/use_tls_pthread_specific_static.cpp (diff) |
 | compiler-rt/test/lsan/TestCases/link_turned_off.cpp (diff) |
 | compiler-rt/test/lsan/TestCases/Linux/use_tls_static.cpp (diff) |
 | compiler-rt/test/lsan/TestCases/register_root_region.cpp (diff) |
 | compiler-rt/test/lsan/TestCases/suppressions_default.cpp (diff) |
 | compiler-rt/test/lsan/TestCases/suppressions_file.cpp (diff) |
 | compiler-rt/test/lsan/TestCases/high_allocator_contention.cpp (diff) |
 | compiler-rt/test/lsan/TestCases/Linux/use_tls_pthread_specific_dynamic.cpp (diff) |
 | compiler-rt/test/lsan/TestCases/use_stacks_threaded.cpp (diff) |
 | compiler-rt/test/lsan/TestCases/use_registers.cpp (diff) |
 | compiler-rt/test/lsan/TestCases/use_globals_uninitialized.cpp (diff) |
 | compiler-rt/test/lsan/lit.common.cfg.py (diff) |
 | compiler-rt/test/lsan/TestCases/realloc_too_big.c (diff) |
 | compiler-rt/test/lsan/TestCases/use_after_return.cpp (diff) |
 | compiler-rt/test/lsan/TestCases/many_tls_keys_pthread.cpp (diff) |
 | compiler-rt/test/lsan/TestCases/Linux/cleanup_in_tsd_destructor.c (diff) |
 | compiler-rt/test/lsan/TestCases/do_leak_check_override.cpp (diff) |
 | compiler-rt/test/lsan/TestCases/malloc_zero.c (diff) |
 | compiler-rt/test/lsan/TestCases/Linux/disabler_in_tsd_destructor.c (diff) |
 | compiler-rt/test/lsan/TestCases/recoverable_leak_check.cpp (diff) |
 | compiler-rt/test/lsan/TestCases/Linux/guard-page.c (diff) |
 | compiler-rt/test/lsan/TestCases/use_stacks.cpp (diff) |
 | compiler-rt/test/lsan/TestCases/Linux/libdl_deadlock.cpp (diff) |
 | compiler-rt/test/lsan/TestCases/disabler.c (diff) |
 | compiler-rt/test/lsan/TestCases/use_unaligned.cpp (diff) |
 | compiler-rt/test/lsan/TestCases/use_registers_extra.cpp (diff) |
 | compiler-rt/test/lsan/TestCases/ignore_object.c (diff) |
 | compiler-rt/test/lsan/TestCases/pointer_to_self.cpp (diff) |
 | compiler-rt/test/lsan/TestCases/Linux/fork_threaded.cpp (diff) |
 | compiler-rt/test/lsan/TestCases/leak_check_at_exit.cpp (diff) |
 | compiler-rt/test/lsan/CMakeLists.txt (diff) |
|
 | flang/test/Driver/target-cpu-features.f90 (diff) |
|
 | llvm/lib/Target/PowerPC/PPCInstrVSX.td (diff) |
 | llvm/test/CodeGen/PowerPC/build-vector-tests.ll (diff) |
Commit
40cef80647cc21b86cbc7c969c7007f9a8f40715
by medismail.bennani[lldb/test] Skip TestStackCoreScriptedProcess if Asan is enabled
This patch skips TestStackCoreScriptedProcess because the test times out when the Address Sanitizer is running.
Signed-off-by: Med Ismail Bennani <medismail.bennani@gmail.com>
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 | lldb/test/API/functionalities/scripted_process/TestStackCoreScriptedProcess.py (diff) |
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 | compiler-rt/lib/hwasan/hwasan.cpp (diff) |
 | compiler-rt/test/lsan/TestCases/default_options.cpp (diff) |