Started 4 mo 25 days ago
Took 3 hr 27 min

Build clang-d423516-ged242b54c9c2-t29347-b29347.tar.gz (May 11, 2022 3:19:16 PM)


No known issues detected

Build Log

  1. [InstCombine] freeze operand in urem expansion (details)
  2. [flang] Fold complex component references (details)
  3. [mlgo] Fix test (details)
  4. [clang][AIX] Don't ignore XCOFF visibility by default (details)
  5. [riscv] Add tests for vsetvli reuse across iterations of a loop (details)
  6. [flang] Fix check for assumed-size arguments to SHAPE() & al. (details)
  7. [gn build] Use llvm-ar when clang_base_path is specified (details)
  8. [riscv] Canonicalize vsetvli (vsetvli avl, vtype1) vtype2 transitionsas reviewed (details)
  9. [RISCV] Add a DAG combine to pre-promote (i32 (and (srl X, Y), 1)) with Zbs on RV64. (details)
  10. [InstCombine] update auto-generated CHECK lines in test file; NFC (details)
  11. [InstCombine] freeze operand in sdiv expansion (details)
  12. [RISCV] Override TargetLowering::shouldProduceAndByConstByHoistingConstFromShiftsLHSOfAnd. (details)
  13. [RISCV] Move implementation of getVLOpNum and getSEWOpNum from RISCVInsertVSETVLI to RISCVBaseInfo.h. NFC (details)
  14. [HLSL] add -D option for dxc mode. (details)
  15. [clang] Fix KEYALL (details)
  16. [RISCV] Add caching to the gather/scatter to strided load/store conversion. (details)
  17. [clang][ppc] Creating Seperate Install Target for PPC htm Headers (details)
  18. [TableGen] Remove the use of global Record state (details)
  19. [TableGen] Refactor TableGenParseFile to no longer use a callback (details)
  20. [test, riscv] Add test illustrating missing handling for fallthrough blocks in 541c9ba (details)
  21. [CodeGenPrepare] Use const reference to avoid unnecessary APInt copy. NFC (details)
  22. [libc++] Add a few more debug wrapper functions (details)
  23. [libc++] Remove __invalidate_all_iterators and replace the uses with std::__debug_db_invalidate_all (details)
  24. [AsmParser] Adopt emitWrongTokenError more, improving QoI (details)
  25. [GVN] Add test case for memdep invalidation bug. (details)
  26. [RISCV] Fold addiw from (add X, (addiw (lui C1, C2))) into load/store address (details)
  27. [RISCV] Enable subregister liveness tracking for RVV. (details)

Started by upstream project relay-lnt-ctmark build number 14546
originally caused by:

This run spent:

  • 3 hr 10 min waiting;
  • 3 hr 27 min build duration;
  • 3 hr 27 min total from scheduled to completion.
Revision: 2b96a257f15dce470fe5b63d8ec46947d03e4e36
  • refs/remotes/origin/main
Revision: ed242b54c9c2aa84a47f66af5b8497d93646b68d
Repository: http://labmaster3.local/git/llvm-project.git
  • detached
Revision: 58c7f0da8dc8be3723643332824b26ef57c0b59f
  • refs/remotes/origin/main
Revision: 11047081ff024bfbda16e35d09c4feb3b0aecd45
  • refs/remotes/origin/main