Changes

Summary

[InstCombine] freeze operand in urem expansion (details)
[flang] Fold complex component references (details)
[mlgo] Fix test (details)
[clang][AIX] Don't ignore XCOFF visibility by default (details)
[riscv] Add tests for vsetvli reuse across iterations of a loop (details)
[flang] Fix check for assumed-size arguments to SHAPE() & al. (details)
[gn build] Use llvm-ar when clang_base_path is specified (details)
[riscv] Canonicalize vsetvli (vsetvli avl, vtype1) vtype2 transitionsas reviewed (details)
[RISCV] Add a DAG combine to pre-promote (i32 (and (srl X, Y), 1)) with Zbs on RV64. (details)
[InstCombine] update auto-generated CHECK lines in test file; NFC (details)
[InstCombine] freeze operand in sdiv expansion (details)
[RISCV] Override TargetLowering::shouldProduceAndByConstByHoistingConstFromShiftsLHSOfAnd. (details)
[RISCV] Move implementation of getVLOpNum and getSEWOpNum from RISCVInsertVSETVLI to RISCVBaseInfo.h. NFC (details)
[HLSL] add -D option for dxc mode. (details)
[clang] Fix KEYALL (details)
[RISCV] Add caching to the gather/scatter to strided load/store conversion. (details)
[clang][ppc] Creating Seperate Install Target for PPC htm Headers (details)
[TableGen] Remove the use of global Record state (details)
[TableGen] Refactor TableGenParseFile to no longer use a callback (details)
[test, riscv] Add test illustrating missing handling for fallthrough blocks in 541c9ba (details)
[CodeGenPrepare] Use const reference to avoid unnecessary APInt copy. NFC (details)
[libc++] Add a few more debug wrapper functions (details)
[libc++] Remove __invalidate_all_iterators and replace the uses with std::__debug_db_invalidate_all (details)
[AsmParser] Adopt emitWrongTokenError more, improving QoI (details)
[GVN] Add test case for memdep invalidation bug. (details)
[RISCV] Fold addiw from (add X, (addiw (lui C1, C2))) into load/store address (details)
[RISCV] Enable subregister liveness tracking for RVV. (details)

Commit d428f09b2c9d49f6a328ef636c02305a8be4ab61 by spatel [InstCombine] freeze operand in urem expansion As discussed in issue #37809, this transform is not safe if the input is an undefined value. There is no difference in codegen on the basic examples, but this could lead to regressions. We may need to improve freeze analysis or lowering if that happens.
	llvm/test/Transforms/InstCombine/rem.ll
	llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp
	llvm/test/Transforms/InstCombine/vector-urem.ll
Commit 3a26596af3613a2ede294ed017f2c05e48255713 by pklausler [flang] Fold complex component references Complex component references (z%RE, z%IM) of complex named constants should be evaluated at compilation time. Differential Revision: https://reviews.llvm.org/D125341
	flang/test/Evaluate/fold-re-im.f90
	flang/include/flang/Evaluate/variable.h
	flang/include/flang/Evaluate/type.h
	flang/lib/Semantics/expression.cpp
	flang/lib/Evaluate/fold-implementation.h
	flang/lib/Evaluate/fold-real.cpp
	flang/lib/Evaluate/tools.cpp
	flang/include/flang/Evaluate/tools.h
Commit 0cc607345fa5c03cda7e1989f91858ce1a1551d4 by mtrofin [mlgo] Fix test Updated reference file for dev-mode-logging.ll and expected output.
	llvm/test/CodeGen/MLRegalloc/dev-mode-logging.ll
	llvm/test/CodeGen/MLRegalloc/Inputs/reference-log-noml.txt
Commit d9c1d3cbcb9751a6a82cc5e4ada0533cbbc79a1a by daltenty [clang][AIX] Don't ignore XCOFF visibility by default D87451 added -mignore-xcoff-visibility for AIX targets and made it the default (which mimicked the behaviour of the XL 16.1 compiler on AIX). However, ignoring hidden visibility has unwanted side effects and some libraries depend on visibility to hide non-ABI facing entities from user headers and reserve the right to change these implementation details based on this (https://libcxx.llvm.org/DesignDocs/VisibilityMacros.html). This forces us to use internal linkage fallbacks for these cases on AIX and creates an unwanted divergence in implementations on the plaform. For these reasons, it's preferable to not add -mignore-xcoff-visibility by default, which is what this patch does. Reviewed By: DiggerLin Differential Revision: https://reviews.llvm.org/D125141
	clang/include/clang/Driver/Options.td
	clang/docs/ReleaseNotes.rst
	clang/test/CodeGen/PowerPC/aix-visibility-inlines-hidden.cpp
	clang/test/CodeGen/PowerPC/aix-ignore-xcoff-visibility.cpp
	clang/lib/Frontend/CompilerInvocation.cpp
Commit 987362342597df266df6b5ac871c9ca19b064795 by preames [riscv] Add tests for vsetvli reuse across iterations of a loop These variations are chosen to exercise both FRE and PRE cases involving loops which don't change state in the iteration and can thus perform vsetvli in the preheader of the loop only. At the moment, these are essentially all TODOs.
	llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll
Commit d80d812df0c829b6dbbcb968e7c3cf3c6be6ff41 by pklausler [flang] Fix check for assumed-size arguments to SHAPE() & al. The predicate that is used to detect an invalid assumed-size argument to the intrinsic functions SHAPE, SIZE, & LBOUND gives false results for arguments whose shapes are not calculatable at compilation time. Replace with an explicit test for an assumed-size array dummy argument symbol. Differential Revision: https://reviews.llvm.org/D125342
	flang/lib/Evaluate/intrinsics.cpp
Commit f37e6faf523d237a04b91fa3d736659a6ef8a9c6 by aeubanks [gn build] Use llvm-ar when clang_base_path is specified Only applies linux for now. This prevents warnings with use_thinlto like bfd plugin: LLVM gold plugin has failed to create LTO module: Not an int attribute (Producer: 'LLVM15.0.0git' Reader: 'LLVM 13.0.1') Reviewed By: thakis Differential Revision: https://reviews.llvm.org/D125399
	llvm/utils/gn/build/toolchain/BUILD.gn
Commit 72925d98bf928431e430a49a0504bda8d7d0d184 by preames [riscv] Canonicalize vsetvli (vsetvli avl, vtype1) vtype2 transitionsas reviewed This patch is an alternative to a piece of D125270. If we have one vsetvli which is using as AVL the output of another, and the prior AVL can be proven to produce the same VL value as that defining one, we can use the AVL from the prior instruction. This has the effect of removing a state transition on AVL, and will let us use the cheaper 'vsetvli x0, x0, vtype1' form or possible even skip emitting it entirely. This builds on the same infrastructure as D125337, and does the analogous extension to working on abstract states instead of only prior explicit vsetvli instructions. This is where the (relatively minor) code improvements come from. More importantly, this fixes the last case where the state computed in phase 1 and 2 of the algorithm differs from the state computed during phase 3. Note that such differences can cause miscompiles by creating disagreements about contents of the VL and VTYPE registers at block boundaries. Doing this transform inside the dataflow can cause the compatibility of a later store to change with regards to the current state. test15 in the diff illustrates this case well. What we have is a vsetvli which is mutated by one following vector op, but whose GPR result is used by another. The compatibility logic walks back to the def in this case, and checks to see if it matches the immediate prior state. In phase 1 and 2, it doesn't, and in phase 3 (after mutation) it does because we remove a transition which caused it to differ. Differential Revision: https://reviews.llvm.org/D125392
	llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll
	llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
Commit 078174278574761edfd557908af59c67aa7b303e by craig.topper [RISCV] Add a DAG combine to pre-promote (i32 (and (srl X, Y), 1)) with Zbs on RV64. Type legalization will want to turn (srl X, Y) into RISCVISD::SRLW, which will prevent us from using a BEXT instruction. I don't think there is any precedent for type promotion checking users to decide how to promote. Instead, I've added this DAG combine to do it before type legalization. Reviewed By: asb Differential Revision: https://reviews.llvm.org/D124109
	llvm/lib/Target/RISCV/RISCVISelLowering.cpp
	llvm/test/CodeGen/RISCV/rv64zbs.ll
Commit 5fdfcf489264fea9840fd70536b79cdcd22b1c0d by spatel [InstCombine] update auto-generated CHECK lines in test file; NFC These are all cosmetic (value naming) diffs that would distract from real changes in this file.
	llvm/test/Transforms/InstCombine/div.ll
Commit 99ef341ce9436e0471eb5502a8521fcaddaf851c by spatel [InstCombine] freeze operand in sdiv expansion As discussed in issue #37809, this transform is not safe if the input is an undefined value. This is similar to a recent change for urem: d428f09b2c9d There is no difference in codegen on the basic examples, but this could lead to regressions. We may need to improve freeze analysis or lowering if that happens. Presumably, in real cases that are similar to the tests where a subsequent transform removes the select, we will also be able to remove the freeze by seeing that the parameter has 'noundef'.
	llvm/test/Transforms/InstCombine/div.ll
	llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp
Commit 0ebb02b90a47b43e039cb7040cc9fb7dd5ec5fce by craig.topper [RISCV] Override TargetLowering::shouldProduceAndByConstByHoistingConstFromShiftsLHSOfAnd. This hook determines if SimplifySetcc transforms (X & (C l>>/<< Y)) ==/!= 0 into ((X <</l>> Y) & C) ==/!= 0. Where C is a constant and X might be a constant. The default implementation favors doing the transform if X is not a constant. Otherwise the code is left alone. There is a provision that if the target supports a bit test instruction then the transform will favor ((1 << Y) & X) ==/!= 0. RISCV does not say it has a variable bit test operation. RISCV with Zbs does have a BEXT instruction that performs (X >> Y) & 1. Without Zbs, (X >> Y) & 1 still looks preferable to ((1 << Y) & X) since we can fold use ANDI instead of putting a 1 in a register for SLL. This patch overrides this hook to favor bit extract patterns and otherwise falls back to the "do the transform if X is not a constant" heuristic. I've added tests where both C and X are constants with both the shl form and lshr form. I've also added a test for a switch statement that lowers to a bit test. That was my original motivation for looking at this. Reviewed By: asb Differential Revision: https://reviews.llvm.org/D124639
	llvm/lib/Target/RISCV/RISCVISelLowering.cpp
	llvm/test/CodeGen/RISCV/bittest.ll
	llvm/lib/Target/RISCV/RISCVISelLowering.h
Commit 09f48c6b80a44f91cc8acae1406ce4224e0bfe42 by craig.topper [RISCV] Move implementation of getVLOpNum and getSEWOpNum from RISCVInsertVSETVLI to RISCVBaseInfo.h. NFC We should consolidate the operand counting and ordering into RISCVBaseInfo.h and stop spreading it around. Reviewed By: asb Differential Revision: https://reviews.llvm.org/D125344
	llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
	llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
Commit 4dae38ebfba0d8583e52c3ded8f62f5f9fa77fda by python3kgae [HLSL] add -D option for dxc mode. Create dxc_D as alias to option D which Define <macro> to <value> (or 1 if <value> omitted). Reviewed By: aaron.ballman Differential Revision: https://reviews.llvm.org/D125338
	clang/include/clang/Driver/Options.td
	clang/lib/Driver/ToolChains/Clang.cpp
	clang/test/Driver/dxc_D.hlsl
Commit 84db35594953a6f7aff7cbc007f1c5d2fd35b1a9 by Yaxun.Liu [clang] Fix KEYALL Update KEYALL to cover KEYCUDA. Introduce KEYMAX and a generic way to update KEYALL. Reviewed by: Dan Liew Differential Revision: https://reviews.llvm.org/D125396
	clang/lib/Basic/IdentifierTable.cpp
Commit f499ec6b3d138e6b5643f5c848c38d61462e063b by craig.topper [RISCV] Add caching to the gather/scatter to strided load/store conversion. If we have multiple gather/scatter instructions using the same the same strided address we would scalarize it multiple times. I guess a later pass cleans this up, but I don't know if that's guaranteed. This patch adds a cache to remember the scalarization we already created for a previous gather/scatter. Reviewed By: frasercrmck Differential Revision: https://reviews.llvm.org/D125326
	llvm/test/CodeGen/RISCV/rvv/fixed-vector-strided-load-store.ll
	llvm/lib/Target/RISCV/RISCVGatherScatterLowering.cpp
Commit 3ca6328637b3f42096c652e4df53282649956bdb by qwu [clang][ppc] Creating Seperate Install Target for PPC htm Headers This patch splits out the htm intrinsic headers from the PPC headers list. Reviewed By: jsji Differential Revision: https://reviews.llvm.org/D125386
	clang/lib/Headers/CMakeLists.txt
Commit 2ac3cd20cacdf37135eeb64ad2b7baefb9769e99 by riddleriver [TableGen] Remove the use of global Record state This commits removes TableGens reliance on managed static global record state by moving the RecordContext into the RecordKeeper. The RecordKeeper is now treated similarly to a (LLVM\|MLIR\|etc)Context object and is passed to static construction functions. This is an important step forward in removing TableGens reliance on global state, and in a followup will allow for users that parse tablegen to parse multiple tablegen files without worrying about Record lifetime. Differential Revision: https://reviews.llvm.org/D125276
	llvm/utils/TableGen/DecoderEmitter.cpp
	llvm/lib/TableGen/Record.cpp
	llvm/utils/TableGen/CodeGenInstruction.cpp
	llvm/utils/TableGen/SearchableTableEmitter.cpp
	llvm/utils/TableGen/CodeGenTarget.cpp
	llvm/utils/TableGen/CodeGenRegisters.cpp
	llvm/utils/TableGen/PseudoLoweringEmitter.cpp
	llvm/lib/TableGen/Parser.cpp
	llvm/lib/TableGen/Error.cpp
	llvm/lib/TableGen/TGParser.cpp
	llvm/utils/TableGen/CodeGenDAGPatterns.cpp
	llvm/include/llvm/TableGen/Record.h
	llvm/lib/TableGen/RecordContext.h
	llvm/utils/TableGen/WebAssemblyDisassemblerEmitter.cpp
Commit 5a9a438a54672915247b70ba293d2e8dfe262570 by riddleriver [TableGen] Refactor TableGenParseFile to no longer use a callback Now that TableGen no longer relies on global Record state, we can allow for the client to own the RecordKeeper and SourceMgr. Given that TableGen internally still relies on the global llvm::SrcMgr, this method unfortunately still isn't thread-safe. Differential Revision: https://reviews.llvm.org/D125277
	mlir/lib/Tools/PDLL/Parser/Parser.cpp
	llvm/include/llvm/TableGen/Parser.h
	llvm/unittests/TableGen/ParserEntryPointTest.cpp
	llvm/lib/TableGen/Parser.cpp
Commit ca81c0f8fca4730d4cf9c950c2b38d10e37d7357 by preames [test, riscv] Add test illustrating missing handling for fallthrough blocks in 541c9ba
	llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.mir
Commit edbf390d10b86962774c920cfab089fa1fd1c3f5 by craig.topper [CodeGenPrepare] Use const reference to avoid unnecessary APInt copy. NFC Spotted while looking at Matthias' patches. Reviewed By: RKSimon Differential Revision: https://reviews.llvm.org/D124985
	llvm/lib/CodeGen/CodeGenPrepare.cpp
Commit 08f68dfef6102e7b18116aec30ecb712cedfc2d9 by nikolasklauser [libc++] Add a few more debug wrapper functions Reviewed By: ldionne, #libc, jloser Spies: libcxx-commits Differential Revision: https://reviews.llvm.org/D125176
	libcxx/include/__hash_table
	libcxx/include/vector
	libcxx/include/unordered_map
	libcxx/include/unordered_set
	libcxx/include/string
	libcxx/include/list
	libcxx/include/__debug
Commit c095440cafb22f9342fafbbef0b8dee04fc24206 by nikolasklauser [libc++] Remove __invalidate_all_iterators and replace the uses with std::__debug_db_invalidate_all Reviewed By: ldionne, #libc Spies: libcxx-commits Differential Revision: https://reviews.llvm.org/D125188
	libcxx/include/vector
	libcxx/include/list
	libcxx/include/string
Commit 86445e8c63c7a15456149c88b99af03933268c5d by clattner [AsmParser] Adopt emitWrongTokenError more, improving QoI This is a full audit of emitError calls, I took the opportunity to remove extranous parens and fix a couple cases where we'd generate multiple diagnostics for the same error. Differential Revision: https://reviews.llvm.org/D125355
	mlir/test/Dialect/SPIRV/IR/misc-ops.mlir
	mlir/test/Dialect/SPIRV/IR/logical-ops.mlir
	mlir/test/IR/invalid-locations.mlir
	mlir/test/Dialect/SPIRV/IR/ocl-ops.mlir
	mlir/lib/Parser/AffineParser.cpp
	mlir/lib/Parser/TypeParser.cpp
	mlir/lib/Parser/LocationParser.cpp
	mlir/test/IR/invalid.mlir
	mlir/lib/Parser/DialectSymbolParser.cpp
	mlir/test/Dialect/SPIRV/IR/glsl-ops.mlir
	mlir/lib/Parser/AttributeParser.cpp
Commit 411b9b8153ee95a51a2b7b3ebdb6fec9a7229f5a by flo [GVN] Add test case for memdep invalidation bug. Test case for #30999.
	llvm/test/Transforms/GVN/condprop-memdep-invalidation.ll
Commit 5c7ec998a916baf8b35d571d0cc11753d464792d by craig.topper [RISCV] Fold addiw from (add X, (addiw (lui C1, C2))) into load/store address This is a followup to D124231. We can fold the ADDIW in this pattern if we can prove that LUI+ADDI would have produced the same result as LUI+ADDIW. This pattern occurs because constant materialization prefers LUI+ADDIW for all simm32 immediates. Only immediates in the range 0x7ffff800-0x7fffffff require an ADDIW. Other simm32 immediates work with LUI+ADDI. Reviewed By: asb Differential Revision: https://reviews.llvm.org/D124693
	llvm/test/CodeGen/RISCV/mem64.ll
	llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
	llvm/test/CodeGen/RISCV/mem.ll
Commit ed242b54c9c2aa84a47f66af5b8497d93646b68d by craig.topper [RISCV] Enable subregister liveness tracking for RVV. RVV makes heavy use of subregisters due to LMUL>1 and segment load/store tuples. Enabling subregister liveness tracking improves the quality of the register allocation. I've added a command line that can be used to turn it off if it causes compile time or functional issues. I used the command line to keep the old behavior for one interesting test case that was testing register allocation. Reviewed By: frasercrmck Differential Revision: https://reviews.llvm.org/D125108
	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv32.ll
	llvm/test/CodeGen/RISCV/rvv/vsseg-rv32.ll
	llvm/test/CodeGen/RISCV/rvv/zvlsseg-zero-vl.ll
	llvm/test/CodeGen/RISCV/rvv/vlsseg-rv64.ll
	llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int.ll
	llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-exttrunc.ll
	llvm/test/CodeGen/RISCV/rvv/vlseg-rv32.ll
	llvm/test/CodeGen/RISCV/rvv/vlsseg-rv32.ll
	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
	llvm/test/CodeGen/RISCV/rvv/rv64-spill-zvlsseg.ll
	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
	llvm/test/CodeGen/RISCV/rvv/vlsegff-rv32.ll
	llvm/test/CodeGen/RISCV/rvv/rv32-spill-zvlsseg.ll
	llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-interleave.ll
	llvm/test/CodeGen/RISCV/rvv/vpgather-sdnode.ll
	llvm/test/CodeGen/RISCV/rvv/vlsegff-rv64.ll
	llvm/test/CodeGen/RISCV/rvv/fixed-vector-segN-load.ll
	llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll
	llvm/lib/Target/RISCV/RISCVSubtarget.cpp
	llvm/test/CodeGen/RISCV/rvv/vlseg-rv64.ll
	llvm/test/CodeGen/RISCV/regalloc-last-chance-recoloring-failure.ll
	llvm/lib/Target/RISCV/RISCVSubtarget.h
	llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
	llvm/test/CodeGen/RISCV/rvv/vssseg-rv64.ll
	llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-interleave.ll
	llvm/test/CodeGen/RISCV/rvv/vssseg-rv32.ll
	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv32.ll
	llvm/test/CodeGen/RISCV/rvv/vsseg-rv64.ll
	llvm/test/CodeGen/RISCV/rvv/insert-subvector.ll
	llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll
	llvm/test/CodeGen/RISCV/rvv/vlsegff-rv32-dead.ll
	llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
	llvm/test/CodeGen/RISCV/rvv/extract-subvector.ll
	llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
	llvm/test/CodeGen/RISCV/rvv/vlsegff-rv64-dead.ll
	llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll