Changes

[VPlan] Exit earlier when trying to widen with scalar VFs.

This simplifies the code a bit, suggested in D124718.

Reviewed By: Ayal

Differential Revision: https://reviews.llvm.org/D125029

[pseudo] Add missing dependency, fix shared library build.

[LoopVectorize] Fix assertion failure in fixReduction when tail-folding

When compiling the attached new test in scalable-reductions-tf.ll we
were hitting this assertion in fixReduction:

  Assertion `isa<PHINode>(U) && "Reduction exit must feed Phi's or select"

The loop contains a reduction and an intermediate store of the reduction
value. When vectorising with tail-folding the contains of 'U' in the
assertion above happened to be a scatter_store. It turns out that we
were still creating a widen recipe for the invariant store, despite
knowing that we can actually sink it. The simplest fix is to change
buildVPlanWithVPRecipes so that we look for invariant stores before
attempting to widen it.

Differential Revision: https://reviews.llvm.org/D126295

[Clang] Added options for integrated backend.

Following the new flow for external object code emission,
provide flags to switch between integrated and external
backend similar to the integrated assembler options.

SPIR-V target is the only user of this functionality at
this point.

This patch also updated SPIR-V documentation to clarify
that integrated object code emission for SPIR-V is an
experimental feature.

Differential Revision: https://reviews.llvm.org/D125679

[ARM] Fix vcvtb/t.f16 input liveness

The `vcvtb.f16.f32 Sd, Sn` (and vcvtt.f16.f32) instruction convert a f32
into a f16, writing either the top or bottom halves of the register.
That means that half of the input register Sd is used in the output.
This wasn't being modelled in the instructions, leading later analyses
to believe that the registers were dead where they were not, generating
invalid scheduling

Fix that be specifying the input Sda register for the instructions too,
allowing them to be set for cases like vector inserts. Most of the
changes are plumbing through the constraint string, cstr.

Differential Revision: https://reviews.llvm.org/D126118

[gn build] (manually) port some of cd2292ef8245

[mlir][openmp] Add check for types of operands in omp.atomic.write

This patch makes sure that the address dereferences to value in
omp.atomic.write operation.

Reviewed By: kiranchandramohan, peixin

Differential Revision: https://reviews.llvm.org/D126272

[MLIR][Linalg] Adjust documentation (NFC)

Adjust docs for tensor.pad, tensor.collapse_shape and tensor.expand_shape.

Reviewed By: ftynse

Differential Revision: https://reviews.llvm.org/D126370

[clang-tidy] Extend SimplifyBooleanExpr demorgan support.

Adds an option SimplifyDemorganRelaxed which, when enabled, will transform negated conjunctions or disjunctions when neither operand is a negation.
Default value is `false`.

Reviewed By: LegalizeAdulthood

Differential Revision: https://reviews.llvm.org/D126162

[clang-tidy] Update docs for SimplifyDeMorganRelaxed

Forgot to add this to f3c1d281767

Test C DR conformance (part three of many)

This adds more of the tests for the first 100 DRs in C and updates
their status on the status page.

[x86] add test with volatile load; NFC

Test for D126353

[lld-macho] Support  -non_global_symbols_strip_list, -non_global_symbols_no_strip_list, -x

PR/55600

Differential Revision: https://reviews.llvm.org/D126046

[tests] precommit tests for D126040

Reviewed By: spatel

Differential Revision: https://reviews.llvm.org/D126356

[MLIR][NFC] Fix the Conversion/MemRefToSPIRV/alloc.mlir test.

Caught with D125604.

Reviewed By: antiagainst

Differential Revision: https://reviews.llvm.org/D126292

[pseudo-gen] Add -o flag, make --grammar required

Virtually all LLVM tools accept a `-o` flag, so add one. This will make it
possible to possibly add a --write-if-changed flag later. It also makes it
so that the file isn't partially written if the tool oesn't run successfully.

Marking --grammar as `Required` allows removing some manual
verification code for it.

Differential Revision: https://reviews.llvm.org/D126373

[AST] Dont invalidate a ref-type var decl if it has no initializer.

This would allow more AST nodes being preserved for broken code, and
have a more consistent valid bit for ref-type var decl (currently, a
ref-type var decl with a broken initializer is valid).

Per https://reviews.llvm.org/D76831#1973053, the initializer of a variable
should play no part in its "invalid" bit.

Reviewed By: sammccall

Differential Revision: https://reviews.llvm.org/D122935

Fix unused-variable warning, NFC.

[libc++] Use Python subprocess instead of libc++'s own utilities

Once we move off entirely from the legacy testing framework, this will
allow removing a bunch of code.

Differential Revision: https://reviews.llvm.org/D126303

[PS5] Default to -fno-rtti

[VP][fix] Don't discard masks in reductions

When expanding VP reductions to non VP-code, the reduction pass was
ignoring the mask before. Fix this by keeping the mask and selecting
neutral elements where the mask is zero.

Reviewed By: frasercrmck

Differential Revision: https://reviews.llvm.org/D126362

[libc++] Remove conditional include

[MLIR][Presburger] Add getDomainSet, getRangeSet to IntegerRelation

This patch adds support for obtaining a set corresponding to the domain/range
of the relation.

Reviewed By: ftynse

Differential Revision: https://reviews.llvm.org/D126326

[PhaseOrdering] Add test for unprofitable loop load PRE backedge splitting (NFC)

[MLIR][Presburger] Add inverse to IntegerRelation

This patch adds support for obtaining inverse of a relation.

Reviewed By: ftynse

Differential Revision: https://reviews.llvm.org/D126327

[llvm-rc] Avoid which(1) dependency in windres-prefix.test

Rely on lit substitution to provide the path to llvm-windres instead
of redundantly calling which(1) with the subtituted absolute path.
This fixes test failure on the happy systems without which(1) installed.

Differential Revision: https://reviews.llvm.org/D126366

[TableGen] Undeprecate 'field' when used with the CodeEmitterGen backend.

Differential Revision: https://reviews.llvm.org/D126290

[riscv] Add coverage for fixed length vector loops using LMUL

[libc++][test] Verify std::ranges::rbegin, crbegin, rend, crend are CPOs

Uncomment the tests to ensure `std::ranges::rbegin` and friends are indeed
customization points objects.

Differential Revision: https://reviews.llvm.org/D126325

[mlir][scf] Retain existing attributes in scf.for transforms

These attributes can carry useful information, e.g., pipelines
might use them to organize and chain patterns.

Reviewed By: hanchung

Differential Revision: https://reviews.llvm.org/D126320

[mlir][spirv] Fix capability check for 64-bit element types

Using 64-bit integer/float type in interface storage classes would
require Int64/Float64 capability, per the Vulkan spec:

```
shaderInt64 specifies whether 64-bit integers (signed and unsigned) are
supported in shader code. If this feature is not enabled, 64-bit integer
types must not be used in shader code. This also specifies whether
shader modules can declare the Int64 capability. Declaring and using
64-bit integers is enabled for all storage classes that SPIR-V allows
with the Int64 capability.
```

This is different from, say, 16-bit element types, where:

```
shaderInt16 specifies whether 16-bit integers (signed and unsigned) are
supported in shader code. If this feature is not enabled, 16-bit integer
types must not be used in shader code. This also specifies whether
shader modules can declare the Int16 capability. However, this only
enables a subset of the storage classes that SPIR-V allows for the Int16
SPIR-V capability: Declaring and using 16-bit integers in the Private,
Workgroup (for non-Block variables), and Function storage classes is
enabled, while declaring them in the interface storage classes (e.g.,
UniformConstant, Uniform, StorageBuffer, Input, Output, and
PushConstant) is not enabled.
```

Reviewed By: hanchung

Differential Revision: https://reviews.llvm.org/D126256

[RISCV] Restructure comment and add clarifying assert to getFrameIndexReference [NFC]

Differential Revision: https://reviews.llvm.org/D126088