Changes

Summary

  1. [LV] Add additional tests for pointer select support. (details)
  2. Revert "[ValueTypes] Define MVTs for v128i2/v64i4 as well as i2 and i4." (details)
  3. Refactor PS4OSTargetInfo into a base class and PS4 subclass; prep for PS5 (details)
  4. [PS5] Add PS5OSTargetInfo class, update affected tests (details)
  5. [ObjectYAML][DX] Support yaml2dxcontainer (details)
  6. [gn build] Port 129c056d6269 (details)
  7. [BOLT][NFC] Remove unused variable (details)
  8. [flang][NFC] Document intentional non-support for an extension (details)
  9. Temporarily disabling this test on arm (details)
  10. [bazel] Add a missing dependency after f3bdb56d61e3 (details)
  11. update_mir_test_checks: Better handling of common prefixes (details)
  12. [BOLT][TEST] Replace cache+ option with ext-tsp (details)
  13. [LV] Update var name to Exiting, in line with terminology (NFC) (details)
  14. [mlir][sparse] Using non-empty function name suffix for OverheadType::kIndex (details)
  15. Temporarily disabling this test on arm (details)
  16. [mlir][sparse][NFC] Switch InitOp to bufferization::AllocTensorOp (details)
  17. [clang][AIX] add option mdefault-visibility-export-mapping (details)
  18. [RISCV] Use MachineRegisterInfo::use_instr_begin instead of use_begin+getParent. NFCI (details)
  19. [Binary] Promote OffloadBinary to inherit from Binary (details)
  20. Revert "[SLP]Improve shuffles cost estimation where possible." (details)
  21. [RISCV] Split fixed-vector-strided-load-store.ll so it can be autogened (details)
  22. [OMPIRBuilder] Add the support for compare capture (details)
  23. [Object] Fix namespace style issues in D122069 (details)
  24. [RegisterClassInfo] Invalidate cached information if ignoreCSRForAllocationOrder changes (details)
  25. [Polly] Fix -Wreorder-ctor. NFC (details)
  26. [ValueTypes] Define MVTs for v128i2/v64i4 as well as i2 and i4. (details)
  27. LTO: Decide upfront whether to use opaque/non-opaque pointer types (details)
  28. AMDGPU: Fix missing c++ mode comment (details)
  29. AMDGPU: Add release notes about atomic load and store (details)
  30. BranchFolder: Require NoPHIs (details)
Commit 72aca94b9080f1c89b2772b3a2612022525bf0d0 by flo
[LV] Add additional tests for pointer select support.

Additional test cases for D114487.
The file was addedllvm/test/Transforms/LoopVectorize/pointer-select-runtime-checks.ll
Commit e9d05cc7d82cc828f5bc8f40d3bf00b09885e7ce by hgreving
Revert "[ValueTypes] Define MVTs for v128i2/v64i4 as well as i2 and i4."

This reverts commit 430ac5c3029c52e391e584c6d4447e6e361fae99.

Due to failures in Clang tests.

Differential Revision: https://reviews.llvm.org/D125247
The file was modifiedllvm/test/CodeGen/X86/srem-seteq-illegal-types.ll
The file was modifiedllvm/test/CodeGen/AArch64/srem-seteq-illegal-types.ll
The file was modifiedllvm/lib/CodeGen/TargetLoweringBase.cpp
The file was modifiedllvm/lib/CodeGen/ValueTypes.cpp
The file was modifiedllvm/lib/IR/Function.cpp
The file was modifiedllvm/test/CodeGen/X86/bitreverse.ll
The file was modifiedllvm/include/llvm/CodeGen/ValueTypes.td
The file was modifiedllvm/test/CodeGen/AMDGPU/srem-seteq-illegal-types.ll
The file was modifiedllvm/test/CodeGen/Thumb/srem-seteq-illegal-types.ll
The file was modifiedllvm/test/CodeGen/ARM/srem-seteq-illegal-types.ll
The file was modifiedllvm/test/TableGen/intrinsic-pointer-to-any.td
The file was modifiedllvm/test/CodeGen/PowerPC/srem-seteq-illegal-types.ll
The file was modifiedllvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll
The file was modifiedllvm/utils/TableGen/CodeGenTarget.cpp
The file was modifiedllvm/include/llvm/Support/MachineValueType.h
The file was modifiedllvm/test/CodeGen/Thumb2/srem-seteq-illegal-types.ll
The file was modifiedllvm/utils/TableGen/IntrinsicEmitter.cpp
The file was modifiedllvm/test/CodeGen/Mips/srem-seteq-illegal-types.ll
Commit 5d005d8256ecd7d57c72e24e7169c4e3d40a773a by paul.robinson
Refactor PS4OSTargetInfo into a base class and PS4 subclass; prep for PS5
The file was modifiedclang/lib/Basic/Targets/OSTargets.h
Commit 8869ba366268c644200784b15c4e6b8efe891397 by paul.robinson
[PS5] Add PS5OSTargetInfo class, update affected tests
The file was modifiedclang/lib/Basic/Targets.cpp
The file was modifiedclang/test/Sema/wchar.c
The file was modifiedclang/lib/Basic/LangStandards.cpp
The file was modifiedclang/test/Preprocessor/init.c
The file was modifiedclang/unittests/Tooling/RecursiveASTVisitorTests/LambdaExpr.cpp
The file was modifiedclang/lib/Basic/Targets/OSTargets.h
Commit 129c056d626986eb95f9724283b8f6106cdde2e9 by chris.bieneman
[ObjectYAML][DX] Support yaml2dxcontainer

This patch adds a the first bits of support for a yaml representation
of dxcontainer files.

Since the YAML representation's primary purpose is testing
infrastructure, the yaml representation supports both verbose and a
more friendly format by making computable sizes and offsets optional.
If provided they are validated to be correct, otherwise they are
computed on the fly during emission.

As I expand the format I'll be able to make more size fields optional,
and I will continue to make the format easier to work with.

Depends on D124804

Reviewed By: lhames

Differential Revision: https://reviews.llvm.org/D124944
The file was addedllvm/lib/ObjectYAML/DXContainerEmitter.cpp
The file was modifiedllvm/include/llvm/BinaryFormat/DXContainer.h
The file was addedllvm/include/llvm/ObjectYAML/DXContainerYAML.h
The file was modifiedllvm/unittests/ObjectYAML/CMakeLists.txt
The file was addedllvm/unittests/ObjectYAML/DXContainerYAMLTest.cpp
The file was modifiedllvm/include/llvm/ObjectYAML/yaml2obj.h
The file was modifiedllvm/lib/ObjectYAML/CMakeLists.txt
The file was addedllvm/test/tools/obj2yaml/DXContainer/InvalidSize.yaml
The file was addedllvm/lib/ObjectYAML/DXContainerYAML.cpp
The file was modifiedllvm/include/llvm/ObjectYAML/ObjectYAML.h
The file was addedllvm/test/tools/obj2yaml/DXContainer/InvalidOffset.yaml
The file was modifiedllvm/lib/ObjectYAML/yaml2obj.cpp
The file was modifiedllvm/lib/ObjectYAML/ObjectYAML.cpp
Commit 4bc63858fc04f0901b844ea4c068ada2f00b11dd by llvmgnsyncbot
[gn build] Port 129c056d6269
The file was modifiedllvm/utils/gn/secondary/llvm/lib/ObjectYAML/BUILD.gn
The file was modifiedllvm/utils/gn/secondary/llvm/unittests/ObjectYAML/BUILD.gn
Commit 0426100ff4822add9271f55ac508387f3433fb00 by maks
[BOLT][NFC] Remove unused variable

Reviewed By: Amir

Differential Revision: https://reviews.llvm.org/D126808
The file was modifiedbolt/lib/Core/BinaryFunction.cpp
Commit f2ee0a3f2c5c6f1fd25b0cb9b52745dd368827e9 by pklausler
[flang][NFC] Document intentional non-support for an extension

F18 doesn't accept INTEGER operands to the intrinsic LOGICAL operations;
some compilers do.  This usage is not portable, and not just because it's
non-conforming -- the bit representations of LOGICAL also vary between
compilers and options.  The "MIL-STD" bit intrinsics IAND() & al. have been
avaiable since the late 70's and should be used instead.

Differential Revision: https://reviews.llvm.org/D126798
The file was modifiedflang/docs/Extensions.md
Commit 7b759d6d87ea88acc730f31c474fc161addc4f3d by chris.bieneman
Temporarily disabling this test on arm

This is failing on an arm32 builder, and it is going to take me a while
to debug. To not block further progress I'm disabling this test on
arm32 configuraitons.
The file was modifiedllvm/unittests/Object/DXContainerTest.cpp
Commit d9de52819dbd37aa8007efce69016175d849cdde by benny.kra
[bazel] Add a missing dependency after f3bdb56d61e3
The file was modifiedutils/bazel/llvm-project-overlay/mlir/test/BUILD.bazel
The file was modifiedutils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Commit d53de9b7ac394963730ef34616d4104746eea0f0 by nicolai.haehnle
update_mir_test_checks: Better handling of common prefixes

Support the pattern where a test file uses multiple prefixes per run line:
one prefix that is unique to the run line, and additional prefixes that are
common with other run lines.

Decide on a per-function basis which prefix(es) to emit, based on which run
lines have the same output.

Move the renaming of vregs earlier, so that we can compare the output as it
would actually be printed in check lines.

Differential Revision: https://reviews.llvm.org/D126411
The file was addedllvm/test/tools/UpdateTestChecks/update_mir_test_checks/Inputs/x86-multiple-prefixes.ll.expected
The file was modifiedllvm/utils/update_mir_test_checks.py
The file was addedllvm/test/tools/UpdateTestChecks/update_mir_test_checks/x86-multiple-prefixes.test
The file was addedllvm/test/tools/UpdateTestChecks/update_mir_test_checks/Inputs/x86-multiple-prefixes.ll
Commit 38fb7d56e543f3cd137a79d6e6331b697ef9f92c by aaupov
[BOLT][TEST] Replace cache+ option with ext-tsp

Replace "cache+" with "ext-tsp" in all BOLT tests

Test Plan:
```
ninja check-bolt
grep -rnw . -e "cache+"
```
no more tests containing "cache+"
"cache+" and "ext-tsp" are aliases

Reviewed By: rafauler

Differential Revision: https://reviews.llvm.org/D126714
The file was modifiedbolt/README.md
The file was modifiedbolt/test/X86/bug-reorder-bb-jrcxz.s
The file was modifiedbolt/test/runtime/X86/instrumentation-shlib.c
The file was modifiedbolt/test/runtime/X86/instrumentation-indirect.c
The file was modifiedbolt/test/runtime/X86/exceptions-instrumentation.test
The file was modifiedbolt/test/X86/loop-inversion-pass.s
The file was modifiedbolt/test/runtime/X86/instrumentation-pie.c
The file was modifiedbolt/test/runtime/X86/instrumentation-ind-calls.s
The file was modifiedbolt/test/runtime/X86/instrumentation-dup-jts.s
The file was modifiedbolt/test/runtime/X86/fix-branches-jrcxz.s
The file was modifiedbolt/test/X86/tail-duplication-pass.s
The file was modifiedbolt/test/runtime/meta-merge-fdata.test
The file was modifiedbolt/test/runtime/X86/tail-duplication-constant-prop.s
The file was modifiedbolt/docs/OptimizingClang.md
Commit 08482830eb8a038450d36103aa2a3569a9dcea5c by flo
[LV] Update var name to Exiting, in line with terminology (NFC)

Recently the terminology used has been changed from Exit->Exiting in
line with common LLVM loop terminology. Update a remaining use of the
old terminology.
The file was modifiedllvm/lib/Transforms/Vectorize/LoopVectorize.cpp
Commit b364c76683f8ef241025a9556300778c07b590c2 by 2998727+wrengr
[mlir][sparse] Using non-empty function name suffix for OverheadType::kIndex

The trick of using an empty token in the `FOREVERY_O` x-macro relies on preprocessor behavior which is only standard since C99 6.10.3/4 and C++11 N3290 16.3/4 (whereas it was undefined behavior up through C++03 16.3/10).  Since the `ExecutionEngine/SparseTensorUtils.cpp` file is required to be compile-able under C++98 compatibility mode (unlike the C++11 used elsewhere in MLIR), we shouldn't rely on that behavior.

Also, using a non-empty suffix helps improve uniformity of the API, since all other primary/overhead suffixes are also non-empty.  I'm using the suffix `0` since that's the value used by the `SparseTensorEncoding` attribute for indicating the index overhead-type.

Depends On D126720

Reviewed By: aartbik

Differential Revision: https://reviews.llvm.org/D126724
The file was modifiedmlir/test/Dialect/SparseTensor/sparse_lower_inplace.mlir
The file was modifiedmlir/test/Dialect/SparseTensor/sparse_lower.mlir
The file was modifiedmlir/test/Dialect/SparseTensor/sparse_lower_col.mlir
The file was modifiedmlir/test/Dialect/SparseTensor/conversion.mlir
The file was modifiedmlir/include/mlir/ExecutionEngine/SparseTensorUtils.h
The file was modifiedmlir/lib/Dialect/SparseTensor/Transforms/CodegenUtils.cpp
Commit 902360d21dfb53b00fd2093488972bc422ae7941 by chris.bieneman
Temporarily disabling this test on arm

This is failing on an arm32 builder, and it is going to take me a while
to debug. To not block further progress I'm disabling this test on
arm32 configuraitons.
The file was modifiedllvm/unittests/Object/DXContainerTest.cpp
Commit 6232a8f3d61e5856c17e7b314385e9ea8068cdc1 by springerm
[mlir][sparse][NFC] Switch InitOp to bufferization::AllocTensorOp

Now that we have an AllocTensorOp (previously InitTensorOp) in the bufferization dialect, the InitOp in the sparse dialect is no longer needed.

Differential Revision: https://reviews.llvm.org/D126180
The file was modifiedmlir/test/Integration/Dialect/SparseTensor/CPU/sparse_out_reduction.mlir
The file was modifiedmlir/test/Integration/Dialect/SparseTensor/CPU/sparse_complex64.mlir
The file was modifiedmlir/test/Integration/Dialect/SparseTensor/CPU/sparse_sampled_mm_fusion.mlir
The file was modifiedmlir/test/Integration/Dialect/SparseTensor/CPU/sparse_binary.mlir
The file was modifiedmlir/test/Integration/Dialect/SparseTensor/CPU/sparse_matrix_ops.mlir
The file was modifiedmlir/lib/Dialect/SparseTensor/IR/SparseTensorDialect.cpp
The file was modifiedmlir/test/Integration/Dialect/SparseTensor/CPU/sparse_index.mlir
The file was modifiedmlir/test/Integration/Dialect/SparseTensor/CPU/sparse_out_mult_elt.mlir
The file was modifiedmlir/test/Integration/Dialect/SparseTensor/CPU/sparse_transpose.mlir
The file was modifiedmlir/lib/Dialect/SparseTensor/Transforms/Sparsification.cpp
The file was modifiedmlir/test/Integration/Dialect/SparseTensor/CPU/dense_output.mlir
The file was modifiedmlir/lib/Dialect/Linalg/Transforms/SparseTensorRewriting.cpp
The file was modifiedmlir/test/Integration/Dialect/SparseTensor/CPU/sparse_complex_ops.mlir
The file was modifiedmlir/lib/Dialect/SparseTensor/Transforms/SparseTensorConversion.cpp
The file was modifiedmlir/test/Dialect/SparseTensor/sparse_index.mlir
The file was modifiedmlir/test/Dialect/SparseTensor/sparse_expand.mlir
The file was modifiedmlir/include/mlir/Dialect/SparseTensor/IR/SparseTensorOps.td
The file was modifiedmlir/test/Dialect/SparseTensor/sparse_kernels.mlir
The file was modifiedmlir/test/Dialect/SparseTensor/sparse_out.mlir
The file was modifiedmlir/test/Integration/Dialect/SparseTensor/CPU/sparse_sign.mlir
The file was modifiedmlir/include/mlir/Dialect/Bufferization/IR/BufferizationOps.td
The file was modifiedmlir/test/Integration/Dialect/SparseTensor/CPU/sparse_re_im.mlir
The file was modifiedmlir/test/Dialect/SparseTensor/sparse_fp_ops.mlir
The file was modifiedmlir/test/Integration/Dialect/SparseTensor/python/test_elementwise_add_sparse_output.py
The file was modifiedmlir/test/Dialect/SparseTensor/roundtrip.mlir
The file was modifiedmlir/test/Integration/Dialect/SparseTensor/CPU/sparse_tensor_ops.mlir
The file was modifiedmlir/test/Integration/Dialect/SparseTensor/CPU/sparse_unary.mlir
The file was modifiedmlir/test/Integration/Dialect/SparseTensor/CPU/sparse_vector_ops.mlir
The file was modifiedmlir/lib/Dialect/SparseTensor/Transforms/SparseTensorPasses.cpp
The file was modifiedmlir/test/Dialect/SparseTensor/conversion.mlir
The file was modifiedmlir/test/Integration/Dialect/SparseTensor/taco/tools/mlir_pytaco.py
The file was modifiedmlir/test/Integration/Dialect/SparseTensor/CPU/sparse_complex32.mlir
The file was modifiedmlir/test/Integration/Dialect/SparseTensor/CPU/sparse_matmul.mlir
The file was modifiedmlir/test/Dialect/SparseTensor/invalid.mlir
Commit 8c8a2679a20f621994fa904bcfc68775e7345edc by daltenty
[clang][AIX] add option mdefault-visibility-export-mapping

The option mdefault-visibility-export-mapping is created to allow
mapping default visibility to an explicit shared library export
(e.g. dllexport). Exactly how and if this is manifested is target
dependent (since it depends on how they map dllexport in the IR).

Three values are provided for the option:

* none: the default and behavior without the option, no additional export linkage information is created.
* explicit: add the export for entities with explict default visibility from the source, including RTTI
* all: add the export for all entities with default visibility

This option is useful for targets which do not export symbols as part of
their usual default linkage behaviour (e.g. AIX), such targets
traditionally specified such information in external files (e.g. export
lists), but this mapping allows them to use the visibility information
typically used for this purpose on other (e.g. ELF) platforms.

Reviewed By: MaskRay

Differential Revision: https://reviews.llvm.org/D126340
The file was modifiedclang/lib/CodeGen/ItaniumCXXABI.cpp
The file was addedclang/test/CodeGenCXX/mdefault-visibility-export-mapping-alias.cpp
The file was modifiedclang/include/clang/Basic/LangOptions.h
The file was modifiedclang/lib/Driver/ToolChains/Clang.cpp
The file was addedclang/test/CodeGenCXX/mdefault-visibility-export-mapping.cpp
The file was addedclang/test/CodeGenCXX/mdefault-visibility-export-mapping-rtti.cpp
The file was modifiedclang/lib/CodeGen/CodeGenModule.cpp
The file was modifiedclang/lib/CodeGen/CodeGenModule.h
The file was addedclang/test/CodeGen/mdefault-visibility-export-mapping.c
The file was modifiedclang/include/clang/Driver/Options.td
The file was modifiedclang/docs/UsersManual.rst
The file was modifiedclang/lib/CodeGen/MicrosoftCXXABI.cpp
The file was modifiedclang/include/clang/Basic/LangOptions.def
Commit 909a78b3a430f99518a04ae0bced8f0b9ba6e02a by craig.topper
[RISCV] Use MachineRegisterInfo::use_instr_begin instead of use_begin+getParent. NFCI
The file was modifiedllvm/lib/Target/RISCV/RISCVMergeBaseOffset.cpp
Commit afd2f7e9919737e30f9fae2d3cff892189301a55 by jhuber6
[Binary] Promote OffloadBinary to inherit from Binary

We use the `OffloadBinary` to create binary images of offloading files
and their corresonding metadata. This patch changes this to inherit from
the base `Binary` class. This allows us to create and insepect these
more generically. This patch includes all the necessary glue to
implement this as a new binary format, along with added the magic bytes
we use to distinguish the offloading binary to the `file_magic`
implementation.

Reviewed By: tra

Differential Revision: https://reviews.llvm.org/D126812
The file was modifiedllvm/include/llvm/BinaryFormat/Magic.h
The file was modifiedllvm/lib/BinaryFormat/Magic.cpp
The file was modifiedllvm/lib/Object/ObjectFile.cpp
The file was modifiedllvm/lib/Object/OffloadBinary.cpp
The file was modifiedllvm/include/llvm/Object/Binary.h
The file was modifiedllvm/include/llvm/Object/OffloadBinary.h
The file was modifiedllvm/unittests/Object/OffloadingTest.cpp
The file was modifiedclang/lib/CodeGen/BackendUtil.cpp
The file was modifiedllvm/include/llvm-c/Object.h
The file was modifiedllvm/lib/Object/Binary.cpp
The file was modifiedllvm/lib/Object/Object.cpp
Commit 73020b45407f6c463893c2143df9a3b188c31d88 by a.bataev
Revert "[SLP]Improve shuffles cost estimation where possible."

This reverts commit fd5a6ce9dcb77b7821c95355d73af0b3b2020647 to fix
a crash detected by a buildbot
https://lab.llvm.org/buildbot/#/builders/179/builds/3805/steps/11/logs/stdio.
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/resched.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/AArch64/tsc-s116.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/AArch64/accelerate-vector-functions.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/load-merge.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/alternate-int.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/AArch64/accelerate-vector-functions-inseltpoison.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/PR39774.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/malformed_phis.ll
The file was modifiedllvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/load-merge-inseltpoison.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/alternate-int-inseltpoison.ll
Commit f15add7d93aeabbfa381499a04eae769cc1cf4f0 by listmail
[RISCV] Split fixed-vector-strided-load-store.ll so it can be autogened

I've gotten tired of updating register allocation changes by hand, let's just autogen this even if we have to duplicate it.
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vector-strided-load-store.ll
The file was addedllvm/test/CodeGen/RISCV/rvv/fixed-vector-strided-load-store-asm.ll
Commit eb673be5ac8510646692f82a606a1f2c10f24828 by i
[OMPIRBuilder] Add the support for compare capture

This patch adds the support for `compare capture` in `OMPIRBuilder`.

Reviewed By: jdoerfert

Differential Revision: https://reviews.llvm.org/D120007
The file was modifiedllvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
The file was modifiedllvm/include/llvm/Frontend/OpenMP/OMPIRBuilder.h
The file was modifiedllvm/unittests/Frontend/OpenMPIRBuilderTest.cpp
The file was modifiedclang/lib/CodeGen/CGStmtOpenMP.cpp
Commit 2108f7a243a5018b4ffc09bcbc2a8bdbe3c9a4d1 by i
[Object] Fix namespace style issues in D122069

https://llvm.org/docs/CodingStandards.html#use-namespace-qualifiers-to-implement-previously-declared-functions
The file was modifiedllvm/lib/Object/OffloadBinary.cpp
Commit 1a155ee7de3b62a2fabee86fb470a1554fadc54d by qcolombet
[RegisterClassInfo] Invalidate cached information if ignoreCSRForAllocationOrder changes

Even if CSR list is same between functions, we could have had a different
allocation order if ignoreCSRForAllocationOrder is evaluated differently.
Hence invalidate cached register class information if
ignoreCSRForAllocationOrder changes.

Patch by Srividya Karumuri <srividya_karumuri@apple.com>

Differential Revision: https://reviews.llvm.org/D126565
The file was modifiedllvm/include/llvm/CodeGen/RegisterClassInfo.h
The file was modifiedllvm/lib/CodeGen/RegisterClassInfo.cpp
Commit 8d3dda7624d2003496babf360c90678fe53c4b14 by i
[Polly] Fix -Wreorder-ctor. NFC
The file was modifiedpolly/lib/Transform/MaximalStaticExpansion.cpp
Commit a92ed167f2c98d332ad7ce5b0544444b8e917bc0 by hgreving
[ValueTypes] Define MVTs for v128i2/v64i4 as well as i2 and i4.

Adds MVT::v128i2, MVT::v64i4, and implied MVT::i2, MVT::i4.

Keeps MVT::i2, MVT::i4 lowering actions as expand, which should be
removed once targets set this explicitly.

Adjusts 11 lit tests to reflect slightly different behavior during
DAG combine.

Differential Revision: https://reviews.llvm.org/D125247
The file was modifiedllvm/test/CodeGen/Thumb/srem-seteq-illegal-types.ll
The file was modifiedllvm/utils/TableGen/CodeGenTarget.cpp
The file was modifiedllvm/lib/IR/Function.cpp
The file was modifiedllvm/include/llvm/CodeGen/ValueTypes.td
The file was modifiedllvm/test/CodeGen/X86/srem-seteq-illegal-types.ll
The file was modifiedllvm/test/CodeGen/X86/bitreverse.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/srem-seteq-illegal-types.ll
The file was modifiedllvm/test/CodeGen/AArch64/srem-seteq-illegal-types.ll
The file was modifiedllvm/test/CodeGen/PowerPC/srem-seteq-illegal-types.ll
The file was modifiedllvm/test/CodeGen/Mips/srem-seteq-illegal-types.ll
The file was modifiedllvm/lib/CodeGen/TargetLoweringBase.cpp
The file was modifiedllvm/lib/CodeGen/ValueTypes.cpp
The file was modifiedllvm/utils/TableGen/IntrinsicEmitter.cpp
The file was modifiedllvm/test/CodeGen/ARM/srem-seteq-illegal-types.ll
The file was modifiedllvm/include/llvm/Support/MachineValueType.h
The file was modifiedllvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll
The file was modifiedllvm/test/CodeGen/Thumb2/srem-seteq-illegal-types.ll
The file was modifiedllvm/test/TableGen/intrinsic-pointer-to-any.td
Commit 850d53a197f9ffbf5708b7bd795056335e81e9b7 by Matthias Braun
LTO: Decide upfront whether to use opaque/non-opaque pointer types

LTO code may end up mixing bitcode files from various sources varying in
their use of opaque pointer types. The current strategy to decide
between opaque / typed pointers upon the first bitcode file loaded does
not work here, since we could be loading a non-opaque bitcode file first
and would then be unable to load any files with opaque pointer types
later.

So for LTO this:
- Adds an `lto::Config::OpaquePointer` option and enforces an upfront
  decision between the two modes.
- Adds `-opaque-pointers`/`-no-opaque-pointers` options to the gold
  plugin; disabled by default.
- `--opaque-pointers`/`--no-opaque-pointers` options with
  `-plugin-opt=-opaque-pointers`/`-plugin-opt=-no-opaque-pointers`
  aliases to lld; disabled by default.
- Adds an `-lto-opaque-pointers` option to the `llvm-lto2` tool.
- Changes the clang driver to pass `-plugin-opt=-opaque-pointers` to
  the linker in LTO modes when clang was configured with opaque
  pointers enabled by default.

This fixes https://github.com/llvm/llvm-project/issues/55377

Differential Revision: https://reviews.llvm.org/D125847
The file was modifiedlld/test/ELF/lto/type-merge.ll
The file was modifiedllvm/test/ThinLTO/X86/cfi-unsat.ll
The file was modifiedllvm/test/ThinLTO/X86/import-dsolocal.ll
The file was modifiedlld/test/ELF/lto/type-merge2.ll
The file was modifiedllvm/test/LTO/X86/cfi_jt_aliases.ll
The file was modifiedllvm/test/ThinLTO/X86/index-const-prop-gvref-pie.ll
The file was modifiedlld/test/ELF/lto/discard-value-names.ll
The file was addedclang/test/Driver/lto-no-opaque-pointers.c
The file was modifiedlld/ELF/LTO.cpp
The file was modifiedclang/lib/Driver/ToolChains/CommonArgs.cpp
The file was modifiedlld/ELF/Options.td
The file was modifiedllvm/tools/gold/gold-plugin.cpp
The file was modifiedllvm/test/Analysis/StackSafetyAnalysis/ipa-alias.ll
The file was modifiedllvm/test/LTO/Resolution/X86/comdat.ll
The file was modifiedllvm/test/ThinLTO/X86/devirt_single_hybrid.ll
The file was modifiedllvm/include/llvm/LTO/Config.h
The file was modifiedllvm/test/ThinLTO/X86/import-constant.ll
The file was modifiedllvm/test/ThinLTO/X86/index-const-prop-gvref.ll
The file was modifiedllvm/test/LTO/Resolution/X86/ifunc2.ll
The file was modifiedllvm/test/ThinLTO/X86/devirt_promote.ll
The file was modifiedllvm/test/ThinLTO/X86/reference_non_importable.ll
The file was addedllvm/test/LTO/X86/Inputs/opaque-pointers.ll
The file was modifiedllvm/test/LTO/Resolution/X86/alias-alias.ll
The file was modifiedllvm/test/LTO/Resolution/X86/local-def-dllimport.ll
The file was addedllvm/test/LTO/X86/mix-opaque-typed.ll
The file was modifiedclang/test/Driver/arm-float-abi-lto.c
The file was modifiedlld/ELF/Config.h
The file was modifiedllvm/test/ThinLTO/X86/index-const-prop-linkage.ll
The file was modifiedllvm/test/Analysis/StackSafetyAnalysis/ipa.ll
The file was modifiedlld/test/ELF/lto/wrap-unreferenced-before-codegen.test
The file was modifiedllvm/test/ThinLTO/X86/globals-import-blockaddr.ll
The file was modifiedlld/test/ELF/lto/ltopasses-basic.ll
The file was modifiedllvm/docs/OpaquePointers.rst
The file was modifiedllvm/test/ThinLTO/X86/devirt2.ll
The file was modifiedllvm/test/ThinLTO/X86/Inputs/import-constant.ll
The file was addedclang/test/Driver/lto-opaque-pointers.c
The file was modifiedllvm/test/ThinLTO/X86/devirt-after-icp.ll
The file was modifiedllvm/test/ThinLTO/X86/devirt_check.ll
The file was modifiedclang/test/CodeGen/thinlto-inline-asm2.c
The file was modifiedllvm/test/LTO/X86/type-mapping-bug4.ll
The file was modifiedllvm/test/ThinLTO/X86/cfi-devirt.ll
The file was modifiedllvm/tools/llvm-lto2/llvm-lto2.cpp
The file was modifiedclang/test/Driver/memtag_lto.c
The file was modifiedllvm/test/ThinLTO/X86/funcattrs-prop-unknown.ll
The file was modifiedlld/ELF/Driver.cpp
The file was modifiedllvm/test/ThinLTO/X86/weak_externals.ll
Commit 89b1808a2f45c81d8604b5b2573535be548cdf4a by Matthew.Arsenault
AMDGPU: Fix missing c++ mode comment
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUMCInstLower.h
Commit 09a539e926c016f947383be4b0bb18e4a5aa94d6 by Matthew.Arsenault
AMDGPU: Add release notes about atomic load and store
The file was modifiedllvm/docs/ReleaseNotes.rst
Commit 4cb722acbccd161bdcde49102bc9645587b808ae by Matthew.Arsenault
BranchFolder: Require NoPHIs

The pass doesn't handle SSA and breaks any phis.
The file was modifiedllvm/lib/CodeGen/BranchFolding.cpp
The file was addedllvm/test/CodeGen/AMDGPU/branch-folder-requires-no-phis.mir