Changes

Summary

  1. [RISCV] Update mir tests. (details)
  2. [NFC] Remove redundant setOperationAction. (details)
  3. [MLIR] [Python] Make Attribute and Type hashable (details)
  4. [X86][FP16] Change the order of the operands in complex FMA intrinsics to allow swap between the mul operands. (details)
  5. [demangle] Support for ISO/IEC TS 18661 binary floating point type (details)
  6. [AArch64][SVE][InstCombine] Eliminate redundant chains of tuple get/set (details)
Commit ebc5feb4ed6b1f59a000669030f9639bf1763403 by kai.wang
[RISCV] Update mir tests.
The file was modifiedllvm/test/CodeGen/RISCV/rvv/emergency-slot.mir
The file was modifiedllvm/test/CodeGen/RISCV/rvv/mask-reg-alloc.mir
The file was modifiedllvm/test/CodeGen/RISCV/rvv/reg-coalescing.mir
The file was modifiedllvm/test/CodeGen/RISCV/rvv/commuted-op-indices-regression.mir
The file was modifiedllvm/test/CodeGen/RISCV/rvv/addi-scalable-offset.mir
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vsetvli-insert.mir
The file was modifiedllvm/test/CodeGen/RISCV/rvv/tail-agnostic-impdef-copy.mir
The file was modifiedllvm/test/CodeGen/RISCV/rvv/zvlsseg-spill.mir
The file was modifiedllvm/test/CodeGen/RISCV/rvv/get-vlen-debugloc.mir
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.mir
The file was modifiedllvm/test/CodeGen/RISCV/rvv/zvlsseg-copy.mir
The file was modifiedllvm/test/CodeGen/RISCV/rvv/frameindex-addr.ll
Commit 13207a21a64d3a0f1537cc99efe91d757d51f46c by freddy.ye
[NFC] Remove redundant setOperationAction.

[FROUND,FROUNDEVEN][f32, f64, f128] are set Expand twice.

Differential Revision: https://reviews.llvm.org/D110302
The file was modifiedllvm/lib/CodeGen/TargetLoweringBase.cpp
Commit 47cc166bc023b497bdffe0964d80f15eaee8b7da by john.demme
[MLIR] [Python] Make Attribute and Type hashable

Enables putting types and attributes in sets and in dicts as keys.

Reviewed By: stellaraccident

Differential Revision: https://reviews.llvm.org/D110301
The file was modifiedmlir/test/python/ir/attributes.py
The file was modifiedmlir/test/python/ir/builtin_types.py
The file was modifiedmlir/lib/Bindings/Python/IRCore.cpp
Commit ebec077e07f5d35a870f075fb665c006978d49ea by pengfei.wang
[X86][FP16] Change the order of the operands in complex FMA intrinsics to allow swap between the mul operands.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D109658
The file was modifiedllvm/test/CodeGen/X86/avx512fp16-combine-xor-vfmulc-fadd.ll
The file was modifiedllvm/test/CodeGen/X86/avx512cfma-intrinsics.ll
The file was modifiedllvm/lib/Target/X86/X86InstrAVX512.td
The file was modifiedclang/lib/Headers/avx512fp16intrin.h
The file was modifiedclang/lib/Headers/avx512vlfp16intrin.h
The file was modifiedllvm/lib/Target/X86/X86InstrInfo.cpp
The file was modifiedllvm/test/CodeGen/X86/stack-folding-fp-avx512fp16vl.ll
The file was modifiedllvm/test/CodeGen/X86/stack-folding-fp-avx512fp16.ll
The file was modifiedllvm/test/CodeGen/X86/avx512cfmulsh-instrinsics.ll
The file was modifiedllvm/test/CodeGen/X86/avx512cfmul-intrinsics.ll
The file was modifiedllvm/lib/Target/X86/X86IntrinsicsInfo.h
The file was modifiedllvm/test/CodeGen/X86/avx512fp16-combine-vfmulc-fadd.ll
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
The file was modifiedllvm/lib/Target/X86/X86InstrFragmentsSIMD.td
Commit 1873f3be78a5255df8c36c195f4c778f9f47fc5c by pengfei.wang
[demangle] Support for ISO/IEC TS 18661 binary floating point type

Reviewed By: #libc_abi, ldionne

Differential Revision: https://reviews.llvm.org/D105278
The file was modifiedlibcxxabi/test/test_demangle.pass.cpp
The file was modifiedllvm/include/llvm/Demangle/ItaniumDemangle.h
The file was modifiedlibcxxabi/src/demangle/ItaniumDemangle.h
Commit 3b12282b0ed738f138229993505fbba23cd534a2 by mnadeem
[AArch64][SVE][InstCombine] Eliminate redundant chains of tuple get/set

Differential Revision: https://reviews.llvm.org/D109667

Change-Id: I06a3c28e3658ecda109a3a1b73265828274ab2ea
The file was modifiedllvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
The file was addedllvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-opts-tuple-get.ll